647 lines
21 KiB
C
647 lines
21 KiB
C
/* DKM APIC Driver — APIC discovery + IOAPIC init + LAPIC enable
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* Stage 0, required, depends on "timer", provides "irq" and "apic".
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*
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* 真机路径:
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* 1. LAPIC 使能 + Spurious Interrupt Vector 注册
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* 2. IOAPIC 重定向表初始化: 逐条目编程, 将 ISA IRQ 映射到 vector 0x20-0x2F
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* (兼容 PIC 布局), 逐条目 mask
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* 3. MADT ISO (Interrupt Source Override) 处理: 按 ACPI 规范修正 IRQ→GSI 映射
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* 4. SIPI 多核启动框架 (预留, 未实现)
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*
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* QEMU 兼容:
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* - QEMU 默认只提供 1 个 IOAPIC, 24 条 GSI
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* - 实机可能有多个 IOAPIC, GSI 范围更大
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* - 实机必须处理 MADT ISO (IRQ0→GSI2 等)
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*/
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#include <stdint.h>
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#define DKM_DRIVER_MAGIC 0x444B4D31u
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#define DKM_ABI_VERSION 1u
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typedef unsigned char u8;
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typedef unsigned short u16;
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typedef unsigned int u32;
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typedef unsigned long long u64;
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typedef long long i64;
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#define NULL ((void *)0)
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struct dkm_log_api {
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void (*info)(const char *msg);
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void (*warn)(const char *msg);
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void (*error)(const char *msg);
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void (*panic)(const char *msg);
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};
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struct dkm_kernel_api {
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u32 version;
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u32 size;
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u64 feature_bits;
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const struct dkm_log_api *log;
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const void *mem;
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const void *utsm;
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const void *irq;
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const void *pci;
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const void *dma;
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const void *vfs;
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const void *net;
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const void *timer;
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const void *drr;
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const void *rsdp_address;
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const void *fb_address;
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u64 fb_width;
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u64 fb_height;
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u64 fb_pitch;
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u16 fb_bpp;
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const void *boot_modules_response;
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int (*irq_register)(u8 irq, void *handler);
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u64 hhdm_offset;
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const void *block;
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const void *mmio;
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void *(*mm_map_mmio)(u64 phys, u64 size);
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void (*mm_unmap_mmio)(void *virt, u64 size);
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};
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struct dkm_driver_handle;
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struct dkm_driver_desc {
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u32 magic;
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u16 abi_version;
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u16 desc_size;
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const char *name;
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const char *version;
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const char *vendor;
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u32 driver_class;
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u32 stage;
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u32 flags;
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u32 priority;
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const char *const *depends;
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u32 depends_count;
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const char *const *provides;
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u32 provides_count;
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u64 min_kernel_abi;
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u64 feature_bits;
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u64 reserved0;
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u64 reserved1;
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};
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static const char *const g_depends[] = { "timer" };
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static const char *const g_provides[] = { "irq", "apic" };
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__attribute__((visibility("default"), used))
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const struct dkm_driver_desc driver_desc = {
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.magic = DKM_DRIVER_MAGIC,
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.abi_version = DKM_ABI_VERSION,
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.desc_size = sizeof(struct dkm_driver_desc),
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.name = "apic",
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.version = "0.1.0",
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.vendor = "Deshab",
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.driver_class = 3, /* DKM_CLASS_INTERRUPT */
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.stage = 0,
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.flags = 1, /* DKM_F_REQUIRED */
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.priority = 0,
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.depends = g_depends,
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.depends_count = 1,
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.provides = g_provides,
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.provides_count = 2,
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.min_kernel_abi = 1,
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.feature_bits = 0,
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.reserved0 = 0,
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.reserved1 = 0
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};
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typedef struct __attribute__((packed)) {
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char signature[8];
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u8 checksum;
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char oem_id[6];
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u8 revision;
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u32 rsdt_addr;
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} acpi_rsdp_v1;
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typedef struct __attribute__((packed)) {
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char signature[8];
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u8 checksum;
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char oem_id[6];
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u8 revision;
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u32 rsdt_addr;
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u32 length;
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u64 xsdt_addr;
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u8 ext_checksum;
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u8 reserved[3];
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} acpi_rsdp_v2;
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typedef struct __attribute__((packed)) {
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char signature[4];
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u32 length;
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u8 revision;
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u8 checksum;
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char oem_id[6];
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char oem_table_id[8];
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u32 oem_revision;
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u32 creator_id;
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u32 creator_revision;
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} acpi_sdt_header;
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typedef struct __attribute__((packed)) {
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acpi_sdt_header hdr;
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u32 lapic_addr;
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u32 flags;
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} acpi_madt;
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/* ---- IOAPIC 信息存储（真机多 IOAPIC 支持） ---- */
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#define MAX_IOAPIC 4
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#define MAX_ISO 16
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#define MAX_LAPIC 256
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struct ioapic_info {
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u8 id;
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u32 gsi_base;
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u32 gsi_count; /* 从 IOAPIC VER 寄存器读取: max_redir_entry + 1 */
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u64 mmio_phys; /* IOAPIC MMIO 物理基址 */
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volatile u32 *mmio; /* HHDM/MMIO 窗口映射后的虚拟地址, 0=未映射 */
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};
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struct iso_info {
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u8 bus_source; /* ISA bus source IRQ (0-15) */
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u32 gsi; /* 全局系统中断号 */
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u16 flags; /* 极性/触发模式标志 */
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};
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struct lapic_entry {
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u8 apic_id;
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u32 flags; /* MADT LAPIC flags: bit0=enabled */
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};
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struct madt_info {
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u64 lapic_phys;
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u32 flags;
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u32 lapic_count;
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u32 ioapic_count;
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u32 iso_count;
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struct ioapic_info ioapics[MAX_IOAPIC];
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struct iso_info isos[MAX_ISO];
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struct lapic_entry lapics[MAX_LAPIC];
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};
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static const struct dkm_log_api *g_log;
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static __inline__ void apic_mb(void) {
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__asm__ volatile("" ::: "memory");
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}
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static int memeq(const char *a, const char *b, u32 n) {
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for (u32 i = 0; i < n; i++) {
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if (a[i] != b[i]) return 0;
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}
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return 1;
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}
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static u8 checksum8(const u8 *data, u32 len) {
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u8 sum = 0;
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for (u32 i = 0; i < len; i++) sum += data[i];
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return sum;
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}
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static void log_hex(const char *prefix, u64 val) {
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static const char hex[] = "0123456789abcdef";
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char buf[19];
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u32 pos = 0;
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buf[pos++] = '0';
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buf[pos++] = 'x';
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for (int i = 15; i >= 0; i--) {
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buf[pos++] = hex[(val >> (i * 4)) & 0xf];
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}
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buf[pos] = 0;
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g_log->info(prefix);
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g_log->info(buf);
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}
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static void cpuid(u32 leaf, u32 *a, u32 *b, u32 *c, u32 *d) {
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__asm__ volatile ("cpuid"
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: "=a"(*a), "=b"(*b), "=c"(*c), "=d"(*d)
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: "a"(leaf), "c"(0));
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}
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static u64 rdmsr(u32 msr) {
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u32 lo;
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u32 hi;
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__asm__ volatile ("rdmsr" : "=a"(lo), "=d"(hi) : "c"(msr));
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return ((u64)hi << 32) | lo;
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}
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static int cpu_has_lapic(void) {
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u32 a, b, c, d;
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cpuid(1, &a, &b, &c, &d);
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(void)a;
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(void)b;
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(void)c;
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return (d & (1u << 9)) != 0;
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}
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static const acpi_sdt_header *find_table_from_rsdt(const acpi_sdt_header *rsdt, const char sig[4], u32 entry_size) {
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if (!rsdt || rsdt->length < sizeof(acpi_sdt_header)) return NULL;
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if (checksum8((const u8 *)rsdt, rsdt->length) != 0) return NULL;
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u32 count = (rsdt->length - sizeof(acpi_sdt_header)) / entry_size;
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const u8 *entries = (const u8 *)rsdt + sizeof(acpi_sdt_header);
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for (u32 i = 0; i < count; i++) {
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u64 addr;
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if (entry_size == 4) {
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addr = (u64)((const u32 *)entries)[i];
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} else {
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addr = ((const u64 *)entries)[i];
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}
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if (!addr) continue;
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const acpi_sdt_header *hdr = (const acpi_sdt_header *)(uintptr_t)addr;
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if (hdr->length >= sizeof(acpi_sdt_header) && memeq(hdr->signature, sig, 4)) {
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if (checksum8((const u8 *)hdr, hdr->length) == 0) return hdr;
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}
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}
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return NULL;
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}
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static const acpi_madt *find_madt(const void *rsdp_addr) {
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if (!rsdp_addr) return NULL;
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const acpi_rsdp_v2 *rsdp = (const acpi_rsdp_v2 *)rsdp_addr;
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if (!memeq(rsdp->signature, "RSD PTR ", 8)) return NULL;
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if (checksum8((const u8 *)rsdp, 20) != 0) return NULL;
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if (rsdp->revision >= 2 && rsdp->length >= sizeof(acpi_rsdp_v2) && rsdp->xsdt_addr) {
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if (checksum8((const u8 *)rsdp, rsdp->length) == 0) {
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const acpi_sdt_header *xsdt = (const acpi_sdt_header *)(uintptr_t)rsdp->xsdt_addr;
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const acpi_sdt_header *madt = find_table_from_rsdt(xsdt, "APIC", 8);
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if (madt) return (const acpi_madt *)madt;
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}
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}
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if (rsdp->rsdt_addr) {
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const acpi_sdt_header *rsdt = (const acpi_sdt_header *)(uintptr_t)(u64)rsdp->rsdt_addr;
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const acpi_sdt_header *madt = find_table_from_rsdt(rsdt, "APIC", 4);
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if (madt) return (const acpi_madt *)madt;
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}
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return NULL;
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}
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static void parse_madt_entries(const acpi_madt *madt, struct madt_info *info) {
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const u8 *base = (const u8 *)madt;
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u32 off = (u32)sizeof(acpi_madt);
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while (off + 2 <= madt->hdr.length) {
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const u8 *entry = base + off;
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u8 type = entry[0];
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u8 len = entry[1];
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if (len < 2 || off + len > madt->hdr.length) {
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g_log->warn("[apic] malformed MADT entry");
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return;
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}
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if (type == 0 && len >= 8) {
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/* LAPIC entry */
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u8 apic_id = entry[3];
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u32 flags = *(const u32 *)(const void *)(entry + 4);
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log_hex("[apic] CPU LAPIC id=", apic_id);
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if (flags & 1u) {
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info->lapic_count++;
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if (info->lapic_count <= MAX_LAPIC) {
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info->lapics[info->lapic_count - 1].apic_id = apic_id;
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info->lapics[info->lapic_count - 1].flags = flags;
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}
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}
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} else if (type == 1 && len >= 12) {
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/* IOAPIC entry */
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u8 ioapic_id = entry[2];
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u32 addr = *(const u32 *)(const void *)(entry + 4);
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u32 gsi = *(const u32 *)(const void *)(entry + 8);
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log_hex("[apic] IOAPIC id=", ioapic_id);
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log_hex("[apic] IOAPIC addr=", addr);
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log_hex("[apic] IOAPIC gsi_base=", gsi);
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if (info->ioapic_count < MAX_IOAPIC) {
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struct ioapic_info *io = &info->ioapics[info->ioapic_count];
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io->id = ioapic_id;
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io->gsi_base = gsi;
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io->mmio_phys = (u64)addr;
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io->mmio = (volatile u32 *)(uintptr_t)(u64)addr; /* HHDM 直映射, 后续映射修正 */
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io->gsi_count = 0;
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info->ioapic_count++;
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}
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} else if (type == 2 && len >= 10) {
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/* ISO (Interrupt Source Override) entry */
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u8 source = entry[3];
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u32 gsi = *(const u32 *)(const void *)(entry + 4);
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u16 flags = *(const u16 *)(const void *)(entry + 8);
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info->iso_count++;
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log_hex("[apic] ISO source=", source);
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log_hex("[apic] ISO gsi=", gsi);
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log_hex("[apic] ISO flags=", flags);
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if (info->iso_count <= MAX_ISO) {
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struct iso_info *iso = &info->isos[info->iso_count - 1];
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iso->bus_source = source;
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iso->gsi = gsi;
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iso->flags = flags;
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}
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} else if (type == 5 && len >= 12) {
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u64 override = *(const u64 *)(const void *)(entry + 4);
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info->lapic_phys = override;
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log_hex("[apic] LAPIC override=", override);
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}
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off += len;
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}
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}
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/* ---- IOAPIC MMIO 访问 ---- *
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* IOAPIC 寄存器通过 MMIO 访问, 地址空间为 IOREGSEL(0x00) + IOWIN(0x10).
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* 真机 IOAPIC 地址通常在 0xFEC00000, HHDM 通常覆盖此低 4G 地址。
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* 写入 IOREGSEL 选择寄存器号, 读/写 IOWIN 访问数据。
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*/
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#define IOAPIC_IOREGSEL 0x00
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#define IOAPIC_IOWIN 0x10
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static u32 ioapic_read(volatile u32 *base, u8 reg) {
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base[IOAPIC_IOREGSEL / 4] = (u32)reg;
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apic_mb(); /* 寄存器选择必须先于数据读取 */
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return base[IOAPIC_IOWIN / 4];
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}
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static void ioapic_write(volatile u32 *base, u8 reg, u32 val) {
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base[IOAPIC_IOREGSEL / 4] = (u32)reg;
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apic_mb(); /* 寄存器选择必须先于数据写入 */
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base[IOAPIC_IOWIN / 4] = val;
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}
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/* IOAPIC 重定向表项 (64-bit, 分两次 32-bit 读写)
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* bits 0-7: interrupt vector (0x20-0xFF)
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* bit 8: delivery mode: 0=fixed, 1=lowest, 2=SMI, 4=NMI, 5=INIT, 7=ExtINT
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* bit 9: destination mode: 0=physical, 1=logical
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* bit 10: delivery status (RO)
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* bit 11: polarity: 0=active high, 1=active low
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* bit 12: remote IRR (RO, level-triggered only)
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* bit 13: trigger mode: 0=edge, 1=level
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* bit 14: mask: 0=enabled, 1=masked
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* bit 15: reserved
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* bits 16-55: reserved
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* bits 56-63: destination APIC ID (physical mode) or MDA (logical mode)
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*/
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static u64 ioapic_read_redir(volatile u32 *base, u8 entry) {
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u32 lo = ioapic_read(base, (u8)(0x10 + entry * 2));
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u32 hi = ioapic_read(base, (u8)(0x10 + entry * 2 + 1));
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return ((u64)hi << 32) | (u64)lo;
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}
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static void ioapic_write_redir(volatile u32 *base, u8 entry, u64 val) {
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ioapic_write(base, (u8)(0x10 + entry * 2), (u32)(val & 0xffffffffu));
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ioapic_write(base, (u8)(0x10 + entry * 2 + 1), (u32)(val >> 32));
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}
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/* ---- IOAPIC 初始化 ---- *
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* 逐条目编程重定向表: ISA IRQ→vector 映射 + mask all。
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* 真机关键: 处理 MADT ISO (IRQ0→GSI2 是最常见的 override)。
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* PIC 兼容模式: vector = 0x20 + IRQ (与 PIC remap 布局一致)。
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*
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* **QEMU 无法测试但真机必需的代码路径**:
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* 1. ISO 处理: 真机几乎总有 IRQ0→GSI2 override, QEMU 默认无 override
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* 2. 极性标志: 真机 ISA IRQ0 (timer) 必须设 active-high,
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* 但 ISO 可能指定 active-low (PCIe SCI 等)
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* 3. 多 IOAPIC: 真机可能有 2+ IOAPIC, 每个 GSI 范围不同
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*/
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static void ioapic_init_one(struct ioapic_info *io, u64 hhdm_offset,
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const struct iso_info *isos, u32 iso_count,
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void *(*mm_map_mmio_fn)(u64, u64)) {
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/* 映射 IOAPIC MMIO — 真机地址通常在 0xFECxxxxx, HHDM 通常覆盖,
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* 但使用 mm_map_mmio 更安全 (PCD|PWT 属性) */
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if (mm_map_mmio_fn) {
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void *mapped = mm_map_mmio_fn(io->mmio_phys, 0x1000);
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if (mapped) {
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io->mmio = (volatile u32 *)mapped;
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g_log->info("[apic] IOAPIC mapped via mm_map_mmio");
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} else {
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g_log->warn("[apic] mm_map_mmio failed for IOAPIC; trying HHDM");
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io->mmio = (volatile u32 *)(uintptr_t)(hhdm_offset + io->mmio_phys);
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}
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} else {
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io->mmio = (volatile u32 *)(uintptr_t)(hhdm_offset + io->mmio_phys);
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}
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/* 读取 IOAPIC 版本寄存器获取最大重定向条目数 */
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u32 ver = ioapic_read(io->mmio, 0x01);
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u32 max_redir = ((ver >> 16) & 0xff) + 1;
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io->gsi_count = max_redir;
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log_hex("[apic] IOAPIC VER=", ver);
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log_hex("[apic] IOAPIC max_redir=", max_redir);
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|
|
|
/* 读取 IOAPIC ID 验证 */
|
|
u32 id_reg = ioapic_read(io->mmio, 0x00);
|
|
log_hex("[apic] IOAPIC ID reg=", id_reg);
|
|
|
|
/* 构建默认 ISA IRQ→GSI→vector 映射表 (identity map + ISO override)
|
|
* 默认: GSI = ISA_IRQ (0-15), vector = 0x20 + ISA_IRQ
|
|
* ISO override: 修改特定 IRQ 的 GSI 和极性/触发模式 */
|
|
u32 gsi_to_vector[256]; /* GSI → vector 映射 */
|
|
u32 gsi_flags[256]; /* GSI → polar/trigger flags from ISO */
|
|
for (u32 i = 0; i < 256; i++) {
|
|
gsi_to_vector[i] = 0;
|
|
gsi_flags[i] = 0;
|
|
}
|
|
|
|
/* 先建立 identity 映射: GSI 0-15 → vector 0x20-0x2F */
|
|
for (u32 gsi = 0; gsi < 16; gsi++) {
|
|
gsi_to_vector[gsi] = 0x20 + gsi;
|
|
}
|
|
|
|
/* 应用 ISO override */
|
|
for (u32 i = 0; i < iso_count; i++) {
|
|
const struct iso_info *iso = &isos[i];
|
|
u8 src = iso->bus_source;
|
|
u32 gsi = iso->gsi;
|
|
if (gsi < 256) {
|
|
gsi_to_vector[gsi] = 0x20 + src; /* vector 仍基于 ISA IRQ 编号 */
|
|
gsi_flags[gsi] = iso->flags;
|
|
g_log->info("[apic] ISO: ISA IRQ -> GSI override");
|
|
log_hex("[apic] ISA IRQ=", src);
|
|
log_hex("[apic] GSI=", gsi);
|
|
log_hex("[apic] vector=", 0x20 + src);
|
|
}
|
|
}
|
|
|
|
/* 编程重定向表: 全部 mask, 编入正确的 vector/极性/触发模式/目标 APIC */
|
|
for (u32 pin = 0; pin < max_redir && pin < 256; pin++) {
|
|
u32 gsi = io->gsi_base + pin;
|
|
u64 entry = 0;
|
|
|
|
if (gsi < 256 && gsi_to_vector[gsi] != 0) {
|
|
u32 vec = gsi_to_vector[gsi];
|
|
u16 flags = gsi_flags[gsi];
|
|
|
|
entry = (u64)vec; /* vector */
|
|
/* delivery mode = fixed (0) */
|
|
/* destination mode = physical (0) */
|
|
|
|
/* 极性: bit 11. ISA 默认 active-high (0).
|
|
* ISO flags bit 1: 0=conforms (active-high for ISA), 1=active-low */
|
|
if (flags & 0x03) {
|
|
if (flags & 0x02) entry |= (1ULL << 11); /* active low */
|
|
}
|
|
|
|
/* 触发模式: bit 13. ISA 默认 edge (0).
|
|
* ISO flags bit 3: 0=conforms (edge for ISA), 1=level */
|
|
if (flags & 0x08) {
|
|
if (flags & 0x04) entry |= (1ULL << 13); /* level triggered */
|
|
}
|
|
|
|
/* destination: BSP APIC ID (读自 LAPIC) */
|
|
/* 暂时硬编码 destination = 0 (BSP), 后续从 LAPIC ID 寄存器获取 */
|
|
entry |= (0ULL << 56); /* destination APIC ID = 0 */
|
|
}
|
|
|
|
entry |= (1ULL << 14); /* mask = 1, 所有条目默认屏蔽 */
|
|
|
|
ioapic_write_redir(io->mmio, (u8)pin, entry);
|
|
}
|
|
|
|
g_log->info("[apic] IOAPIC redirect table programmed (all masked)");
|
|
}
|
|
|
|
/* ---- LAPIC 使能 ---- *
|
|
* 真机必须:
|
|
* 1. 写 IA32_APIC_BASE MSR 启用 bit 11 (global enable)
|
|
* 2. 写 LAPIC SVR 寄存器设置 Spurious Interrupt Vector (建议 0xFF)
|
|
* 3. 设置 SVR bit 8 (APIC software enable)
|
|
*
|
|
* **QEMU 无法测试但真机必需**: LAPIC SVR 设置 — QEMU 默认已启用 LAPIC,
|
|
* 但实机 BIOS 可能留 LAPIC 为 software-disable 状态。
|
|
*/
|
|
|
|
static void wrmsr(u32 msr, u64 val) {
|
|
u32 lo = (u32)(val & 0xffffffffu);
|
|
u32 hi = (u32)(val >> 32);
|
|
__asm__ volatile("wrmsr" :: "a"(lo), "d"(hi), "c"(msr));
|
|
}
|
|
|
|
static void lapic_enable(u64 hhdm_offset, u64 lapic_phys) {
|
|
volatile u32 *lapic = (volatile u32 *)(uintptr_t)(hhdm_offset + lapic_phys);
|
|
|
|
/* 确保 IA32_APIC_BASE 的 global enable 和 BSP 位已设置 */
|
|
u64 apic_base = rdmsr(0x1B);
|
|
apic_base |= (1ULL << 11); /* global enable */
|
|
/* 保持 BSP 位不变 (bit 8) */
|
|
wrmsr(0x1B, apic_base);
|
|
g_log->info("[apic] LAPIC global enable set in MSR");
|
|
|
|
/* 读当前 SVR */
|
|
u32 svr = lapic[0xF0 / 4];
|
|
log_hex("[apic] LAPIC SVR before=", svr);
|
|
|
|
/* 设置 Spurious Interrupt Vector = 0xFF + APIC software enable (bit 8) */
|
|
svr = 0xFF | (1u << 8);
|
|
lapic[0xF0 / 4] = svr;
|
|
apic_mb();
|
|
|
|
/* 回读验证 */
|
|
svr = lapic[0xF0 / 4];
|
|
log_hex("[apic] LAPIC SVR after=", svr);
|
|
if (svr & (1u << 8)) {
|
|
g_log->info("[apic] LAPIC software enabled");
|
|
} else {
|
|
g_log->warn("[apic] LAPIC SVR bit8 not set — hardware may not support");
|
|
}
|
|
|
|
/* 读 LAPIC ID 和 version 做诊断 dump */
|
|
log_hex("[apic] LAPIC ID=", lapic[0x20 / 4]);
|
|
log_hex("[apic] LAPIC LDR=", lapic[0xD0 / 4]);
|
|
log_hex("[apic] LAPIC version=", lapic[0x30 / 4]);
|
|
}
|
|
|
|
__attribute__((visibility("default")))
|
|
int driver_init(const struct dkm_kernel_api *api,
|
|
struct dkm_driver_handle *handle) {
|
|
(void)handle;
|
|
|
|
if (!api || !api->log) return -1;
|
|
g_log = api->log;
|
|
|
|
g_log->info("[apic] init begin");
|
|
|
|
if (!api->irq_register) {
|
|
g_log->error("[apic] kernel irq_register missing");
|
|
return -1;
|
|
}
|
|
g_log->info("[apic] kernel IRQ backend present: PIC");
|
|
|
|
if (!cpu_has_lapic()) {
|
|
g_log->warn("[apic] CPUID local APIC not present; PIC fallback active");
|
|
g_log->info("[apic] driver ready");
|
|
return 0;
|
|
}
|
|
g_log->info("[apic] CPUID local APIC present");
|
|
|
|
u64 apic_base = rdmsr(0x1B);
|
|
u64 lapic_phys = apic_base & 0xFFFFF000ULL;
|
|
log_hex("[apic] IA32_APIC_BASE=", apic_base);
|
|
log_hex("[apic] LAPIC phys base=", lapic_phys);
|
|
if (apic_base & (1ULL << 8)) g_log->info("[apic] bootstrap processor");
|
|
if (apic_base & (1ULL << 11)) g_log->info("[apic] LAPIC enabled by firmware");
|
|
|
|
struct madt_info info;
|
|
info.lapic_phys = lapic_phys;
|
|
info.flags = 0;
|
|
info.lapic_count = 0;
|
|
info.ioapic_count = 0;
|
|
info.iso_count = 0;
|
|
|
|
const acpi_madt *madt = find_madt(api->rsdp_address);
|
|
if (madt) {
|
|
g_log->info("[apic] MADT found");
|
|
info.lapic_phys = (u64)madt->lapic_addr;
|
|
info.flags = madt->flags;
|
|
log_hex("[apic] MADT lapic_phys=", info.lapic_phys);
|
|
log_hex("[apic] MADT flags=", info.flags);
|
|
parse_madt_entries(madt, &info);
|
|
log_hex("[apic] CPU LAPIC count=", info.lapic_count);
|
|
log_hex("[apic] IOAPIC count=", info.ioapic_count);
|
|
log_hex("[apic] ISO count=", info.iso_count);
|
|
} else {
|
|
g_log->warn("[apic] MADT not found; PIC fallback active");
|
|
}
|
|
|
|
if (api->hhdm_offset && info.lapic_phys) {
|
|
volatile u32 *lapic = (volatile u32 *)(uintptr_t)(api->hhdm_offset + info.lapic_phys);
|
|
log_hex("[apic] LAPIC ID reg=", lapic[0x20 / 4]);
|
|
log_hex("[apic] LAPIC version reg=", lapic[0x30 / 4]);
|
|
log_hex("[apic] LAPIC SVR reg=", lapic[0xF0 / 4]);
|
|
} else {
|
|
g_log->warn("[apic] HHDM unavailable; skip LAPIC MMIO read");
|
|
}
|
|
|
|
/* ---- LAPIC 使能（真机必需，QEMU 也可安全执行） ---- */
|
|
if (api->hhdm_offset && info.lapic_phys) {
|
|
lapic_enable(api->hhdm_offset, info.lapic_phys);
|
|
}
|
|
|
|
/* ---- IOAPIC 初始化（真机必需，QEMU 也可安全执行） ---- */
|
|
for (u32 i = 0; i < info.ioapic_count; i++) {
|
|
g_log->info("[apic] initializing IOAPIC");
|
|
log_hex("[apic] index=", i);
|
|
ioapic_init_one(&info.ioapics[i], api->hhdm_offset,
|
|
info.isos, info.iso_count,
|
|
api->mm_map_mmio);
|
|
}
|
|
|
|
g_log->info("[apic] discovery + init complete; PIC routing retained as fallback");
|
|
g_log->info("[apic] driver ready");
|
|
return 0;
|
|
}
|
|
|
|
__attribute__((visibility("default")))
|
|
int driver_exit(struct dkm_driver_handle *handle) {
|
|
(void)handle;
|
|
return 0;
|
|
}
|