xyou
efa626ed17
- 用户态共享网络协议栈 CODE/tools/net_stack.h（eth/ARP/IPv4/ICMP/UDP-DNS/TCP static inline，轮询模型） - shell 内建 ping/curl/run 命令；ping.elf/curl.elf 对齐 net_stack.h 真实协议栈 - shell dev_mode 串口镜像（g_serial_mirror）便于自动化验证 - DSK 启动流程：firstInit.txt 双行格式（firstInit + dev_mode），dev_mode=1 触发 shell 自动回归测试 - FirstInit 完成→持久化 USER.CONF + 翻转 firstInit 0->1（保留 dev_mode） - firstInit=1 时 DSK 加载 login.elf 进行用户选择 + 密码校验后再进 desktop - 新增 CODE/login/ 登录应用、CODE/DKM/dkm_shared.h、Logo.png - ahci/e1000/virtio_net/fat32/console_fb 驱动更新；utsm serial/block/dsk_loader 调整 - build.ps1 打包 ping.elf/curl.elf 进 SATA FAT32 根目录 - 移除 CODE/tools/bash（与 shell.elf 重复）
618 lines
20 KiB
C
618 lines
20 KiB
C
/* DKM AHCI Driver — PCI AHCI discovery and ABAR read-only enumeration
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* Stage 1 optional storage driver, depends on "pci" and "irq", provides "block".
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* This first version does not issue DMA commands; it only discovers the HBA
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* and ports so later block I/O can be added safely.
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*/
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#include "../dkm_shared.h"
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static const char *const g_depends[] = { "pci", "irq" };
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static const char *const g_provides[] = { "block" };
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__attribute__((visibility("default"), used))
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const struct dkm_driver_desc driver_desc = {
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.magic = DKM_DRIVER_MAGIC,
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.abi_version = DKM_ABI_VERSION,
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.desc_size = sizeof(struct dkm_driver_desc),
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.name = "ahci",
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.version = "0.1.0",
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.vendor = "Deshab",
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.driver_class = 6, /* DKM_CLASS_STORAGE */
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.stage = 1,
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.flags = 0, /* optional */
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.priority = 0,
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.depends = g_depends,
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.depends_count = 2,
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.provides = g_provides,
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.provides_count = 1,
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.min_kernel_abi = 1,
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.feature_bits = 0,
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.reserved0 = 0,
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.reserved1 = 0
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};
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#define AHCI_CLASS_STORAGE 0x01
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#define AHCI_SUBCLASS_SATA 0x06
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#define AHCI_PROGIF_AHCI 0x01
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#define HBA_CAP 0x00
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#define HBA_GHC 0x04
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#define HBA_IS 0x08
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#define HBA_PI 0x0C
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#define HBA_VS 0x10
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#define HBA_CAP2 0x24
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#define HBA_BOHC 0x28
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#define HBA_PORT_BASE 0x100
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#define HBA_PORT_SIZE 0x80
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#define PxCLB 0x00
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#define PxFB 0x08
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#define PxIS 0x10
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#define PxIE 0x14
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#define PxCMD 0x18
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#define PxTFD 0x20
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#define PxSIG 0x24
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#define PxSSTS 0x28
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#define PxSCTL 0x2C
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#define PxSERR 0x30
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#define PxSACT 0x34
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#define PxCI 0x38
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#define PxSNTF 0x3C
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#define PxFBS 0x40
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#define AHCI_CMD_ST (1u << 0)
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#define AHCI_CMD_FRE (1u << 4)
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#define AHCI_CMD_W (1u << 6)
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#define AHCI_CMD_FR (1u << 14)
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#define AHCI_CMD_CR (1u << 15)
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#define AHCI_CMD_ICC_ACTIVE (1u << 28)
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#define ATA_CMD_IDENTIFY 0xEC
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#define ATA_CMD_IDENTIFY_PACKET 0xA1
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#define ATA_CMD_READ_DMA_EXT 0x25
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#define ATA_CMD_WRITE_DMA_EXT 0x35
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typedef struct __attribute__((packed)) ahci_cmd_header {
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u16 flags;
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u16 prdtl;
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u32 prdbc;
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u32 ctba;
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u32 ctbau;
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u32 reserved[4];
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} ahci_cmd_header;
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typedef struct __attribute__((packed)) ahci_prdt_entry {
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u32 dba;
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u32 dbau;
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u32 reserved;
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u32 dbc_i;
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} ahci_prdt_entry;
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typedef struct __attribute__((packed)) ahci_cmd_table {
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u8 cfis[64];
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u8 acmd[16];
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u8 reserved[48];
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ahci_prdt_entry prdt[1];
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} ahci_cmd_table;
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static const struct dkm_log_api *g_log;
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static volatile u32 *g_abar;
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static u32 g_ready_port = 0xffffffffu;
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static ahci_cmd_header *g_cmd_header;
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static struct dkm_dma_buffer g_cmd_table;
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static struct dkm_dma_buffer g_data;
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static u32 pci_read(u8 bus, u8 dev, u8 func, u8 reg) {
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return dkm_pci_read(bus, dev, func, reg);
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}
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static void pci_write(u8 bus, u8 dev, u8 func, u8 reg, u32 value) {
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dkm_pci_write(bus, dev, func, reg, value);
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}
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static void log_hex(const char *prefix, u64 value) {
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static const char hex[] = "0123456789abcdef";
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char buf[19];
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u32 pos = 0;
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buf[pos++] = '0';
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buf[pos++] = 'x';
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for (int i = 15; i >= 0; i--) {
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buf[pos++] = hex[(value >> (i * 4)) & 0xf];
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}
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buf[pos] = 0;
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g_log->info(prefix);
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g_log->info(buf);
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}
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static void ahci_zero(void *ptr, u32 len) {
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u8 *p = (u8 *)ptr;
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for (u32 i = 0; i < len; i++) p[i] = 0;
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}
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static int ahci_find(u8 *out_bus, u8 *out_dev, u8 *out_func) {
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for (u8 bus = 0; bus < 8; bus++) {
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for (u8 dev = 0; dev < 32; dev++) {
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u32 vd = pci_read(bus, dev, 0, PCI_VENDOR_ID);
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if ((vd & 0xffff) == 0xffff) continue;
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u8 header = (u8)(pci_read(bus, dev, 0, PCI_HEADER) >> 16);
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u8 func_count = (header & 0x80) ? 8 : 1;
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for (u8 func = 0; func < func_count; func++) {
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u32 vd2 = pci_read(bus, dev, func, PCI_VENDOR_ID);
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if ((vd2 & 0xffff) == 0xffff) continue;
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u32 class_reg = pci_read(bus, dev, func, 0x08);
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u8 prog_if = (u8)((class_reg >> 8) & 0xff);
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u8 subclass = (u8)((class_reg >> 16) & 0xff);
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u8 class_code = (u8)((class_reg >> 24) & 0xff);
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if (class_code == AHCI_CLASS_STORAGE &&
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subclass == AHCI_SUBCLASS_SATA &&
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prog_if == AHCI_PROGIF_AHCI) {
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*out_bus = bus;
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*out_dev = dev;
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*out_func = func;
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return 0;
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}
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}
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}
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}
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return -1;
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}
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static const char *sata_sig_name(u32 sig) {
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if (sig == 0x00000101u) return "SATA drive";
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if (sig == 0xEB140101u) return "ATAPI device";
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if (sig == 0xC33C0101u) return "Enclosure mgmt";
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if (sig == 0x96690101u) return "Port multiplier";
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if (sig == 0x00000000u) return "empty/unknown";
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return "unknown signature";
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}
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static void ahci_log_port(u32 port) {
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if (!g_abar || port >= 32) {
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return;
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}
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u32 base = HBA_PORT_BASE + port * HBA_PORT_SIZE;
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u32 ssts = g_abar[(base + PxSSTS) / 4];
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u32 sig = g_abar[(base + PxSIG) / 4];
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u32 cmd = g_abar[(base + PxCMD) / 4];
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u32 tfd = g_abar[(base + PxTFD) / 4];
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u32 serr = g_abar[(base + PxSERR) / 4];
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u32 ci = g_abar[(base + PxCI) / 4];
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u32 sact = g_abar[(base + PxSACT) / 4];
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u32 det = ssts & 0xf;
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u32 spd = (ssts >> 4) & 0xf;
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u32 ipm = (ssts >> 8) & 0xf;
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log_hex("[ahci] port=", port);
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log_hex("[ahci] SSTS=", ssts);
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log_hex("[ahci] DET=", det);
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log_hex("[ahci] SPD=", spd);
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log_hex("[ahci] IPM=", ipm);
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log_hex("[ahci] SIG=", sig);
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g_log->info("[ahci] type");
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g_log->info(sata_sig_name(sig));
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log_hex("[ahci] CMD=", cmd);
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log_hex("[ahci] TFD=", tfd);
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log_hex("[ahci] SERR=", serr);
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log_hex("[ahci] CI=", ci);
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log_hex("[ahci] SACT=", sact);
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}
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static int ahci_stop_port(u32 port) {
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u32 base = HBA_PORT_BASE + port * HBA_PORT_SIZE;
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u32 cmd = g_abar[(base + PxCMD) / 4];
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cmd &= ~AHCI_CMD_ST;
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g_abar[(base + PxCMD) / 4] = cmd;
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/* 实机: 500ms TSC 超时等待 CR 清除 */
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u64 deadline = dkm_rdtsc() + dkm_tsc_per_ms * 500;
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while (dkm_rdtsc() < deadline) {
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cmd = g_abar[(base + PxCMD) / 4];
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if (!(cmd & AHCI_CMD_CR)) break;
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__asm__ volatile("pause");
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}
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cmd &= ~AHCI_CMD_FRE;
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g_abar[(base + PxCMD) / 4] = cmd;
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/* 实机: 500ms TSC 超时等待 FR 清除 */
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deadline = dkm_rdtsc() + dkm_tsc_per_ms * 500;
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while (dkm_rdtsc() < deadline) {
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cmd = g_abar[(base + PxCMD) / 4];
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if (!(cmd & AHCI_CMD_FR)) return 0;
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__asm__ volatile("pause");
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}
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return -1;
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}
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static int ahci_start_port(u32 port) {
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u32 base = HBA_PORT_BASE + port * HBA_PORT_SIZE;
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u32 cmd = g_abar[(base + PxCMD) / 4];
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cmd |= AHCI_CMD_FRE;
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g_abar[(base + PxCMD) / 4] = cmd;
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cmd |= AHCI_CMD_ST;
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g_abar[(base + PxCMD) / 4] = cmd;
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return 0;
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}
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static void ahci_fill_identify_fis(u8 *fis, u8 command) {
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for (u32 i = 0; i < 64; i++) fis[i] = 0;
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fis[0] = 0x27; /* Register H2D FIS */
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fis[1] = 1u << 7; /* command */
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fis[2] = command;
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fis[7] = 1u << 6; /* LBA mode */
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}
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static void ahci_fill_read_fis(u8 *fis, u64 lba, u32 count) {
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ahci_zero(fis, 64);
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fis[0] = 0x27;
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fis[1] = 1u << 7;
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fis[2] = ATA_CMD_READ_DMA_EXT;
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fis[4] = (u8)(lba & 0xff);
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fis[5] = (u8)((lba >> 8) & 0xff);
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fis[6] = (u8)((lba >> 16) & 0xff);
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fis[7] = (1u << 6) | (u8)((lba >> 24) & 0x0f);
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fis[8] = (u8)((lba >> 24) & 0xff);
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fis[9] = (u8)((lba >> 32) & 0xff);
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fis[10] = (u8)((lba >> 40) & 0xff);
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fis[12] = (u8)(count & 0xff);
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fis[13] = (u8)((count >> 8) & 0xff);
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}
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static void ahci_fill_write_fis(u8 *fis, u64 lba, u32 count) {
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ahci_zero(fis, 64);
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fis[0] = 0x27;
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fis[1] = 1u << 7;
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fis[2] = ATA_CMD_WRITE_DMA_EXT;
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fis[4] = (u8)(lba & 0xff);
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fis[5] = (u8)((lba >> 8) & 0xff);
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fis[6] = (u8)((lba >> 16) & 0xff);
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fis[7] = (1u << 6) | (u8)((lba >> 24) & 0x0f);
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fis[8] = (u8)((lba >> 24) & 0xff);
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fis[9] = (u8)((lba >> 32) & 0xff);
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fis[10] = (u8)((lba >> 40) & 0xff);
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fis[12] = (u8)(count & 0xff);
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fis[13] = (u8)((count >> 8) & 0xff);
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}
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static int ahci_read_blocks_internal(u32 port, ahci_cmd_header *hdr, struct dkm_dma_buffer *table, struct dkm_dma_buffer *data, u64 lba, u32 count, void *buffer) {
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if (!buffer || count == 0) return -1;
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if (count > 8) return -2;
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u32 base = HBA_PORT_BASE + port * HBA_PORT_SIZE;
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ahci_cmd_table *tbl = (ahci_cmd_table *)table->virt;
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u32 bytes = count * 512;
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ahci_zero(tbl, sizeof(ahci_cmd_table));
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ahci_zero(data->virt, bytes);
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hdr[0].flags = 5;
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hdr[0].prdtl = 1;
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hdr[0].prdbc = 0;
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hdr[0].ctba = (u32)(table->phys & 0xffffffffu);
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hdr[0].ctbau = (u32)(table->phys >> 32);
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tbl->prdt[0].dba = (u32)(data->phys & 0xffffffffu);
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tbl->prdt[0].dbau = (u32)(data->phys >> 32);
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tbl->prdt[0].dbc_i = (bytes - 1) | (1u << 31);
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ahci_fill_read_fis(tbl->cfis, lba, count);
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g_abar[(base + PxIS) / 4] = 0xffffffffu;
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g_abar[HBA_IS / 4] = (1u << port);
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g_abar[(base + PxCI) / 4] = 1;
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for (u32 i = 0; i < 5000000; i++) {
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if ((g_abar[(base + PxCI) / 4] & 1u) == 0) {
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u8 *dst = (u8 *)buffer;
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u8 *src = (u8 *)data->virt;
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for (u32 j = 0; j < bytes; j++) dst[j] = src[j];
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return 0;
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}
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}
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g_log->warn("[ahci] READ timeout");
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log_hex("[ahci] READ lba=", lba);
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log_hex("[ahci] READ count=", count);
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log_hex("[ahci] READ CI=", g_abar[(base + PxCI) / 4]);
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log_hex("[ahci] READ IS=", g_abar[(base + PxIS) / 4]);
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log_hex("[ahci] READ TFD=", g_abar[(base + PxTFD) / 4]);
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return -3;
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}
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static int ahci_write_blocks_internal(u32 port, ahci_cmd_header *hdr, struct dkm_dma_buffer *table, struct dkm_dma_buffer *data, u64 lba, u32 count, const void *buffer) {
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if (!buffer || count == 0) return -1;
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if (count > 8) return -2;
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u32 base = HBA_PORT_BASE + port * HBA_PORT_SIZE;
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ahci_cmd_table *tbl = (ahci_cmd_table *)table->virt;
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u32 bytes = count * 512;
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ahci_zero(tbl, sizeof(ahci_cmd_table));
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/* copy data from user buffer into DMA buffer */
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{
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u8 *dst = (u8 *)data->virt;
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const u8 *src = (const u8 *)buffer;
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for (u32 j = 0; j < bytes; j++) dst[j] = src[j];
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}
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hdr[0].flags = 5 | (1u << 6); /* CFL=5, W=1 (write) */
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hdr[0].prdtl = 1;
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hdr[0].prdbc = 0;
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hdr[0].ctba = (u32)(table->phys & 0xffffffffu);
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hdr[0].ctbau = (u32)(table->phys >> 32);
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tbl->prdt[0].dba = (u32)(data->phys & 0xffffffffu);
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tbl->prdt[0].dbau = (u32)(data->phys >> 32);
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tbl->prdt[0].dbc_i = (bytes - 1) | (1u << 31);
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ahci_fill_write_fis(tbl->cfis, lba, count);
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/* set PxCMD.W to indicate write direction */
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u32 cmd = g_abar[(base + PxCMD) / 4];
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cmd |= AHCI_CMD_W;
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g_abar[(base + PxCMD) / 4] = cmd;
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g_abar[(base + PxIS) / 4] = 0xffffffffu;
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g_abar[HBA_IS / 4] = (1u << port);
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g_abar[(base + PxCI) / 4] = 1;
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for (u32 i = 0; i < 5000000; i++) {
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if ((g_abar[(base + PxCI) / 4] & 1u) == 0) {
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/* clear PxCMD.W after write completes */
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cmd = g_abar[(base + PxCMD) / 4];
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cmd &= ~AHCI_CMD_W;
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g_abar[(base + PxCMD) / 4] = cmd;
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return 0;
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}
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}
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/* timeout: clear PxCMD.W */
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cmd = g_abar[(base + PxCMD) / 4];
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cmd &= ~AHCI_CMD_W;
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g_abar[(base + PxCMD) / 4] = cmd;
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g_log->warn("[ahci] WRITE timeout");
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log_hex("[ahci] WRITE lba=", lba);
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log_hex("[ahci] WRITE count=", count);
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log_hex("[ahci] WRITE CI=", g_abar[(base + PxCI) / 4]);
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log_hex("[ahci] WRITE IS=", g_abar[(base + PxIS) / 4]);
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log_hex("[ahci] WRITE TFD=", g_abar[(base + PxTFD) / 4]);
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return -3;
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}
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static int ahci_block_read(void *ctx, u64 lba, u32 count, void *buffer) {
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(void)ctx;
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if (g_ready_port == 0xffffffffu || !g_cmd_header) return -1;
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log_hex("[ahci] block_read lba=", lba);
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log_hex("[ahci] block_read count=", count);
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while (count > 0) {
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u32 chunk = count > 8 ? 8 : count;
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int status = ahci_read_blocks_internal(g_ready_port, g_cmd_header, &g_cmd_table, &g_data, lba, chunk, buffer);
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if (status != 0) return status;
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lba += chunk;
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count -= chunk;
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buffer = (void *)((u8 *)buffer + (chunk * 512));
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}
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return 0;
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}
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static int ahci_block_write(void *ctx, u64 lba, u32 count, const void *buffer) {
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(void)ctx;
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if (g_ready_port == 0xffffffffu || !g_cmd_header) return -1;
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/* ensure port is in ST+FRE state */
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u32 base = HBA_PORT_BASE + g_ready_port * HBA_PORT_SIZE;
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u32 cmd = g_abar[(base + PxCMD) / 4];
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if (!(cmd & AHCI_CMD_ST) || !(cmd & AHCI_CMD_FRE)) {
|
|
g_log->warn("[ahci] port not ready; restarting");
|
|
ahci_stop_port(g_ready_port);
|
|
ahci_start_port(g_ready_port);
|
|
}
|
|
while (count > 0) {
|
|
u32 chunk = count > 8 ? 8 : count;
|
|
int status = ahci_write_blocks_internal(g_ready_port, g_cmd_header, &g_cmd_table, &g_data, lba, chunk, buffer);
|
|
if (status != 0) return status;
|
|
lba += chunk;
|
|
count -= chunk;
|
|
buffer = (const void *)((const u8 *)buffer + (chunk * 512));
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
static int ahci_read_lba0(u32 port, ahci_cmd_header *hdr, struct dkm_dma_buffer *table, struct dkm_dma_buffer *data) {
|
|
int status = ahci_read_blocks_internal(port, hdr, table, data, 0, 1, data->virt);
|
|
if (status == 0) {
|
|
log_hex("[ahci] READ LBA0 port=", port);
|
|
log_hex("[ahci] READ LBA0 bytes=", hdr[0].prdbc);
|
|
log_hex("[ahci] READ LBA0 word0=", ((u16 *)data->virt)[0]);
|
|
log_hex("[ahci] READ LBA0 word255=", ((u16 *)data->virt)[255]);
|
|
return 1;
|
|
}
|
|
return status;
|
|
}
|
|
|
|
static int ahci_identify_port(u32 port, const struct dkm_dma_api *dma) {
|
|
if (!dma || !dma->alloc_pages) return -1;
|
|
|
|
u32 base = HBA_PORT_BASE + port * HBA_PORT_SIZE;
|
|
u32 ssts = g_abar[(base + PxSSTS) / 4];
|
|
u32 sig = g_abar[(base + PxSIG) / 4];
|
|
u32 det = ssts & 0xf;
|
|
u32 ipm = (ssts >> 8) & 0xf;
|
|
if (det != 3 || ipm != 1) return 0;
|
|
if (sig != 0x00000101u) {
|
|
g_log->info("[ahci] IDENTIFY skipped non-SATA port");
|
|
log_hex("[ahci] IDENTIFY skip port=", port);
|
|
log_hex("[ahci] IDENTIFY skip sig=", sig);
|
|
return 0;
|
|
}
|
|
|
|
struct dkm_dma_buffer clb;
|
|
struct dkm_dma_buffer fis;
|
|
struct dkm_dma_buffer table;
|
|
struct dkm_dma_buffer data;
|
|
if (dma->alloc_pages(1, 1024, 0x100000000ULL, &clb) != 0) return -2;
|
|
if (dma->alloc_pages(1, 256, 0x100000000ULL, &fis) != 0) return -3;
|
|
if (dma->alloc_pages(1, 128, 0x100000000ULL, &table) != 0) return -4;
|
|
if (dma->alloc_pages(1, 512, 0x100000000ULL, &data) != 0) return -5;
|
|
|
|
if (ahci_stop_port(port) != 0) {
|
|
g_log->warn("[ahci] port stop timeout");
|
|
return -6;
|
|
}
|
|
|
|
g_abar[(base + PxCLB) / 4] = (u32)(clb.phys & 0xffffffffu);
|
|
g_abar[(base + PxCLB + 4) / 4] = (u32)(clb.phys >> 32);
|
|
g_abar[(base + PxFB) / 4] = (u32)(fis.phys & 0xffffffffu);
|
|
g_abar[(base + PxFB + 4) / 4] = (u32)(fis.phys >> 32);
|
|
|
|
ahci_cmd_header *hdr = (ahci_cmd_header *)clb.virt;
|
|
ahci_cmd_table *tbl = (ahci_cmd_table *)table.virt;
|
|
hdr[0].flags = 5; /* FIS length in DWORDS */
|
|
hdr[0].prdtl = 1;
|
|
hdr[0].ctba = (u32)(table.phys & 0xffffffffu);
|
|
hdr[0].ctbau = (u32)(table.phys >> 32);
|
|
tbl->prdt[0].dba = (u32)(data.phys & 0xffffffffu);
|
|
tbl->prdt[0].dbau = (u32)(data.phys >> 32);
|
|
tbl->prdt[0].dbc_i = (512 - 1) | (1u << 31);
|
|
|
|
u8 cmd = ATA_CMD_IDENTIFY;
|
|
ahci_fill_identify_fis(tbl->cfis, cmd);
|
|
|
|
g_abar[(base + PxIS) / 4] = 0xffffffffu;
|
|
g_abar[HBA_IS / 4] = (1u << port);
|
|
ahci_start_port(port);
|
|
|
|
g_abar[(base + PxCI) / 4] = 1;
|
|
for (u32 i = 0; i < 5000000; i++) {
|
|
if ((g_abar[(base + PxCI) / 4] & 1u) == 0) {
|
|
log_hex("[ahci] IDENTIFY port=", port);
|
|
log_hex("[ahci] IDENTIFY status=", g_abar[(base + PxTFD) / 4]);
|
|
log_hex("[ahci] IDENTIFY bytes=", hdr[0].prdbc);
|
|
u16 *id = (u16 *)data.virt;
|
|
log_hex("[ahci] IDENTIFY word0=", id[0]);
|
|
log_hex("[ahci] IDENTIFY word49=", id[49]);
|
|
log_hex("[ahci] IDENTIFY word83=", id[83]);
|
|
ahci_read_lba0(port, hdr, &table, &data);
|
|
g_ready_port = port;
|
|
g_cmd_header = hdr;
|
|
g_cmd_table = table;
|
|
g_data = data;
|
|
return 1;
|
|
}
|
|
}
|
|
|
|
g_log->warn("[ahci] IDENTIFY timeout");
|
|
log_hex("[ahci] IDENTIFY CI=", g_abar[(base + PxCI) / 4]);
|
|
log_hex("[ahci] IDENTIFY IS=", g_abar[(base + PxIS) / 4]);
|
|
log_hex("[ahci] IDENTIFY TFD=", g_abar[(base + PxTFD) / 4]);
|
|
return -7;
|
|
}
|
|
|
|
__attribute__((visibility("default")))
|
|
int driver_init(const struct dkm_kernel_api *api,
|
|
struct dkm_driver_handle *handle) {
|
|
(void)handle;
|
|
/* 实机要求: 先校准 TSC, 再使用基于 CPU 频率的延迟 */
|
|
dkm_tsc_calibrate();
|
|
|
|
if (!api || !api->log) return -1;
|
|
g_log = api->log;
|
|
|
|
g_log->info("[ahci] init begin");
|
|
|
|
u8 bus = 0;
|
|
u8 dev = 0;
|
|
u8 func = 0;
|
|
if (ahci_find(&bus, &dev, &func) != 0) {
|
|
g_log->warn("[ahci] AHCI controller not found");
|
|
g_log->info("[ahci] driver ready");
|
|
return 0;
|
|
}
|
|
|
|
g_log->info("[ahci] AHCI controller found");
|
|
log_hex("[ahci] bus=", bus);
|
|
log_hex("[ahci] dev=", dev);
|
|
log_hex("[ahci] func=", func);
|
|
|
|
u32 vd = pci_read(bus, dev, func, PCI_VENDOR_ID);
|
|
log_hex("[ahci] vendor=", vd & 0xffff);
|
|
log_hex("[ahci] device=", vd >> 16);
|
|
|
|
u32 command = pci_read(bus, dev, func, PCI_COMMAND) & 0xffff;
|
|
command |= PCI_CMD_MEM | PCI_CMD_BUSM;
|
|
pci_write(bus, dev, func, PCI_COMMAND, command);
|
|
log_hex("[ahci] PCI command=", command);
|
|
|
|
u64 abar_phys = (u64)(pci_read(bus, dev, func, PCI_BAR5) & 0xFFFFFFF0u);
|
|
u32 irq_line = pci_read(bus, dev, func, PCI_IRQ_LINE) & 0xff;
|
|
log_hex("[ahci] ABAR phys=", abar_phys);
|
|
log_hex("[ahci] PCI IRQ line=", irq_line);
|
|
|
|
if (!api->hhdm_offset || !abar_phys) {
|
|
g_log->warn("[ahci] missing HHDM or ABAR; skip MMIO enumeration");
|
|
g_log->info("[ahci] driver ready");
|
|
return 0;
|
|
}
|
|
|
|
g_abar = (volatile u32 *)(uintptr_t)(api->hhdm_offset + abar_phys);
|
|
log_hex("[ahci] HHDM offset=", api->hhdm_offset);
|
|
|
|
u32 cap = g_abar[HBA_CAP / 4];
|
|
u32 ghc = g_abar[HBA_GHC / 4];
|
|
u32 is = g_abar[HBA_IS / 4];
|
|
u32 pi = g_abar[HBA_PI / 4];
|
|
u32 vs = g_abar[HBA_VS / 4];
|
|
u32 cap2 = g_abar[HBA_CAP2 / 4];
|
|
u32 bohc = g_abar[HBA_BOHC / 4];
|
|
|
|
log_hex("[ahci] CAP=", cap);
|
|
log_hex("[ahci] GHC=", ghc);
|
|
log_hex("[ahci] IS=", is);
|
|
log_hex("[ahci] PI=", pi);
|
|
log_hex("[ahci] VS=", vs);
|
|
log_hex("[ahci] CAP2=", cap2);
|
|
log_hex("[ahci] BOHC=", bohc);
|
|
log_hex("[ahci] ports count=", (cap & 0x1f) + 1);
|
|
log_hex("[ahci] cmd slots=", ((cap >> 8) & 0x1f) + 1);
|
|
|
|
u32 implemented = 0;
|
|
for (u32 port = 0; port < 32; port++) {
|
|
if (pi & (1u << port)) {
|
|
implemented++;
|
|
ahci_log_port(port);
|
|
}
|
|
}
|
|
log_hex("[ahci] implemented ports=", implemented);
|
|
|
|
u32 identified = 0;
|
|
if (api->dma) {
|
|
for (u32 port = 0; port < 32; port++) {
|
|
if (pi & (1u << port)) {
|
|
int ident = ahci_identify_port(port, api->dma);
|
|
if (ident > 0) {
|
|
identified++;
|
|
break;
|
|
}
|
|
}
|
|
}
|
|
} else {
|
|
g_log->warn("[ahci] DMA API unavailable; skip IDENTIFY");
|
|
}
|
|
log_hex("[ahci] identified ports=", identified);
|
|
if (identified && api->block && api->block->register_device) {
|
|
struct dkm_block_device_desc desc;
|
|
desc.name = "ahci0";
|
|
desc.sector_size = 512;
|
|
desc.sector_count = 0;
|
|
desc.ctx = 0;
|
|
desc.read = ahci_block_read;
|
|
desc.write = ahci_block_write;
|
|
int index = api->block->register_device(&desc);
|
|
log_hex("[ahci] block provider index=", (u64)(i64)index);
|
|
} else if (identified) {
|
|
g_log->warn("[ahci] block API unavailable; provider not registered");
|
|
}
|
|
|
|
g_log->info("[ahci] driver ready");
|
|
return 0;
|
|
}
|
|
|
|
__attribute__((visibility("default")))
|
|
int driver_exit(struct dkm_driver_handle *handle) {
|
|
(void)handle;
|
|
return 0;
|
|
}
|