291 lines
12 KiB
C
291 lines
12 KiB
C
#ifndef UTSM_VMX_H
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#define UTSM_VMX_H
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#include <utsm/types.h>
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/* ===== VMX MSRs ===== */
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#define IA32_VMX_BASIC 0x480
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#define IA32_VMX_PINBASED_CTLS 0x481
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#define IA32_VMX_PROCBASED_CTLS 0x482
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#define IA32_VMX_EXIT_CTLS 0x483
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#define IA32_VMX_ENTRY_CTLS 0x484
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#define IA32_VMX_PROCBASED_CTLS2 0x48B
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#define IA32_VMX_EPT_VPID_CAP 0x48C
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#define IA32_VMX_TRUE_PINBASED_CTLS 0x48D
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#define IA32_VMX_TRUE_PROCBASED_CTLS 0x48E
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#define IA32_VMX_TRUE_EXIT_CTLS 0x48F
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#define IA32_VMX_TRUE_ENTRY_CTLS 0x490
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/* ===== CR4 / CR0 bits ===== */
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#define CR4_VMXE_BIT 13ULL
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#define CR4_VMXE (1ULL << CR4_VMXE_BIT)
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#define CR4_PAE (1ULL << 5)
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#define CR4_PGE (1ULL << 7)
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#define CR4_PSE (1ULL << 4)
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#define CR0_PE (1ULL << 0)
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#define CR0_NE (1ULL << 5)
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#define CR0_WP (1ULL << 16)
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#define CR0_PG (1ULL << 31)
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/* ===== VMCS field encodings (Intel SDM Vol 3, Appendix H) ===== */
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/* Field encoding: bit 13=1 -> host root, bit 12=1 -> guest, bits [11:10] = type, bits [9:1] = index */
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#define VMCS_FIELD_HOST 0x2000ULL
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#define VMCS_FIELD_GUEST 0x1000ULL
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#define VMCS_FIELD_CTRL 0x4000ULL
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#define VMCS_FIELD_READ 0x6000ULL
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/* Control fields */
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#define VMCS_VPID 0x0000
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#define VMCS_GUEST_ES_ADDR 0x0006
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#define VMCS_GUEST_CS_ADDR 0x0008
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#define VMCS_GUEST_SS_ADDR 0x000A
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#define VMCS_GUEST_DS_ADDR 0x000C
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#define VMCS_GUEST_FS_ADDR 0x000E
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#define VMCS_GUEST_GS_ADDR 0x0010
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#define VMCS_GUEST_LDTR_ADDR 0x0012
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#define VMCS_GUEST_TR_ADDR 0x0014
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#define VMCS_GUEST_INTR_STATUS 0x0009
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#define VMCS_IO_BITMAP_A 0x2000
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#define VMCS_IO_BITMAP_B 0x2002
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#define VMCS_MSR_BITMAP 0x2004
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#define VMCS_TSC_OFFSET 0x2010
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#define VMCS_EPT_POINTER 0x201A
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/* Read-only data fields */
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#define VMCS_GUEST_PHYSICAL_ADDR 0x2400
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#define VMCS_EXIT_REASON 0x4402
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#define VMCS_EXIT_QUALIFICATION 0x6400
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#define VMCS_IO_RCX 0x6404
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#define VMCS_IO_RSI 0x6406
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#define VMCS_IO_RDI 0x6408
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#define VMCS_IO_RIP 0x640A
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#define VMCS_GUEST_LINEAR_ADDR 0x640A
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#define VMCS_INSTRUCTION_LENGTH 0x440C
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#define VMCS_VMX_INSTRUCTION_ERROR 0x4406
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/* Guest-state fields */
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#define VMCS_GUEST_ES_SELECTOR 0x0800
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#define VMCS_GUEST_CS_SELECTOR 0x0802
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#define VMCS_GUEST_SS_SELECTOR 0x0804
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#define VMCS_GUEST_DS_SELECTOR 0x0806
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#define VMCS_GUEST_FS_SELECTOR 0x0808
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#define VMCS_GUEST_GS_SELECTOR 0x080A
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#define VMCS_GUEST_LDTR_SELECTOR 0x080C
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#define VMCS_GUEST_TR_SELECTOR 0x080E
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#define VMCS_GUEST_ES_LIMIT 0x4800
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#define VMCS_GUEST_CS_LIMIT 0x4802
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#define VMCS_GUEST_SS_LIMIT 0x4804
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#define VMCS_GUEST_DS_LIMIT 0x4806
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#define VMCS_GUEST_FS_LIMIT 0x4808
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#define VMCS_GUEST_GS_LIMIT 0x480A
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#define VMCS_GUEST_LDTR_LIMIT 0x480C
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#define VMCS_GUEST_TR_LIMIT 0x480E
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#define VMCS_GUEST_CS_ACCESS 0x4816
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#define VMCS_GUEST_SS_ACCESS 0x481A
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#define VMCS_GUEST_DS_ACCESS 0x4818
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#define VMCS_GUEST_ES_ACCESS 0x4814
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#define VMCS_GUEST_FS_ACCESS 0x481C
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#define VMCS_GUEST_GS_ACCESS 0x481E
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#define VMCS_GUEST_LDTR_ACCESS 0x4820
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#define VMCS_GUEST_TR_ACCESS 0x4822
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#define VMCS_GUEST_INTERRUPTIBILITY 0x4824
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#define VMCS_GUEST_ACTIVITY_STATE 0x4826
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#define VMCS_GUEST_SYSENTER_CS 0x482A
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#define VMCS_GUEST_PREEMPTION_TIMER 0x482E
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/* 64-bit guest-state fields（与 PDPTR 共享编码，仅在 EPT 启用时为 EFER/PAT） */
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#define VMCS_GUEST_LINK_POINTER 0x2800 /* P8.4: must be 0xFFFFFFFFFFFFFFFF */
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#define VMCS_GUEST_IA32_EFER 0x2806
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#define VMCS_GUEST_IA32_PAT 0x2804
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#define VMCS_GUEST_IA32_PERF_GLOBAL_CTRL 0x2808
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#define VMCS_GUEST_CR0 0x6800
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#define VMCS_GUEST_CR3 0x6802
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#define VMCS_GUEST_CR4 0x6804
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#define VMCS_GUEST_ES_BASE 0x6806
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#define VMCS_GUEST_CS_BASE 0x6808
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#define VMCS_GUEST_SS_BASE 0x680A
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#define VMCS_GUEST_DS_BASE 0x680C
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#define VMCS_GUEST_FS_BASE 0x680E
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#define VMCS_GUEST_GS_BASE 0x6810
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#define VMCS_GUEST_LDTR_BASE 0x6812
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#define VMCS_GUEST_TR_BASE 0x6814
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#define VMCS_GUEST_GDTR_BASE 0x6816
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#define VMCS_GUEST_GDTR_LIMIT 0x4810
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#define VMCS_GUEST_IDTR_BASE 0x6818
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#define VMCS_GUEST_IDTR_LIMIT 0x4812
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#define VMCS_GUEST_DR7 0x681A
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#define VMCS_GUEST_RSP 0x681C
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#define VMCS_GUEST_RIP 0x681E
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#define VMCS_GUEST_RFLAGS 0x6820
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#define VMCS_GUEST_SYSENTER_ESP 0x6824
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#define VMCS_GUEST_SYSENTER_EIP 0x6826
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/* Host-state fields (Intel SDM Vol 3D, Appendix H, Table H-6) */
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#define VMCS_HOST_CR0 0x6C00
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#define VMCS_HOST_CR3 0x6C02
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#define VMCS_HOST_CR4 0x6C04
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#define VMCS_HOST_ES_SELECTOR 0x0C00
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#define VMCS_HOST_CS_SELECTOR 0x0C02
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#define VMCS_HOST_SS_SELECTOR 0x0C04
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#define VMCS_HOST_DS_SELECTOR 0x0C06
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#define VMCS_HOST_FS_SELECTOR 0x0C08
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#define VMCS_HOST_GS_SELECTOR 0x0C0A
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#define VMCS_HOST_TR_SELECTOR 0x0C0C
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#define VMCS_HOST_FS_BASE 0x6C06
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#define VMCS_HOST_GS_BASE 0x6C08
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#define VMCS_HOST_TR_BASE 0x6C0A
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#define VMCS_HOST_GDTR_BASE 0x6C0C
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#define VMCS_HOST_IDTR_BASE 0x6C0E
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#define VMCS_HOST_SYSENTER_CS 0x4C00
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#define VMCS_HOST_RSP 0x6C14
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#define VMCS_HOST_RIP 0x6C16
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#define VMCS_HOST_SYSENTER_ESP 0x6C10
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#define VMCS_HOST_SYSENTER_EIP 0x6C12
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/* 64-bit host-state fields */
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#define VMCS_HOST_IA32_EFER 0x2C02
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#define VMCS_HOST_IA32_PAT 0x2C00
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#define VMCS_HOST_IA32_PERF_GLOBAL_CTRL 0x2C04
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/* IA32_EFER MSR (0xC0000080) bits */
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#define EFER_SCE (1ULL << 0)
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#define EFER_LME (1ULL << 8)
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#define EFER_LMA (1ULL << 10)
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#define EFER_NXE (1ULL << 11)
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#define EFER_SVME (1ULL << 12)
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#define EFER_LMSLE (1ULL << 13)
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#define EFER_FFXSR (1ULL << 14)
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#define EFER_TCE (1ULL << 15)
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/* VM-execution control fields */
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#define VMCS_PIN_BASED_VM_EXEC_CONTROL 0x4000
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#define VMCS_CPU_BASED_VM_EXEC_CONTROL 0x4002
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#define VMCS_EXCEPTION_BITMAP 0x4004
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#define VMCS_VM_EXIT_CONTROLS 0x400C
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#define VMCS_VM_ENTRY_CONTROLS 0x4012
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#define VMCS_VM_ENTRY_INTERRUPT_INFO 0x4016
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#define VMCS_SECONDARY_VM_EXEC_CONTROL 0x401E
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/* ===== Pin-based controls ===== */
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#define PIN_EXT_INTERRUPT_EXITING (1ULL << 0)
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#define PIN_NMI_EXITING (1ULL << 3)
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#define PIN_VMX_PREEMPTION_TIMER (1ULL << 6)
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/* ===== Primary processor-based controls ===== */
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#define CPU_BASED_INTR_WINDOW_EXITING (1ULL << 2)
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#define CPU_BASED_HLT_EXITING (1ULL << 7)
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#define CPU_BASED_INVLPG_EXITING (1ULL << 9)
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#define CPU_BASED_MWAIT_EXITING (1ULL << 10)
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#define CPU_BASED_RDPMC_EXITING (1ULL << 11)
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#define CPU_BASED_RDTSC_EXITING (1ULL << 12)
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#define CPU_BASED_CR8_LOAD_EXITING (1ULL << 19)
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#define CPU_BASED_CR8_STORE_EXITING (1ULL << 20)
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#define CPU_BASED_MOV_DR_EXITING (1ULL << 23)
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#define CPU_BASED_UNCOND_IO_EXITING (1ULL << 24)
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#define CPU_BASED_USE_IO_BITMAPS (1ULL << 25)
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#define CPU_BASED_PAUSE_EXITING (1ULL << 30)
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#define CPU_BASED_ACTIVATE_SECONDARY (1ULL << 31)
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#define CPU_BASED_USE_MSR_BITMAPS (1ULL << 28)
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/* ===== Secondary processor-based controls ===== */
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#define SEC_EXEC_ENABLE_EPT (1ULL << 1)
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#define SEC_EXEC_ENABLE_VPID (1ULL << 5)
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#define SEC_EXEC_UNRESTRICTED_GUEST (1ULL << 7)
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/* ===== VM-exit controls ===== */
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#define VM_EXIT_SAVE_DEBUG_CONTROLS (1ULL << 2)
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#define VM_EXIT_HOST_ADDR_SPACE_SIZE (1ULL << 9)
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#define VM_EXIT_LOAD_PERF_GLOBAL_CTRL (1ULL << 12)
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#define VM_EXIT_ACK_INTR_ON_EXIT (1ULL << 15)
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#define VM_EXIT_SAVE_GUEST_EFER (1ULL << 20)
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#define VM_EXIT_LOAD_HOST_EFER (1ULL << 21)
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/* ===== VM-entry controls ===== */
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#define VM_ENTRY_LOAD_DEBUG_CONTROLS (1ULL << 2)
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#define VM_ENTRY_IA32E_MODE_GUEST (1ULL << 9)
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#define VM_ENTRY_LOAD_GUEST_EFER (1ULL << 15)
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/* ===== Exit reasons ===== */
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#define EXIT_EXCEPTION_NMI 0
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#define EXIT_EXTERNAL_INTERRUPT 1
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#define EXIT_TRIPLE_FAULT 2
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#define EXIT_INIT_SIGNAL 3
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#define EXIT_INTERRUPT_WINDOW 7
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#define EXIT_CPUID 10
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#define EXIT_INVD 13
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#define EXIT_RDMSR 31
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#define EXIT_WRMSR 32
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#define EXIT_MONITOR 39
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#define EXIT_MWAIT 36
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#define EXIT_VMCALL 18
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#define EXIT_VMCLEAR 19
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#define EXIT_VMLAUNCH 20
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#define EXIT_VMPTRLD 21
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#define EXIT_VMPTRST 22
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#define EXIT_VMREAD 23
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#define EXIT_VMRESUME 24
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#define EXIT_VMWRITE 25
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#define EXIT_VMXOFF 26
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#define EXIT_VMXON 27
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#define EXIT_CONTROL_ACCESS 28
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#define EXIT_IO_INSTRUCTION 30
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#define EXIT_RDPMC 15
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#define EXIT_RDTSC 16
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#define EXIT_HLT 12
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#define EXIT_INVLPG 14
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#define EXIT_EPT_VIOLATION 48
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#define EXIT_EPT_MISCONFIG 49
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#define EXIT_VMX_PREEMPTION_TIMER 52
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#define EXIT_APIC_ACCESS 44
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/* ===== VM-entry interruption-information field 编码 ===== */
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#define VM_ENTRY_INTR_INFO_VALID 0x80000000ULL
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#define VM_ENTRY_INTR_TYPE_HW_IRQ 0 /* external interrupt (bits 10:8) */
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/* ===== EPT memory types ===== */
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#define EPT_MEMORY_TYPE_UC 0ULL
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#define EPT_MEMORY_TYPE_WC 1ULL
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#define EPT_MEMORY_TYPE_WT 4ULL
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#define EPT_MEMORY_TYPE_WP 5ULL
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#define EPT_MEMORY_TYPE_WB 6ULL
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/* ===== EPT entry bits ===== */
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#define EPT_READ (1ULL << 0)
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#define EPT_WRITE (1ULL << 1)
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#define EPT_EXECUTE (1ULL << 2)
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#define EPT_RWX (EPT_READ | EPT_WRITE | EPT_EXECUTE)
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#define EPT_LARGE_PAGE (1ULL << 7)
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/* ===== VMX instruction errors ===== */
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#define VMXERR_VMCALL_INVALID 1
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/* ===== Public API ===== */
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int vmx_supported(void);
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int vmx_enable(void);
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int vmx_disable(void);
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int vmx_vmcs_alloc(u64 *phys_out);
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int vmx_vmcs_load(u64 phys);
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int vmx_vmcs_clear(u64 phys); /* P8.4: VMCLEAR before VMLAUNCH */
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u64 vmx_vmcs_read(u64 field);
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void vmx_vmcs_write(u64 field, u64 value);
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int vmx_vmlaunch(void);
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int vmx_vmresume(void);
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u64 vmx_read_msr(u32 msr);
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u64 vmx_get_host_cr3(void);
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/* ===== 虚拟中断注入（vmexit.c 实现） ===== */
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/* 向 guest 队列注入一个 ISA IRQ 向量（legacy PIC：vector = 0x30 + irq）。
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* 仅排队；实际在下一次 vmresume 前（guest RFLAGS.IF=1 且无阻塞时）注入，
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* 否则 arm interrupt-window exiting，待 guest 可接收时注入。 */
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void vmx_guest_queue_irq(u32 vector);
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/* VMX preemption timer：返回 1ms 对应的 timer 计数值（按 IA32_VMX_BASIC
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* bits[55:48] 的 scale 换算 TSC 频率）。 */
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u64 vmx_preemption_quantum_1ms(void);
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/* 检查 CPU 是否支持 VMX preemption timer。 */
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int vmx_preemption_timer_supported(void);
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#endif
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