xyou
efa626ed17
- 用户态共享网络协议栈 CODE/tools/net_stack.h（eth/ARP/IPv4/ICMP/UDP-DNS/TCP static inline，轮询模型） - shell 内建 ping/curl/run 命令；ping.elf/curl.elf 对齐 net_stack.h 真实协议栈 - shell dev_mode 串口镜像（g_serial_mirror）便于自动化验证 - DSK 启动流程：firstInit.txt 双行格式（firstInit + dev_mode），dev_mode=1 触发 shell 自动回归测试 - FirstInit 完成→持久化 USER.CONF + 翻转 firstInit 0->1（保留 dev_mode） - firstInit=1 时 DSK 加载 login.elf 进行用户选择 + 密码校验后再进 desktop - 新增 CODE/login/ 登录应用、CODE/DKM/dkm_shared.h、Logo.png - ahci/e1000/virtio_net/fat32/console_fb 驱动更新；utsm serial/block/dsk_loader 调整 - build.ps1 打包 ping.elf/curl.elf 进 SATA FAT32 根目录 - 移除 CODE/tools/bash（与 shell.elf 重复）
463 lines
15 KiB
C
463 lines
15 KiB
C
/* DKM e1000 Driver — Intel 8254x Gigabit Ethernet
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* Stage 3, optional, depends on "pci" and "irq", provides "netdev".
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* Finds e1000 via PCI, maps MMIO, reads MAC address.
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*/
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#include "../dkm_shared.h"
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static const char *const g_depends[] = {"pci","irq"};
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static const char *const g_provides[] = {"netdev"};
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__attribute__((visibility("default"), used))
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const struct dkm_driver_desc driver_desc = {
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.magic=DKM_DRIVER_MAGIC,.abi_version=DKM_ABI_VERSION,
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.desc_size=sizeof(struct dkm_driver_desc),
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.name="e1000",.version="0.1.0",.vendor="Deshab",
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.driver_class=9,.stage=3,.flags=0,.priority=0,
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.depends=g_depends,.depends_count=2,
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.provides=g_provides,.provides_count=1,.min_kernel_abi=1,
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};
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/* e1000 MMIO registers */
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#define E1000_CTRL 0x0000
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#define E1000_STATUS 0x0008
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#define E1000_EERD 0x0014
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#define E1000_ICR 0x00C0
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#define E1000_IMS 0x00D0
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#define E1000_IMC 0x00D8
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#define E1000_RAL 0x5400
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#define E1000_RAH 0x5404
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#define E1000_RDBAL 0x2800
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#define E1000_RDBAH 0x2804
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#define E1000_RDLEN 0x2808
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#define E1000_RDH 0x2810
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#define E1000_RDT 0x2818
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#define E1000_RXDCTL 0x2828
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#define E1000_RCTL 0x0100
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#define E1000_TDBAL 0x3800
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#define E1000_TDBAH 0x3804
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#define E1000_TDLEN 0x3808
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#define E1000_TDH 0x3810
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#define E1000_TDT 0x3818
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#define E1000_TXDCTL 0x3828
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#define E1000_TCTL 0x0400
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#define E1000_TIPG 0x0410
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#define E1000_RX_DESC_COUNT 8u
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#define E1000_TX_DESC_COUNT 8u
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#define E1000_RX_BUF_SIZE 2048u
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#define E1000_TX_BUF_SIZE 2048u
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#define E1000_POOL_BYTES(count, size) ((u32)((count) * (size)))
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#define E1000_POOL_PAGES(bytes) (((bytes) + 4095u) / 4096u)
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#define E1000_RCTL_EN (1u << 1)
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#define E1000_RCTL_SBP (1u << 2)
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#define E1000_RCTL_UPE (1u << 3)
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#define E1000_RCTL_MPE (1u << 4)
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#define E1000_RCTL_BAM (1u << 15)
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#define E1000_RCTL_SECRC (1u << 26)
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#define E1000_RCTL_BSIZE_2048 0u
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#define E1000_TCTL_EN (1u << 1)
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#define E1000_TCTL_PSP (1u << 3)
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#define E1000_TCTL_CT_SHIFT 4
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#define E1000_TCTL_COLD_SHIFT 12
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#define E1000_TX_CMD_EOP (1u << 0)
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#define E1000_TX_CMD_IFCS (1u << 1)
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#define E1000_TX_CMD_RS (1u << 3)
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#define E1000_TX_STA_DD (1u << 0)
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#define E1000_RX_STA_DD (1u << 0)
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#define E1000_CTRL_FD (1u << 0)
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#define E1000_CTRL_SLU (1u << 6)
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struct e1000_rx_desc {
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u64 addr;
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u16 length;
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u16 checksum;
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u8 status;
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u8 errors;
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u16 special;
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} __attribute__((packed));
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struct e1000_tx_desc {
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u64 addr;
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u16 length;
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u8 cso;
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u8 cmd;
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u8 status;
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u8 css;
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u16 special;
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} __attribute__((packed));
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static const struct dkm_log_api *g_log;
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static volatile u32 *g_mmio;
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static u64 g_bar0_phys;
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static struct e1000_rx_desc *g_rx_desc;
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static struct e1000_tx_desc *g_tx_desc;
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static u64 g_rx_desc_phys;
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static u64 g_tx_desc_phys;
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static u8 *g_rx_buf[E1000_RX_DESC_COUNT];
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static u64 g_rx_buf_phys[E1000_RX_DESC_COUNT];
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static u8 *g_tx_buf[E1000_TX_DESC_COUNT];
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static u64 g_tx_buf_phys[E1000_TX_DESC_COUNT];
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static u32 g_rx_tail;
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static u32 g_tx_tail;
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static int g_rings_ready;
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#define COM1 0x3F8
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/* 串口发送等待 thin wrapper — 调用 dkm 共享实现 */
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static void serial_wait_tx(void) { dkm_serial_wait_tx(COM1); }
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static void raw_log(const char *s) {
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while (*s) {
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char c = *s++;
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if (c == '\n') {
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serial_wait_tx();
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dkm_outb(COM1, '\r');
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}
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serial_wait_tx();
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dkm_outb(COM1, (u8)c);
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}
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}
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static void raw_hex(const char *prefix, u64 v) {
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static const char h[] = "0123456789abcdef";
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raw_log(prefix);
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raw_log("0x");
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for (int i=15; i>=0; i--) {
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serial_wait_tx();
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dkm_outb(COM1, (u8)h[(v >> (i * 4)) & 0xf]);
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}
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raw_log("\n");
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}
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static u32 pci_read(u8 bus, u8 dev, u8 func, u8 reg) {
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return dkm_pci_read(bus, dev, func, reg);
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}
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static void pci_write(u8 bus, u8 dev, u8 func, u8 reg, u32 v) {
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dkm_pci_write(bus, dev, func, reg, v);
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}
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static int e1000_find(u8 *bus, u8 *dev) {
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for (u8 d=0; d<32; d++) {
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u32 vd = pci_read(0,d,0,PCI_VENDOR_ID);
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if ((vd&0xffff)==0xffff) continue;
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if ((vd&0xffff)!=0x8086) continue;
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u16 did = (u16)(vd>>16);
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/* 82540EM(0x100E) / 82545 等经典 e1000，以及 82574L(0x10D3) e1000e */
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if (did==0x100E || did==0x10D3 || did==0x1004 || did==0x100F ||
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did==0x10D3 || did==0x153A || did==0x1533) {
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*bus=0; *dev=d; return 0;
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}
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}
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return -1;
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}
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/* 读取 EEPROM 一个 16-bit 字（经典 e1000 EERD 接口）。失败返回 0xffff。 */
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static u16 e1000_eeprom_read(u16 addr) {
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/* EERD: bit0=START, addr<<8, 完成后 bit4=DONE, data 在高 16 位 */
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g_mmio[E1000_EERD/4] = ((u32)addr << 8) | 1u;
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/* 实机: 100ms TSC 超时 */
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u64 deadline = dkm_rdtsc() + dkm_tsc_per_ms * 100;
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while (dkm_rdtsc() < deadline) {
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u32 v = g_mmio[E1000_EERD/4];
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if (v & (1u<<4)) return (u16)(v >> 16);
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__asm__ volatile("pause");
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}
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return 0xffff;
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}
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static int irq_handler(u8 irq) {
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(void)irq;
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if (!g_mmio) return 0;
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u32 icr = g_mmio[E1000_ICR/4];
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if (icr) {
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g_mmio[E1000_ICR/4] = icr; /* clear */
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}
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return 0;
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}
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static void copy_bytes(void *dst, const void *src, u32 len) {
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u8 *d = (u8 *)dst;
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const u8 *s = (const u8 *)src;
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for (u32 i=0;i<len;i++) d[i]=s[i];
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}
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static void zero_bytes(void *dst, u32 len) {
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u8 *d = (u8 *)dst;
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for (u32 i=0;i<len;i++) d[i]=0;
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}
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static void mmio_flush(void) {
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if (g_mmio) (void)g_mmio[E1000_STATUS/4];
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}
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static void dma_fence(void) {
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__asm__ volatile("" ::: "memory");
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}
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static int e1000_init_rings(const struct dkm_dma_api *dma) {
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if (!dma || !dma->alloc_pages || !g_mmio) return -1;
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struct dkm_dma_buffer rx_ring, tx_ring;
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if (dma->alloc_pages(1, 16, 0x100000000ULL, &rx_ring) != 0) return -2;
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if (dma->alloc_pages(1, 16, 0x100000000ULL, &tx_ring) != 0) return -3;
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g_rx_desc = (struct e1000_rx_desc *)rx_ring.virt;
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g_tx_desc = (struct e1000_tx_desc *)tx_ring.virt;
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g_rx_desc_phys = rx_ring.phys;
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g_tx_desc_phys = tx_ring.phys;
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for (u32 i=0;i<E1000_RX_DESC_COUNT;i++) {
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struct dkm_dma_buffer b;
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if (dma->alloc_pages(1, 16, 0x100000000ULL, &b) != 0) return -4;
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g_rx_buf[i] = (u8 *)b.virt;
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g_rx_buf_phys[i] = b.phys;
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zero_bytes(&g_rx_desc[i], sizeof(g_rx_desc[i]));
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g_rx_desc[i].addr = b.phys;
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}
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for (u32 i=0;i<E1000_TX_DESC_COUNT;i++) {
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struct dkm_dma_buffer b;
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if (dma->alloc_pages(1, 16, 0x100000000ULL, &b) != 0) return -5;
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g_tx_buf[i] = (u8 *)b.virt;
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g_tx_buf_phys[i] = b.phys;
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zero_bytes(&g_tx_desc[i], sizeof(g_tx_desc[i]));
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g_tx_desc[i].addr = b.phys;
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g_tx_desc[i].status = E1000_TX_STA_DD;
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}
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dma_fence();
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raw_log("[e1000.raw] ring/buffers allocated\n");
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g_mmio[E1000_RCTL/4] = 0;
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g_mmio[E1000_TCTL/4] = 0;
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mmio_flush();
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g_mmio[E1000_RDBAL/4] = (u32)(g_rx_desc_phys & 0xffffffffu);
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g_mmio[E1000_RDBAH/4] = (u32)(g_rx_desc_phys >> 32);
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g_mmio[E1000_RDLEN/4] = E1000_RX_DESC_COUNT * sizeof(struct e1000_rx_desc);
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g_mmio[E1000_RDH/4] = 0;
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g_rx_tail = E1000_RX_DESC_COUNT - 1;
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g_mmio[E1000_RDT/4] = g_rx_tail;
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g_mmio[E1000_TDBAL/4] = (u32)(g_tx_desc_phys & 0xffffffffu);
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g_mmio[E1000_TDBAH/4] = (u32)(g_tx_desc_phys >> 32);
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g_mmio[E1000_TDLEN/4] = E1000_TX_DESC_COUNT * sizeof(struct e1000_tx_desc);
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g_mmio[E1000_TDH/4] = 0;
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g_tx_tail = 0;
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g_mmio[E1000_TDT/4] = 0;
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/* e1000e/部分实现需要显式打开队列描述符控制；经典 e1000 会忽略/兼容。 */
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g_mmio[E1000_RXDCTL/4] = (1u << 25);
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g_mmio[E1000_TXDCTL/4] = (1u << 25);
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g_mmio[E1000_TIPG/4] = 0x0060200Au;
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dma_fence();
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g_mmio[E1000_RCTL/4] = E1000_RCTL_EN | E1000_RCTL_UPE | E1000_RCTL_MPE | E1000_RCTL_BAM | E1000_RCTL_SECRC | E1000_RCTL_BSIZE_2048;
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g_mmio[E1000_TCTL/4] = E1000_TCTL_EN | E1000_TCTL_PSP | (0x0Fu << E1000_TCTL_CT_SHIFT) | (0x40u << E1000_TCTL_COLD_SHIFT);
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mmio_flush();
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g_rings_ready = 1;
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raw_log("[e1000.raw] RX/TX rings initialized\n");
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return 0;
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}
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static int e1000_tx(void *ctx, const void *packet, u32 length) {
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(void)ctx;
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raw_log("[e1000.raw] tx enter\n");
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if (!g_rings_ready || !packet || length == 0 || length > E1000_TX_BUF_SIZE) return -1;
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u32 index = g_tx_tail;
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if (!(g_tx_desc[index].status & E1000_TX_STA_DD)) return -2;
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copy_bytes(g_tx_buf[index], packet, length);
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dma_fence();
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raw_log("[e1000.raw] tx copied\n");
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g_tx_desc[index].length = (u16)length;
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g_tx_desc[index].cso = 0;
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g_tx_desc[index].cmd = E1000_TX_CMD_EOP | E1000_TX_CMD_IFCS | E1000_TX_CMD_RS;
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g_tx_desc[index].css = 0;
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g_tx_desc[index].special = 0;
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g_tx_desc[index].status = 0;
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dma_fence();
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g_tx_tail = (index + 1) % E1000_TX_DESC_COUNT;
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g_mmio[E1000_TDT/4] = g_tx_tail;
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mmio_flush();
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/* 实机: 1秒 TSC 超时等待 TX 完成 */
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u64 deadline = dkm_rdtsc() + dkm_tsc_per_ms * 1000;
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while (dkm_rdtsc() < deadline) {
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dma_fence();
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if (g_tx_desc[index].status & E1000_TX_STA_DD) {
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raw_log("[e1000.raw] tx complete\n");
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return 0;
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}
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__asm__ volatile("pause");
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}
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raw_log("[e1000.raw] tx timeout\n");
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raw_hex("[e1000.raw] STATUS=", g_mmio[E1000_STATUS/4]);
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raw_hex("[e1000.raw] TCTL=", g_mmio[E1000_TCTL/4]);
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raw_hex("[e1000.raw] TDH=", g_mmio[E1000_TDH/4]);
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raw_hex("[e1000.raw] TDT=", g_mmio[E1000_TDT/4]);
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raw_hex("[e1000.raw] desc.status=", g_tx_desc[index].status);
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return -3;
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}
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static int e1000_rx_poll(void *ctx, void *buffer, u32 capacity, u32 *out_length) {
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(void)ctx;
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if (out_length) *out_length = 0;
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if (!g_rings_ready || !buffer || !out_length) return -1;
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u32 next = (g_rx_tail + 1) % E1000_RX_DESC_COUNT;
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dma_fence();
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if (!(g_rx_desc[next].status & E1000_RX_STA_DD)) return 1;
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u32 len = g_rx_desc[next].length;
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if (len > capacity) {
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g_rx_desc[next].status = 0;
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dma_fence();
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g_rx_tail = next;
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g_mmio[E1000_RDT/4] = g_rx_tail;
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mmio_flush();
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return -2;
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}
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copy_bytes(buffer, g_rx_buf[next], len);
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*out_length = len;
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g_rx_desc[next].status = 0;
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dma_fence();
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g_rx_tail = next;
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g_mmio[E1000_RDT/4] = g_rx_tail;
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mmio_flush();
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return 0;
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}
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__attribute__((visibility("default")))
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int driver_init(const struct dkm_kernel_api *api,
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struct dkm_driver_handle *handle) {
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/* 实机要求: 先校准 TSC, 再使用基于 CPU 频率的延迟 */
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dkm_tsc_calibrate();
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raw_log("[e1000.raw] driver_init entered\n");
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(void)handle;
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if (!api||!api->log) return -1;
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g_log=api->log;
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raw_log("[e1000.raw] before find\n");
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u8 bus, dev;
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if (e1000_find(&bus,&dev)!=0) {
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raw_log("[e1000.raw] device not found\n");
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return 0;
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}
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raw_log("[e1000.raw] found device\n");
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u32 cmd = pci_read(bus, dev, 0, PCI_COMMAND);
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cmd |= 0x0007u; /* IO Space | Memory Space | Bus Master */
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pci_write(bus, dev, 0, PCI_COMMAND, cmd);
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raw_log("[e1000.raw] PCI command enabled\n");
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u32 bar0 = pci_read(bus,dev,0,PCI_BAR0);
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if (bar0 & 1u) {
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raw_log("[e1000.raw] IO BAR unsupported\n");
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return 0;
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}
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g_bar0_phys = (u64)(bar0 & 0xFFFFFFF0ULL);
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if ((bar0 & 0x6u) == 0x4u) {
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u32 bar1 = pci_read(bus,dev,0,PCI_BAR1);
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g_bar0_phys |= ((u64)bar1 << 32);
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}
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raw_hex("[e1000.raw] BAR0 raw=", bar0);
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raw_hex("[e1000.raw] BAR0 phys=", g_bar0_phys);
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if (!g_bar0_phys) {
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raw_log("[e1000.raw] BAR0 unavailable\n");
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return 0;
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}
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raw_log("[e1000.raw] BAR0 ok\n");
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u64 hhdm = api->hhdm_offset;
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g_mmio = (volatile u32*)(uintptr_t)(hhdm + g_bar0_phys);
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(void)g_mmio[E1000_STATUS/4];
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raw_log("[e1000.raw] MMIO status read ok\n");
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/* 软件复位，确保 RX/TX/RAL/RAH 从已知状态开始配置。 */
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g_mmio[E1000_CTRL/4] = g_mmio[E1000_CTRL/4] | (1u << 26);
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/* 实机: 1秒 TSC 超时等待复位完成 */
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u64 deadline = dkm_rdtsc() + dkm_tsc_per_ms * 1000;
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while (dkm_rdtsc() < deadline) {
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if (!(g_mmio[E1000_CTRL/4] & (1u << 26))) break;
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__asm__ volatile("pause");
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}
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raw_log("[e1000.raw] reset done\n");
|
|
|
|
u32 ral = g_mmio[E1000_RAL/4];
|
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u32 rah = g_mmio[E1000_RAH/4];
|
|
u8 mac[6];
|
|
mac[0] = (u8)(ral & 0xff);
|
|
mac[1] = (u8)((ral>>8) & 0xff);
|
|
mac[2] = (u8)((ral>>16) & 0xff);
|
|
mac[3] = (u8)((ral>>24) & 0xff);
|
|
mac[4] = (u8)(rah & 0xff);
|
|
mac[5] = (u8)((rah>>8) & 0xff);
|
|
|
|
/* RAL/RAH 为空时从 EEPROM 读 MAC */
|
|
if (ral == 0 && (rah & 0xffff) == 0) {
|
|
u16 w0 = e1000_eeprom_read(0);
|
|
u16 w1 = e1000_eeprom_read(1);
|
|
u16 w2 = e1000_eeprom_read(2);
|
|
if (!(w0==0xffff && w1==0xffff && w2==0xffff)) {
|
|
mac[0]=(u8)(w0&0xff); mac[1]=(u8)(w0>>8);
|
|
mac[2]=(u8)(w1&0xff); mac[3]=(u8)(w1>>8);
|
|
mac[4]=(u8)(w2&0xff); mac[5]=(u8)(w2>>8);
|
|
}
|
|
}
|
|
|
|
/* 仍为全 0 时使用与虚拟机配置一致的回退 MAC，保证收发地址匹配 */
|
|
if (mac[0]==0&&mac[1]==0&&mac[2]==0&&mac[3]==0&&mac[4]==0&&mac[5]==0) {
|
|
mac[0]=0x52; mac[1]=0x54; mac[2]=0x00; mac[3]=0x12; mac[4]=0x34; mac[5]=0x56;
|
|
raw_log("[e1000.raw] using fallback MAC 52:54:00:12:34:56\n");
|
|
}
|
|
|
|
/* 写入 RAL/RAH 并置 AV(bit31) 使能接收该单播地址 */
|
|
g_mmio[E1000_RAL/4] = (u32)mac[0] | ((u32)mac[1]<<8) | ((u32)mac[2]<<16) | ((u32)mac[3]<<24);
|
|
g_mmio[E1000_RAH/4] = (u32)mac[4] | ((u32)mac[5]<<8) | (1u<<31);
|
|
raw_log("[e1000.raw] MAC read ok\n");
|
|
|
|
u32 irq_line = pci_read(bus,dev,0,PCI_IRQ_LINE) & 0xff;
|
|
|
|
g_mmio[E1000_CTRL/4] = g_mmio[E1000_CTRL/4] | E1000_CTRL_FD | E1000_CTRL_SLU;
|
|
raw_log("[e1000.raw] link setup\n");
|
|
|
|
g_mmio[E1000_IMC/4] = 0xffffffffu;
|
|
(void)g_mmio[E1000_ICR/4];
|
|
raw_log("[e1000.raw] interrupts masked\n");
|
|
|
|
int ring_rc = e1000_init_rings(api->dma);
|
|
if (ring_rc != 0) raw_log("[e1000.raw] ring init failed\n");
|
|
|
|
if (api->net && api->net->register_device) {
|
|
struct dkm_net_device_desc netdev;
|
|
netdev.name = "e1000";
|
|
for (int i=0;i<6;i++) netdev.mac[i] = mac[i];
|
|
netdev.flags = DKM_NET_F_LINK_UP;
|
|
if (g_rings_ready) netdev.flags |= DKM_NET_F_TX_READY | DKM_NET_F_RX_READY;
|
|
netdev.ctx = 0;
|
|
netdev.tx = g_rings_ready ? e1000_tx : 0;
|
|
netdev.rx_poll = g_rings_ready ? e1000_rx_poll : 0;
|
|
int net_index = api->net->register_device(&netdev);
|
|
(void)net_index;
|
|
raw_log("[e1000.raw] netdev registered\n");
|
|
} else {
|
|
raw_log("[e1000.raw] net API unavailable\n");
|
|
}
|
|
|
|
g_mmio[E1000_IMC/4] = 0xffffffffu;
|
|
|
|
if (api->irq_register && irq_line < 16) {
|
|
api->irq_register((u8)irq_line, (void*)(uintptr_t)irq_handler);
|
|
raw_log("[e1000.raw] IRQ registered\n");
|
|
}
|
|
|
|
raw_log("[e1000.raw] driver ready\n");
|
|
return 0;
|
|
}
|
|
|
|
__attribute__((visibility("default")))
|
|
int driver_exit(struct dkm_driver_handle *handle) {
|
|
(void)handle; return 0;
|
|
}
|