xyou
f1a2a110d7
Add the current OS source tree, build scripts, system image layout, and development notes covering DMA page allocation, e1000 bring-up, net API dispatch, and DHCP work in progress.
252 lines
7.5 KiB
C
252 lines
7.5 KiB
C
/* DKM PCI Driver — PCI bus enumeration via config space (0xCF8/0xCFC)
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* Stage 0, required, depends on "irq", provides "pci".
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* No IRQ needed for enumeration. Scans all buses/devices/functions.
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*/
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#include <stdint.h>
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/* ---------------------------------------------------------------
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* DKM ABI types
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* --------------------------------------------------------------- */
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#define DKM_DRIVER_MAGIC 0x444B4D31u
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#define DKM_ABI_VERSION 1u
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typedef unsigned char u8;
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typedef unsigned short u16;
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typedef unsigned int u32;
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typedef unsigned long long u64;
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typedef long long i64;
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#define NULL ((void *)0)
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struct dkm_log_api {
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void (*info)(const char *msg);
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void (*warn)(const char *msg);
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void (*error)(const char *msg);
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void (*panic)(const char *msg);
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};
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struct dkm_kernel_api {
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u32 version;
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u32 size;
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u64 feature_bits;
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const struct dkm_log_api *log;
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const void *mem;
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const void *utsm;
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const void *irq;
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const void *pci_api;
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const void *dma;
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const void *vfs;
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const void *net;
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const void *timer;
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const void *drr;
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const void *rsdp_address;
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};
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struct dkm_driver_handle;
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struct dkm_driver_desc {
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u32 magic;
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u16 abi_version;
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u16 desc_size;
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const char *name;
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const char *version;
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const char *vendor;
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u32 driver_class;
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u32 stage;
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u32 flags;
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u32 priority;
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const char *const *depends;
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u32 depends_count;
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const char *const *provides;
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u32 provides_count;
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u64 min_kernel_abi;
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u64 feature_bits;
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u64 reserved0;
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u64 reserved1;
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};
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/* ---------------------------------------------------------------
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* PCI constants
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* --------------------------------------------------------------- */
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#define PCI_CFG_ADDR 0xCF8
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#define PCI_CFG_DATA 0xCFC
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#define PCI_VENDOR_ID 0x00
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#define PCI_DEVICE_ID 0x02
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#define PCI_COMMAND 0x04
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#define PCI_STATUS 0x06
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#define PCI_CLASS 0x0B /* class code */
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#define PCI_SUBCLASS 0x0A /* subclass */
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#define PCI_PROG_IF 0x09 /* prog IF */
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#define PCI_HEADER_TYPE 0x0E
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#define PCI_BAR0 0x10
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/* ---------------------------------------------------------------
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* Driver descriptor
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* --------------------------------------------------------------- */
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static const char *const g_depends[] = { "irq" };
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static const char *const g_provides[] = { "pci" };
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__attribute__((visibility("default"), used))
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const struct dkm_driver_desc driver_desc = {
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.magic = DKM_DRIVER_MAGIC,
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.abi_version = DKM_ABI_VERSION,
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.desc_size = sizeof(struct dkm_driver_desc),
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.name = "pci",
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.version = "0.1.0",
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.vendor = "Deshab",
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.driver_class = 2, /* DKM_CLASS_BUS */
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.stage = 0,
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.flags = 1, /* DKM_F_REQUIRED */
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.priority = 0,
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.depends = g_depends,
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.depends_count = 1,
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.provides = g_provides,
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.provides_count = 1,
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.min_kernel_abi = 1,
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.feature_bits = 0,
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.reserved0 = 0,
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.reserved1 = 0
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};
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/* ---------------------------------------------------------------
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* I/O helpers
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* --------------------------------------------------------------- */
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static const struct dkm_log_api *g_log;
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static __inline__ void outl(u16 port, u32 value) {
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__asm__ volatile ("outl %0, %1" :: "a"(value), "Nd"(port));
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}
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static __inline__ u32 inl(u16 port) {
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u32 value;
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__asm__ volatile ("inl %1, %0" : "=a"(value) : "Nd"(port));
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return value;
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}
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/* ---------------------------------------------------------------
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* PCI config access
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* --------------------------------------------------------------- */
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static u32 pci_cfg_read(u8 bus, u8 dev, u8 func, u8 reg) {
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u32 addr = (u32)((1u << 31)
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| ((u32)bus << 16)
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| ((u32)dev << 11)
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| ((u32)func << 8)
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| ((u32)reg & 0xFC));
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outl(PCI_CFG_ADDR, addr);
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return inl(PCI_CFG_DATA);
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}
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static void pci_cfg_write(u8 bus, u8 dev, u8 func, u8 reg, u32 val) {
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u32 addr = (u32)((1u << 31)
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| ((u32)bus << 16)
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| ((u32)dev << 11)
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| ((u32)func << 8)
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| ((u32)reg & 0xFC));
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outl(PCI_CFG_ADDR, addr);
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outl(PCI_CFG_DATA, val);
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}
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/* ---------------------------------------------------------------
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* Log helpers
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* --------------------------------------------------------------- */
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static void log_hex(const char *prefix, u64 val) {
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static const char hex[] = "0123456789abcdef";
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char buf[19];
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u32 pos = 0;
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buf[pos++] = '0'; buf[pos++] = 'x';
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for (int i = 15; i >= 0; i--) {
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buf[pos++] = hex[(val >> (i * 4)) & 0xf];
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}
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buf[pos] = 0;
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g_log->info(prefix);
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g_log->info(buf);
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}
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static const char *pci_class_name(u8 base, u8 sub) {
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switch (base) {
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case 0x00: return "Legacy";
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case 0x01: return "Storage";
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case 0x02: return "Network";
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case 0x03: return "Display";
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case 0x04: return "Multimedia";
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case 0x05: return "Memory";
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case 0x06: return "Bridge";
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case 0x07: return "SimpleComm";
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case 0x08: return "BasePeriph";
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case 0x09: return "Input";
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case 0x0A: return "Docking";
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case 0x0B: return "CPU";
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case 0x0C: return "SerialBus";
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case 0x0D: return "Wireless";
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case 0x0E: return "IntelligentIO";
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case 0x0F: return "Satellite";
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case 0x10: return "Crypto";
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case 0x11: return "SignalProc";
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case 0x12: return "Accelerator";
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default: return "Unknown";
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}
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(void)sub;
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}
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/* ---------------------------------------------------------------
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* Enumeration
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* --------------------------------------------------------------- */
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static void pci_scan_bus(u8 bus) {
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for (u8 dev = 0; dev < 32; dev++) {
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u32 vid_dev = pci_cfg_read(bus, dev, 0, PCI_VENDOR_ID);
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u16 vendor = (u16)(vid_dev & 0xffff);
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if (vendor == 0xffff) continue;
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u8 header_type = (u8)(pci_cfg_read(bus, dev, 0, PCI_HEADER_TYPE) >> 16);
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int multi_func = (header_type & 0x80) != 0;
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u8 func_count = multi_func ? 8 : 1;
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for (u8 func = 0; func < func_count; func++) {
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u32 vid_dev2 = pci_cfg_read(bus, dev, func, PCI_VENDOR_ID);
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u16 vendor2 = (u16)(vid_dev2 & 0xffff);
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if (vendor2 == 0xffff) continue;
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u16 device = (u16)(vid_dev2 >> 16);
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u32 cc = pci_cfg_read(bus, dev, func, PCI_CLASS);
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u8 class_code = (u8)(cc >> 24);
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u8 subclass = (u8)((cc >> 16) & 0xff);
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g_log->info("[pci]");
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log_hex("[pci] bus=", bus);
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log_hex("[pci] dev=", dev);
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log_hex("[pci] func=", func);
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log_hex("[pci] vendor=", vendor2);
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log_hex("[pci] device=", device);
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g_log->info("[pci] class");
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g_log->info(pci_class_name(class_code, subclass));
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log_hex("[pci] class_hex=", class_code);
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log_hex("[pci] subclass=", subclass);
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}
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}
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}
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/* ---------------------------------------------------------------
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* Driver entry
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* --------------------------------------------------------------- */
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__attribute__((visibility("default")))
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int driver_init(const struct dkm_kernel_api *api,
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struct dkm_driver_handle *handle) {
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(void)handle;
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if (!api || !api->log) return -1;
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g_log = api->log;
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g_log->info("[pci] scanning PCI bus");
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pci_scan_bus(0);
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g_log->info("[pci] driver ready");
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return 0;
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}
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__attribute__((visibility("default")))
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int driver_exit(struct dkm_driver_handle *handle) {
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(void)handle;
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return 0;
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}
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