xyou
f1a2a110d7
Add the current OS source tree, build scripts, system image layout, and development notes covering DMA page allocation, e1000 bring-up, net API dispatch, and DHCP work in progress.
380 lines
12 KiB
C
380 lines
12 KiB
C
/* DKM virtio-net Driver — PCI virtio network discovery
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* Stage 3 optional network driver, depends on "pci" and "irq", provides "netdev".
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* This first version discovers virtio-net devices and logs PCI capabilities;
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* it does not negotiate features, create virtqueues, or transmit packets.
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*/
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#include <stdint.h>
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#define DKM_DRIVER_MAGIC 0x444B4D31u
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#define DKM_ABI_VERSION 1u
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typedef unsigned char u8;
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typedef unsigned short u16;
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typedef unsigned int u32;
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typedef unsigned long long u64;
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typedef long long i64;
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#define NULL ((void *)0)
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struct dkm_log_api {
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void (*info)(const char *msg);
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void (*warn)(const char *msg);
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void (*error)(const char *msg);
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void (*panic)(const char *msg);
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};
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struct dkm_net_device_desc {
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const char *name;
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u8 mac[6];
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u32 flags;
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void *ctx;
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int (*tx)(void *ctx, const void *packet, u32 length);
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int (*rx_poll)(void *ctx, void *buffer, u32 capacity, u32 *out_length);
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};
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struct dkm_net_api {
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int (*register_device)(const struct dkm_net_device_desc *desc);
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u32 (*device_count)(void);
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int (*device_info)(u32 index, void *out);
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};
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#define DKM_NET_F_LINK_UP (1u << 0)
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struct dkm_kernel_api {
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u32 version;
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u32 size;
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u64 feature_bits;
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const struct dkm_log_api *log;
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const void *mem;
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const void *utsm;
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const void *irq;
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const void *pci;
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const void *dma;
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const void *vfs;
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const struct dkm_net_api *net;
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const void *timer;
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const void *drr;
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const void *rsdp_address;
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const void *fb_address;
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u64 fb_width;
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u64 fb_height;
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u64 fb_pitch;
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u16 fb_bpp;
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const void *boot_modules_response;
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int (*irq_register)(u8 irq, void *handler);
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u64 hhdm_offset;
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};
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struct dkm_driver_handle;
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struct dkm_driver_desc {
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u32 magic;
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u16 abi_version;
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u16 desc_size;
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const char *name;
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const char *version;
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const char *vendor;
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u32 driver_class;
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u32 stage;
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u32 flags;
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u32 priority;
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const char *const *depends;
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u32 depends_count;
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const char *const *provides;
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u32 provides_count;
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u64 min_kernel_abi;
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u64 feature_bits;
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u64 reserved0;
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u64 reserved1;
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};
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static const char *const g_depends[] = { "pci", "irq" };
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static const char *const g_provides[] = { "netdev" };
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__attribute__((visibility("default"), used))
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const struct dkm_driver_desc driver_desc = {
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.magic = DKM_DRIVER_MAGIC,
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.abi_version = DKM_ABI_VERSION,
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.desc_size = sizeof(struct dkm_driver_desc),
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.name = "virtio_net",
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.version = "0.1.0",
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.vendor = "Deshab",
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.driver_class = 9, /* DKM_CLASS_NET */
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.stage = 3,
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.flags = 0,
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.priority = 0,
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.depends = g_depends,
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.depends_count = 2,
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.provides = g_provides,
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.provides_count = 1,
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.min_kernel_abi = 1,
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.feature_bits = 0,
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.reserved0 = 0,
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.reserved1 = 0
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};
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#define PCI_ADDR 0xCF8
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#define PCI_DATA 0xCFC
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#define PCI_VENDOR_ID 0x00
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#define PCI_COMMAND 0x04
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#define PCI_CLASS_REG 0x08
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#define PCI_HEADER 0x0E
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#define PCI_CAP_PTR 0x34
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#define PCI_IRQ_LINE 0x3C
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#define PCI_BAR0 0x10
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#define PCI_BAR1 0x14
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#define PCI_BAR2 0x18
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#define PCI_BAR3 0x1C
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#define PCI_BAR4 0x20
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#define PCI_BAR5 0x24
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#define PCI_CMD_IO (1u << 0)
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#define PCI_CMD_MEM (1u << 1)
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#define PCI_CMD_BUSM (1u << 2)
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#define PCI_VENDOR_VIRTIO 0x1AF4u
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#define VIRTIO_TRANS_DEVICE_MIN 0x1000u
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#define VIRTIO_TRANS_DEVICE_MAX 0x103Fu
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#define VIRTIO_MODERN_DEVICE_MIN 0x1040u
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#define VIRTIO_MODERN_DEVICE_MAX 0x107Fu
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#define VIRTIO_NET_DEVICE_ID 1u
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#define VIRTIO_PCI_CAP_COMMON_CFG 1u
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#define VIRTIO_PCI_CAP_NOTIFY_CFG 2u
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#define VIRTIO_PCI_CAP_ISR_CFG 3u
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#define VIRTIO_PCI_CAP_DEVICE_CFG 4u
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#define VIRTIO_PCI_CAP_PCI_CFG 5u
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static const struct dkm_log_api *g_log;
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static __inline__ void outl(u16 port, u32 value) {
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__asm__ volatile ("outl %0, %1" :: "a"(value), "Nd"(port));
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}
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static __inline__ u32 inl(u16 port) {
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u32 value;
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__asm__ volatile ("inl %1, %0" : "=a"(value) : "Nd"(port));
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return value;
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}
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static u32 pci_read(u8 bus, u8 dev, u8 func, u8 reg) {
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u32 addr = (1u << 31)
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| ((u32)bus << 16)
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| ((u32)dev << 11)
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| ((u32)func << 8)
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| ((u32)reg & 0xFC);
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outl(PCI_ADDR, addr);
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return inl(PCI_DATA);
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}
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static void pci_write(u8 bus, u8 dev, u8 func, u8 reg, u32 value) {
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u32 addr = (1u << 31)
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| ((u32)bus << 16)
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| ((u32)dev << 11)
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| ((u32)func << 8)
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| ((u32)reg & 0xFC);
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outl(PCI_ADDR, addr);
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outl(PCI_DATA, value);
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}
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static u8 pci_read8(u8 bus, u8 dev, u8 func, u8 reg) {
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u32 v = pci_read(bus, dev, func, reg);
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return (u8)((v >> ((reg & 3) * 8)) & 0xff);
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}
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static void log_hex(const char *prefix, u64 value) {
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static const char hex[] = "0123456789abcdef";
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char buf[19];
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u32 pos = 0;
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buf[pos++] = '0';
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buf[pos++] = 'x';
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for (int i = 15; i >= 0; i--) {
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buf[pos++] = hex[(value >> (i * 4)) & 0xf];
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}
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buf[pos] = 0;
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g_log->info(prefix);
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g_log->info(buf);
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}
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static u16 virtio_subsystem_id(u16 device_id) {
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if (device_id >= VIRTIO_TRANS_DEVICE_MIN && device_id <= VIRTIO_TRANS_DEVICE_MAX) {
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return (u16)(device_id - VIRTIO_TRANS_DEVICE_MIN);
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}
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if (device_id >= VIRTIO_MODERN_DEVICE_MIN && device_id <= VIRTIO_MODERN_DEVICE_MAX) {
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return (u16)(device_id - VIRTIO_MODERN_DEVICE_MIN);
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}
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return 0xffff;
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}
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static int virtio_net_find(u8 *out_bus, u8 *out_dev, u8 *out_func) {
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for (u8 bus = 0; bus < 16; bus++) {
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for (u8 dev = 0; dev < 32; dev++) {
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u32 vd = pci_read(bus, dev, 0, PCI_VENDOR_ID);
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if ((vd & 0xffff) == 0xffff) continue;
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u8 header = (u8)(pci_read(bus, dev, 0, PCI_HEADER) >> 16);
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u8 func_count = (header & 0x80) ? 8 : 1;
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for (u8 func = 0; func < func_count; func++) {
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u32 vd2 = pci_read(bus, dev, func, PCI_VENDOR_ID);
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u16 vendor = (u16)(vd2 & 0xffff);
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u16 device = (u16)(vd2 >> 16);
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if (vendor != PCI_VENDOR_VIRTIO) continue;
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u16 virtio_id = virtio_subsystem_id(device);
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u32 class_reg = pci_read(bus, dev, func, PCI_CLASS_REG);
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u8 class_code = (u8)(class_reg >> 24);
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if (virtio_id == VIRTIO_NET_DEVICE_ID && class_code == 0x02) {
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*out_bus = bus;
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*out_dev = dev;
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*out_func = func;
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return 0;
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}
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}
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}
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}
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return -1;
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}
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static const char *virtio_cap_name(u8 cfg_type) {
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if (cfg_type == VIRTIO_PCI_CAP_COMMON_CFG) return "common_cfg";
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if (cfg_type == VIRTIO_PCI_CAP_NOTIFY_CFG) return "notify_cfg";
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if (cfg_type == VIRTIO_PCI_CAP_ISR_CFG) return "isr_cfg";
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if (cfg_type == VIRTIO_PCI_CAP_DEVICE_CFG) return "device_cfg";
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if (cfg_type == VIRTIO_PCI_CAP_PCI_CFG) return "pci_cfg";
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return "unknown_cfg";
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}
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static u32 read_bar_raw(u8 bus, u8 dev, u8 func, u8 bar) {
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return pci_read(bus, dev, func, (u8)(PCI_BAR0 + bar * 4));
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}
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static void log_bars(u8 bus, u8 dev, u8 func) {
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for (u8 bar = 0; bar < 6; bar++) {
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u32 raw = read_bar_raw(bus, dev, func, bar);
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if (raw == 0 || raw == 0xffffffffu) continue;
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log_hex("[virtio_net] BAR index=", bar);
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log_hex("[virtio_net] raw=", raw);
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if (raw & 1u) {
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log_hex("[virtio_net] io base=", raw & 0xfffffffcU);
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} else {
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log_hex("[virtio_net] mmio base=", raw & 0xfffffff0U);
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}
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}
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}
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static void log_virtio_caps(u8 bus, u8 dev, u8 func) {
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u8 cap = pci_read8(bus, dev, func, PCI_CAP_PTR) & 0xfc;
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u32 guard = 0;
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u32 found = 0;
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while (cap && guard++ < 32) {
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u8 cap_id = pci_read8(bus, dev, func, cap + 0);
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u8 next = pci_read8(bus, dev, func, cap + 1) & 0xfc;
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if (cap_id == 0x09) {
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u8 cfg_type = pci_read8(bus, dev, func, cap + 3);
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u8 bar = pci_read8(bus, dev, func, cap + 4);
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u32 offset = pci_read(bus, dev, func, cap + 8);
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u32 length = pci_read(bus, dev, func, cap + 12);
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found++;
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g_log->info("[virtio_net] virtio capability");
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g_log->info(virtio_cap_name(cfg_type));
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log_hex("[virtio_net] cap_offset=", cap);
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log_hex("[virtio_net] cfg_type=", cfg_type);
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log_hex("[virtio_net] bar=", bar);
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log_hex("[virtio_net] offset=", offset);
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log_hex("[virtio_net] length=", length);
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if (cfg_type == VIRTIO_PCI_CAP_NOTIFY_CFG) {
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u32 mult = pci_read(bus, dev, func, cap + 16);
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log_hex("[virtio_net] notify_off_multiplier=", mult);
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}
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}
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cap = next;
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}
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log_hex("[virtio_net] virtio cap count=", found);
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if (!found) {
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g_log->warn("[virtio_net] no modern virtio capabilities; transitional IO path expected");
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}
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}
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__attribute__((visibility("default")))
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int driver_init(const struct dkm_kernel_api *api,
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struct dkm_driver_handle *handle) {
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(void)handle;
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if (!api || !api->log) return -1;
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g_log = api->log;
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g_log->info("[virtio_net] init begin");
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u8 bus = 0;
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u8 dev = 0;
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u8 func = 0;
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if (virtio_net_find(&bus, &dev, &func) != 0) {
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g_log->warn("[virtio_net] virtio-net device not found");
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g_log->info("[virtio_net] driver ready");
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return 0;
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}
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g_log->info("[virtio_net] virtio-net device found");
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log_hex("[virtio_net] bus=", bus);
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log_hex("[virtio_net] dev=", dev);
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log_hex("[virtio_net] func=", func);
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u32 vd = pci_read(bus, dev, func, PCI_VENDOR_ID);
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u16 vendor = (u16)(vd & 0xffff);
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u16 device = (u16)(vd >> 16);
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u16 virtio_id = virtio_subsystem_id(device);
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u32 class_reg = pci_read(bus, dev, func, PCI_CLASS_REG);
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u8 revision = (u8)(class_reg & 0xff);
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u8 prog_if = (u8)((class_reg >> 8) & 0xff);
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u8 subclass = (u8)((class_reg >> 16) & 0xff);
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u8 class_code = (u8)((class_reg >> 24) & 0xff);
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log_hex("[virtio_net] vendor=", vendor);
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log_hex("[virtio_net] device=", device);
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log_hex("[virtio_net] virtio_id=", virtio_id);
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log_hex("[virtio_net] class=", class_code);
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log_hex("[virtio_net] subclass=", subclass);
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log_hex("[virtio_net] prog_if=", prog_if);
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log_hex("[virtio_net] revision=", revision);
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u32 command = pci_read(bus, dev, func, PCI_COMMAND) & 0xffff;
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command |= PCI_CMD_IO | PCI_CMD_MEM | PCI_CMD_BUSM;
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pci_write(bus, dev, func, PCI_COMMAND, command);
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log_hex("[virtio_net] PCI command=", command);
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u32 irq_line = pci_read(bus, dev, func, PCI_IRQ_LINE) & 0xff;
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log_hex("[virtio_net] PCI IRQ line=", irq_line);
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log_bars(bus, dev, func);
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log_virtio_caps(bus, dev, func);
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if (api->net && api->net->register_device) {
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struct dkm_net_device_desc netdev;
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netdev.name = "virtio-net";
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for (int i = 0; i < 6; i++) netdev.mac[i] = 0;
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netdev.flags = DKM_NET_F_LINK_UP;
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netdev.ctx = 0;
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netdev.tx = 0;
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netdev.rx_poll = 0;
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int net_index = api->net->register_device(&netdev);
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log_hex("[virtio_net] netdev register rc=", (u64)(i64)net_index);
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} else {
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g_log->warn("[virtio_net] net API unavailable; netdev not registered");
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}
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g_log->info("[virtio_net] discovery only; virtqueues disabled");
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g_log->info("[virtio_net] driver ready");
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return 0;
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}
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__attribute__((visibility("default")))
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int driver_exit(struct dkm_driver_handle *handle) {
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(void)handle;
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return 0;
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}
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