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FUCKYOU

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This commit is contained in:
xyou
2026-07-31 13:53:49 +08:00
parent 5ea84fac97
commit f52157b7af
241 changed files with 26843 additions and 8155 deletions
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CLAUDE.md
+66 -2
View File
@@ -55,6 +55,10 @@ DMP
PCKC
Per-CPU Key Cache
每 CPU 密钥缓存
FUCK
内核启动配置文件
INI 分区格式，控制启动行为/驱动开关/算法参数/桌面行为
```
## 关键设计约束
@@ -81,6 +85,15 @@ SYSTEM/
SYSTEM/driver/manifest.json
内核启动驱动模块清单，控制 ELF .drv 驱动的分阶段加载。
SYSTEM/system/deshab64/FUCK
内核启动配置文件（INI 分区格式），控制启动行为开关、驱动加载开关、UTSM 算法参数、DSK 桌面行为。
UTSM 通过 Limine boot module 预加载读取（cmdline="fuck:config")。
DSK 通过 FAT32 子目录遍历读取（路径 "SYSTEM /DESHAB64 /FUCK ")。
缺失或为空时使用硬编码默认值，行为与无配置文件时一致。
CODE/UTSM/kernel/ini_parser.h / ini_parser.c
UTSM INI 配置解析器，支持分区格式解析、key/value 查询、整型和布尔值便捷获取。
CODE/DKM/README.md
DKM 驱动模块系统说明，记录驱动加载目标、ABI、loader、状态机和实现清单。
@@ -150,5 +163,56 @@ kernel_api 已暴露能力：log, rsdp_address, fb_address/width/height/pitch/bp
4. **网络数据路径**: 在 DMA/IRQ 完成后推进 e1000 RX/TX ring 与 virtio-net feature negotiation/virtqueue/RX-TX。
5. **VFS 与真实块设备接入**: 将 FAT32 从测试镜像迁移到 AHCI/NVMe block provider，完善挂载、读取、目录遍历和错误路径。
6. **DKM 工程化收尾**: 统一驱动本地 ABI 头、清理 warning、补充自动化 QEMU 场景（e1000/virtio-net/nvme/ahci）。
7. **FirstInit 完善**: 修复按键崩溃（fb_text 优化问题）、实现鼠标光标移动、user.conf 写盘（需 block write API）、网络配置界面。
8. **鼠标输入驱动**: 从 mouseInit stub 升级为完整 PS/2 鼠标 IRQ12 + 包解码 + 光标移动。
7. **FirstInit 完善**: ~~修复按键崩溃（fb_text 优化问题）~~（B6 已验证未复现）、~~实现鼠标光标移动~~（M1 已完成）、~~user.conf 写盘~~（已完成）、网络配置界面。
8. ~~**鼠标输入驱动**: 从 mouseInit stub 升级为完整 PS/2 鼠标 IRQ12 + 包解码 + 光标移动~~（M1 已完成）。
## M1 里程碑完成状态（2026-07-29）
### 任务 A: B6 FirstInit 按键崩溃修复
**状态**: [RESOLVED-NOT-REPRODUCIBLE]
**验证结果**:
- QEMU 复现测试完成，系统完整运行 FirstInit 流程无崩溃
- 按键扫描码处理正常，字段输入正确（测试序列: a, b, Enter, shift+comma, Enter, 1, 2, Enter）
- user.conf 成功写入磁盘，firstInit.txt 成功更新为 "1"
- 系统继续加载 desktop
**证据**: `.build_tmp/qemu_serial_b6.log` 串口日志，调试记录 `debug-firstinit-key-crash.md`
**结论**: B6 崩溃在当前构建中未复现，可能已在之前的修改中修复，或崩溃条件较特殊未触发。
### 任务 B: PS/2 鼠标完整实现
**状态**: [COMPLETED]
**实现内容**:
1. **完整初始化序列** (`CODE/mouse/main.c`):
- ps2_drain() 冲刷控制器残留数据
- 读配置字节 → 启用 AUX 时钟/IRQ/翻译 → 写回
- 启用 AUX 端口
- 复位鼠标 → 验证 ACK/自检/设备 ID
- Set Defaults → 采样率 100 → 分辨率 2 → 启用数据报告
- 全程超时保护（100000 次），单步失败只记日志继续
2. **IRQ12 中断处理**:
- 经 kernel_api.irq_register 注册 IRQ12 handler
- 读数据前检查 AUX 位（键盘数据留给键盘路径）
- 3 字节包解码：同步位验证、溢出检测、9 位有符号位移合成
- 坐标累计并钳位到 framebuffer 边界
- 安全不变式：注册但不解屏蔽 PIC，DSK 阶段 IF=0
3. **共享状态接口**:
- `mouse_state_t` 结构体（magic/version/x/y/buttons/计数器/边界）
- `g_mouse_state` 导出全局符号
- `mouse_poll_state()` 只读快照查询接口
**验证结果**:
- mouseInit 初始化成功：`cfg byte=0x47`, `data reporting enabled`, `IRQ12 handler registered`
- FirstInit 中鼠标轮询正常：AUX 端口启用、复位、自检、流模式启用成功
- 鼠标数据包正确接收和解码（串口日志显示 "[mouse] pkt"）
**证据**: `.build_tmp/qemu_serial_mouse.log` 串口日志
**技术要点**:
- 严格遵守"任何单步失败只记日志继续执行，绝不阻塞或崩溃首次启动"准则
- handler 存活性结论：镜像会被后续模块覆盖，IRQ12 保持屏蔽避免野指针执行
- 后续集成路径：DKM 输入驱动 或 DSK 加载器增加"常驻"标志
CODE/DKM/acpi/acpi.c
+180
View File
@@ -103,6 +103,15 @@ typedef struct __attribute__((packed)) {
u32 creator_revision;
} acpi_sdt_header;
/* ACPI Generic Address Structure (GAS) — HPET 等表使用 */
typedef struct __attribute__((packed)) {
u8 space_id; /* 0=SystemMemory, 1=SystemIO, 2=PCIConfig, ... */
u8 bit_width;
u8 bit_offset;
u8 access_size; /* 0=undefined, 1=byte, 2=word, 3=dword, 4=qword */
u64 address;
} acpi_generic_address;
/* ---------------------------------------------------------------
* Driver descriptor
* --------------------------------------------------------------- */
@@ -212,6 +221,168 @@ static const acpi_rsdp_v2 *acpi_find_rsdp(const void *limine_rsdp) {
return NULL;
}
/* ---------------------------------------------------------------
* MCFG (PCIe ECAM Memory-mapped Configuration) 解析
*
* **QEMU 无法测试但真机必需**: PCIe 配置空间通过 ECAM 访问,
* MCFG 表提供 ECAM 基址和总线范围。没有 MCFG 解析,
* 真机无法访问 Bus 0 以外的 PCIe 设备配置空间。
* QEMU 的 PCI 设备都在 Bus 0, 使用传统 CF8/CFC 端口即可。
* --------------------------------------------------------------- */
typedef struct __attribute__((packed)) {
u64 base_address; /* ECAM 基址 (4K 对齐, 256MB per bus) */
u16 pci_segment_group; /* PCI 段组号 (通常为 0) */
u8 start_bus_number; /* 起始总线号 */
u8 end_bus_number; /* 结束总线号 */
u32 reserved;
} mcfg_entry;
typedef struct __attribute__((packed)) {
acpi_sdt_header hdr;
u64 reserved; /* 保留, 通常为 0 */
/* mcfg_entry entries[] 紧跟 */
} mcfg_table;
static void acpi_parse_mcfg(const acpi_sdt_header *hdr) {
if (!hdr || hdr->length < sizeof(mcfg_table)) return;
const mcfg_table *mcfg = (const mcfg_table *)hdr;
u32 entry_size = sizeof(mcfg_entry);
u32 entries_len = mcfg->hdr.length - sizeof(mcfg_table);
u32 count = entries_len / entry_size;
g_log->info("[acpi] MCFG entries:");
log_hex("[acpi] count=", count);
for (u32 i = 0; i < count; i++) {
const mcfg_entry *e = (const mcfg_entry *)((const u8 *)mcfg + sizeof(mcfg_table) + i * entry_size);
log_hex("[acpi] MCFG base=", e->base_address);
log_hex("[acpi] MCFG seg=", e->pci_segment_group);
log_hex("[acpi] MCFG bus_start=", e->start_bus_number);
log_hex("[acpi] MCFG bus_end=", e->end_bus_number);
/* 验证 ECAM 基址合理性 */
if (e->base_address == 0 || e->base_address == 0xFFFFFFFFFFFFFFFFULL) {
g_log->warn("[acpi] MCFG entry has invalid base address");
continue;
}
/* 真机: ECAM 基址通常在 0xB0000000 - 0xBFFFFFFF (3G-4G 范围),
* 但也可能在 4G 以上 (特别是大内存系统) */
if (e->base_address >= 0x100000000ULL) {
g_log->info("[acpi] MCFG base above 4G — requires MMIO mapping");
}
}
}
/* ---------------------------------------------------------------
* HPET (High Precision Event Timer) 解析
*
* 真机需要 HPET 替代 PIT 作为高精度定时器源。
* QEMU 默认也提供 HPET, 但当前内核使用 PIT 即可。
* HPET 信息留作后续高精度定时器实现的参考。
* --------------------------------------------------------------- */
typedef struct __attribute__((packed)) {
u8 hardware_rev_id;
u8 comparator_count : 5;
u8 counter_size : 1; /* 0=32-bit, 1=64-bit */
u8 reserved0 : 1;
u8 legacy_replacement : 1; /* 1=LegacyReplacement IRQ routing available */
u16 pci_vendor_id;
acpi_generic_address address; /* HPET 寄存器基址 */
u8 hpet_number;
u16 minimum_tick;
u8 page_protection;
} hpet_entry_data;
/* HPET 表不含子条目, 只有 1 个 data block */
typedef struct __attribute__((packed)) {
acpi_sdt_header hdr;
u32 event_timer_block_id; /* 与 hpet_entry_data 的前 4 字节相同 */
acpi_generic_address base_address;
u8 hpet_number;
u16 minimum_tick;
u8 page_protection;
} hpet_table;
static void acpi_parse_hpet(const acpi_sdt_header *hdr) {
if (!hdr || hdr->length < sizeof(hpet_table)) return;
const hpet_table *hpet = (const hpet_table *)hdr;
u32 block_id = hpet->event_timer_block_id;
u8 comp_count = (block_id >> 8) & 0x1f;
u8 count_size = (block_id >> 13) & 1;
u8 legacy = (block_id >> 15) & 1;
u8 rev_id = block_id & 0xff;
u16 vendor_id = (block_id >> 16) & 0xffff;
g_log->info("[acpi] HPET info:");
log_hex("[acpi] rev_id=", rev_id);
log_hex("[acpi] comparators=", comp_count);
log_hex("[acpi] counter_size=", count_size ? 64 : 32);
log_hex("[acpi] legacy_irq=", legacy);
log_hex("[acpi] vendor_id=", vendor_id);
log_hex("[acpi] min_tick=", hpet->minimum_tick);
/* HPET 地址空间类型 */
if (hpet->base_address.space_id == 0) {
/* System Memory — MMIO 访问 */
u64 addr = hpet->base_address.address;
log_hex("[acpi] HPET MMIO addr=", addr);
if (addr >= 0x100000000ULL) {
g_log->info("[acpi] HPET base above 4G — requires MMIO mapping");
}
} else if (hpet->base_address.space_id == 1) {
/* System I/O — 端口 I/O */
log_hex("[acpi] HPET I/O port=", hpet->base_address.address);
}
}
/* ---------------------------------------------------------------
* MADT (APIC) 解析 — 为 apic 驱动提供数据
* --------------------------------------------------------------- */
typedef struct __attribute__((packed)) {
acpi_sdt_header hdr;
u32 lapic_addr;
u32 flags;
} acpi_madt;
static void acpi_parse_madt(const acpi_sdt_header *hdr) {
if (!hdr || hdr->length < sizeof(acpi_madt)) return;
const acpi_madt *madt = (const acpi_madt *)hdr;
g_log->info("[acpi] MADT detail:");
log_hex("[acpi] LAPIC addr=", madt->lapic_addr);
log_hex("[acpi] flags=", madt->flags);
if (madt->flags & 1) {
g_log->info("[acpi] PCAT_COMPAT=1 (8259 PIC present)");
}
/* 枚举 MADT 子条目做汇总统计 */
const u8 *base = (const u8 *)madt;
u32 off = sizeof(acpi_madt);
u32 lapic_count = 0, ioapic_count = 0, iso_count = 0, nmi_count = 0;
while (off + 2 <= madt->hdr.length) {
const u8 *entry = base + off;
u8 type = entry[0];
u8 len = entry[1];
if (len < 2 || off + len > madt->hdr.length) break;
if (type == 0) lapic_count++;
else if (type == 1) ioapic_count++;
else if (type == 2) iso_count++;
else if (type == 3 || type == 4) nmi_count++;
off += len;
}
log_hex("[acpi] LAPIC entries=", lapic_count);
log_hex("[acpi] IOAPIC entries=", ioapic_count);
log_hex("[acpi] ISO entries=", iso_count);
log_hex("[acpi] NMI entries=", nmi_count);
}
/* ---------------------------------------------------------------
* Table enumeration
* --------------------------------------------------------------- */
@@ -241,6 +412,15 @@ static void acpi_enumerate_rsdt(const acpi_sdt_header *rsdt, u32 entry_size) {
g_log->info(sig);
log_hex("[acpi] addr=", addr);
log_hex("[acpi] len =", (u64)hdr->length);
/* 对关键表做详细解析 */
if (sig[0]=='A' && sig[1]=='P' && sig[2]=='I' && sig[3]=='C') {
acpi_parse_madt(hdr);
} else if (sig[0]=='M' && sig[1]=='C' && sig[2]=='F' && sig[3]=='G') {
acpi_parse_mcfg(hdr);
} else if (sig[0]=='H' && sig[1]=='P' && sig[2]=='E' && sig[3]=='T') {
acpi_parse_hpet(hdr);
}
}
}
CODE/DKM/ahci/ahci.c
+102 -20
View File
@@ -5,6 +5,13 @@
*/
#include "../dkm_shared.h"
#include "../dkm_instr.h"
DKM_STAT_DECL(ahci_port_found);
DKM_STAT_DECL(ahci_identify_ok);
DKM_STAT_DECL(ahci_block_reads);
DKM_STAT_DECL(ahci_block_writes);
DKM_TS_DECL(ts_abar);
static const char *const g_depends[] = { "pci", "irq" };
static const char *const g_provides[] = { "block" };
@@ -130,7 +137,8 @@ static void ahci_zero(void *ptr, u32 len) {
}
static int ahci_find(u8 *out_bus, u8 *out_dev, u8 *out_func) {
for (u8 bus = 0; bus < 8; bus++) {
/* PCI 规范允许 256 条 bus (0-255)，实机 AHCI 可能位于 bus > 7 */
for (u16 bus = 0; bus < 256; bus++) {
for (u8 dev = 0; dev < 32; dev++) {
u32 vd = pci_read(bus, dev, 0, PCI_VENDOR_ID);
if ((vd & 0xffff) == 0xffff) continue;
@@ -298,13 +306,16 @@ static int ahci_read_blocks_internal(u32 port, ahci_cmd_header *hdr, struct dkm_
g_abar[(base + PxIS) / 4] = 0xffffffffu;
g_abar[HBA_IS / 4] = (1u << port);
g_abar[(base + PxCI) / 4] = 1;
for (u32 i = 0; i < 5000000; i++) {
/* TSC deadline 超时: 5 秒，实机机械 HDD 首次寻道需数百 ms */
u64 deadline = dkm_rdtsc() + dkm_tsc_per_ms * 5000;
while (dkm_rdtsc() < deadline) {
if ((g_abar[(base + PxCI) / 4] & 1u) == 0) {
u8 *dst = (u8 *)buffer;
u8 *src = (u8 *)data->virt;
for (u32 j = 0; j < bytes; j++) dst[j] = src[j];
return 0;
}
__asm__ volatile("pause");
}
g_log->warn("[ahci] READ timeout");
log_hex("[ahci] READ lba=", lba);
@@ -330,6 +341,10 @@ static int ahci_write_blocks_internal(u32 port, ahci_cmd_header *hdr, struct dkm
for (u32 j = 0; j < bytes; j++) dst[j] = src[j];
}
/* BUG-P0-2: 写入前必须 flush CPU cache，否则 DMA 控制器从物理内存
* 读到陈旧数据（CPU write-back cache 尚未写回）。实机必现。 */
__asm__ volatile("wbinvd" ::: "memory");
hdr[0].flags = 5 | (1u << 6); /* CFL=5, W=1 (write) */
hdr[0].prdtl = 1;
hdr[0].prdbc = 0;
@@ -341,29 +356,39 @@ static int ahci_write_blocks_internal(u32 port, ahci_cmd_header *hdr, struct dkm
tbl->prdt[0].dbc_i = (bytes - 1) | (1u << 31);
ahci_fill_write_fis(tbl->cfis, lba, count);
/* set PxCMD.W to indicate write direction */
u32 cmd = g_abar[(base + PxCMD) / 4];
cmd |= AHCI_CMD_W;
g_abar[(base + PxCMD) / 4] = cmd;
/* P0 修复: 移除 PxCMD.W 写入。AHCI 规范中 PxCMD.W 是只读位，
* 由硬件根据命令头 flags.W 自动设置。软件写入此位违反规范，
* 可能在某些实机 AHCI 控制器上导致未定义行为。 */
/* (原代码: cmd |= AHCI_CMD_W; g_abar[...] = cmd; — 已删除) */
g_abar[(base + PxIS) / 4] = 0xffffffffu;
g_abar[HBA_IS / 4] = (1u << port);
g_abar[(base + PxCI) / 4] = 1;
for (u32 i = 0; i < 5000000; i++) {
/* P0 修复: 写入超时改为 TSC deadline，与读取路径一致。
* 固定循环在实机 HDD 上会因 CPU 频率差异导致提前超时或死循环。 */
u64 deadline = dkm_rdtsc() + dkm_tsc_per_ms * 5000;
while (dkm_rdtsc() < deadline) {
if ((g_abar[(base + PxCI) / 4] & 1u) == 0) {
/* clear PxCMD.W after write completes */
cmd = g_abar[(base + PxCMD) / 4];
cmd &= ~AHCI_CMD_W;
g_abar[(base + PxCMD) / 4] = cmd;
/* BUG-P1-1 fix: CI 清除后检查 TFD 错误位。
* TFD 低字节是 STS，正常值 0x50 (DRDY|DRQ) 非零但不是错误。
* 只有 STS bit0 (ERR) 或 ERR 寄存器 (bits15:8) 非零才是真正错误。
* BUG-20260730-P14: 原 `tfd & 0xFF` 误判 STS=0x50 为错误，导致写入
* 实际成功却被报告为失败，FAT32 写路径提前返回错误码。 */
u32 tfd = g_abar[(base + PxTFD) / 4];
u32 is = g_abar[(base + PxIS) / 4];
u8 sts = (u8)(tfd & 0xFF);
u8 err_reg = (u8)((tfd >> 8) & 0xFF);
if ((sts & 0x01) || err_reg) {
g_log->warn("[ahci] write error: TFD ERR");
log_hex("[ahci] TFD=", tfd);
log_hex("[ahci] PxIS=", is);
return -4;
}
return 0;
}
__asm__ volatile("pause");
}
/* timeout: clear PxCMD.W */
cmd = g_abar[(base + PxCMD) / 4];
cmd &= ~AHCI_CMD_W;
g_abar[(base + PxCMD) / 4] = cmd;
g_log->warn("[ahci] WRITE timeout");
log_hex("[ahci] WRITE lba=", lba);
log_hex("[ahci] WRITE count=", count);
@@ -376,6 +401,7 @@ static int ahci_write_blocks_internal(u32 port, ahci_cmd_header *hdr, struct dkm
static int ahci_block_read(void *ctx, u64 lba, u32 count, void *buffer) {
(void)ctx;
if (g_ready_port == 0xffffffffu || !g_cmd_header) return -1;
DKM_STAT_INC(ahci_block_reads);
log_hex("[ahci] block_read lba=", lba);
log_hex("[ahci] block_read count=", count);
while (count > 0) {
@@ -392,6 +418,7 @@ static int ahci_block_read(void *ctx, u64 lba, u32 count, void *buffer) {
static int ahci_block_write(void *ctx, u64 lba, u32 count, const void *buffer) {
(void)ctx;
if (g_ready_port == 0xffffffffu || !g_cmd_header) return -1;
DKM_STAT_INC(ahci_block_writes);
/* ensure port is in ST+FRE state */
u32 base = HBA_PORT_BASE + g_ready_port * HBA_PORT_SIZE;
u32 cmd = g_abar[(base + PxCMD) / 4];
@@ -445,8 +472,27 @@ static int ahci_identify_port(u32 port, const struct dkm_dma_api *dma) {
struct dkm_dma_buffer data;
if (dma->alloc_pages(1, 1024, 0x100000000ULL, &clb) != 0) return -2;
if (dma->alloc_pages(1, 256, 0x100000000ULL, &fis) != 0) return -3;
if (dma->alloc_pages(1, 128, 0x100000000ULL, &table) != 0) return -4;
if (dma->alloc_pages(1, 512, 0x100000000ULL, &data) != 0) return -5;
/* BUG-P0-1: sizeof(ahci_cmd_table)=144, 128B 缓冲区越界 16 字节。
* 改为 256B 满足对齐和大小要求，防止 ahci_zero 越界写。 */
if (dma->alloc_pages(1, 256, 0x100000000ULL, &table) != 0) return -4;
/* BUG-20260730-022: DMA data buffer must hold at least 8 sectors (4096B)
* for ahci_block_write chunked DMA. 512B caused 3584B out-of-bounds
* overwrite of adjacent kernel data on real hardware. */
if (dma->alloc_pages(1, 8192, 0x100000000ULL, &data) != 0) return -5;
/* P0 验证: DMA 缓冲区物理地址必须在 4GB 以下。
* AHCI 控制器 8086:2922 只支持 32 位 DMA，
* PRDT 地址超过 4GB 会导致 DMA 写入截断到错误物理地址。
* dma->alloc_pages 的上限参数 0x100000000ULL 已保证此约束，
* 但添加显式校验以防御 alloc_pages 实现变更。 */
if (clb.phys >= 0x100000000ULL || fis.phys >= 0x100000000ULL ||
table.phys >= 0x100000000ULL || data.phys >= 0x100000000ULL) {
g_log->warn("[ahci] DMA buffer above 4GB — 32-bit DMA will fail on this controller!");
log_hex("[ahci] clb.phys=", clb.phys);
log_hex("[ahci] fis.phys=", fis.phys);
log_hex("[ahci] table.phys=", table.phys);
log_hex("[ahci] data.phys=", data.phys);
}
if (ahci_stop_port(port) != 0) {
g_log->warn("[ahci] port stop timeout");
@@ -476,7 +522,10 @@ static int ahci_identify_port(u32 port, const struct dkm_dma_api *dma) {
ahci_start_port(port);
g_abar[(base + PxCI) / 4] = 1;
for (u32 i = 0; i < 5000000; i++) {
/* BUG-P0-3: 固定 500 万次循环在 3GHz CPU 上仅 ~1-2ms，
* 不够 HDD 寻道。改为 TSC deadline 5s 超时，与 read/write 路径一致。 */
u64 deadline = dkm_rdtsc() + dkm_tsc_per_ms * 5000;
while (dkm_rdtsc() < deadline) {
if ((g_abar[(base + PxCI) / 4] & 1u) == 0) {
log_hex("[ahci] IDENTIFY port=", port);
log_hex("[ahci] IDENTIFY status=", g_abar[(base + PxTFD) / 4]);
@@ -492,6 +541,7 @@ static int ahci_identify_port(u32 port, const struct dkm_dma_api *dma) {
g_data = data;
return 1;
}
__asm__ volatile("pause");
}
g_log->warn("[ahci] IDENTIFY timeout");
@@ -510,6 +560,7 @@ int driver_init(const struct dkm_kernel_api *api,
if (!api || !api->log) return -1;
g_log = api->log;
dkm_instr_init(api);
g_log->info("[ahci] init begin");
@@ -536,7 +587,17 @@ int driver_init(const struct dkm_kernel_api *api,
pci_write(bus, dev, func, PCI_COMMAND, command);
log_hex("[ahci] PCI command=", command);
u64 abar_phys = (u64)(pci_read(bus, dev, func, PCI_BAR5) & 0xFFFFFFF0u);
/* 读取 ABAR: BAR5 可能是 64-bit MMIO BAR，高位在 BAR4 */
u32 bar5_lo = pci_read(bus, dev, func, PCI_BAR5);
u64 abar_phys;
if ((bar5_lo & 0x7) == 0x4) {
/* 64-bit MMIO BAR: 高 32 位在 BAR4 */
u32 bar5_hi = pci_read(bus, dev, func, PCI_BAR4);
abar_phys = ((u64)bar5_hi << 32) | (bar5_lo & 0xFFFFFFF0u);
g_log->info("[ahci] ABAR is 64-bit MMIO BAR");
} else {
abar_phys = bar5_lo & 0xFFFFFFF0u;
}
u32 irq_line = pci_read(bus, dev, func, PCI_IRQ_LINE) & 0xff;
log_hex("[ahci] ABAR phys=", abar_phys);
log_hex("[ahci] PCI IRQ line=", irq_line);
@@ -548,6 +609,7 @@ int driver_init(const struct dkm_kernel_api *api,
}
g_abar = (volatile u32 *)(uintptr_t)(api->hhdm_offset + abar_phys);
DKM_TS_BEGIN(ts_abar);
log_hex("[ahci] HHDM offset=", api->hhdm_offset);
u32 cap = g_abar[HBA_CAP / 4];
@@ -565,13 +627,32 @@ int driver_init(const struct dkm_kernel_api *api,
log_hex("[ahci] VS=", vs);
log_hex("[ahci] CAP2=", cap2);
log_hex("[ahci] BOHC=", bohc);
/* AHCI 1.3+ BOHC handoff: 如果 BIOS 仍拥有控制器, 请求所有权 */
if (bohc & 0x01) {
g_log->info("[ahci] BIOS owns HBA, requesting handoff");
g_abar[HBA_BOHC / 4] = bohc | 0x02; /* set OOS */
u64 deadline = dkm_rdtsc() + dkm_tsc_per_ms * 2000;
while (dkm_rdtsc() < deadline) {
if (!(g_abar[HBA_BOHC / 4] & 0x01)) break;
__asm__ volatile("pause");
}
if (g_abar[HBA_BOHC / 4] & 0x01) {
g_log->warn("[ahci] BIOS handoff timeout, proceeding anyway");
} else {
g_log->info("[ahci] BIOS handoff complete");
}
}
log_hex("[ahci] ports count=", (cap & 0x1f) + 1);
log_hex("[ahci] cmd slots=", ((cap >> 8) & 0x1f) + 1);
DKM_TS_END(ts_abar, g_log->info, "ahci_abar_mmio");
u32 implemented = 0;
for (u32 port = 0; port < 32; port++) {
if (pi & (1u << port)) {
implemented++;
DKM_STAT_INC(ahci_port_found);
ahci_log_port(port);
}
}
@@ -584,6 +665,7 @@ int driver_init(const struct dkm_kernel_api *api,
int ident = ahci_identify_port(port, api->dma);
if (ident > 0) {
identified++;
DKM_STAT_INC(ahci_identify_ok);
break;
}
}
CODE/DKM/apic/apic.c
+294 -6
View File
@@ -1,7 +1,17 @@
/* DKM APIC Driver — APIC discovery with PIC fallback
/* DKM APIC Driver — APIC discovery + IOAPIC init + LAPIC enable
* Stage 0, required, depends on "timer", provides "irq" and "apic".
* Current kernel IRQ backend is still PIC; this driver only discovers APIC
* topology and keeps PIC routing active.
*
* 真机路径:
* 1. LAPIC 使能 + Spurious Interrupt Vector 注册
* 2. IOAPIC 重定向表初始化: 逐条目编程, 将 ISA IRQ 映射到 vector 0x20-0x2F
* (兼容 PIC 布局), 逐条目 mask
* 3. MADT ISO (Interrupt Source Override) 处理: 按 ACPI 规范修正 IRQ→GSI 映射
* 4. SIPI 多核启动框架 (预留, 未实现)
*
* QEMU 兼容:
* - QEMU 默认只提供 1 个 IOAPIC, 24 条 GSI
* - 实机可能有多个 IOAPIC, GSI 范围更大
* - 实机必须处理 MADT ISO (IRQ0→GSI2 等)
*/
#include <stdint.h>
@@ -47,6 +57,10 @@ struct dkm_kernel_api {
const void *boot_modules_response;
int (*irq_register)(u8 irq, void *handler);
u64 hhdm_offset;
const void *block;
const void *mmio;
void *(*mm_map_mmio)(u64 phys, u64 size);
void (*mm_unmap_mmio)(void *virt, u64 size);
};
struct dkm_driver_handle;
@@ -135,16 +149,49 @@ typedef struct __attribute__((packed)) {
u32 flags;
} acpi_madt;
/* ---- IOAPIC 信息存储（真机多 IOAPIC 支持） ---- */
#define MAX_IOAPIC 4
#define MAX_ISO 16
#define MAX_LAPIC 256
struct ioapic_info {
u8 id;
u32 gsi_base;
u32 gsi_count; /* 从 IOAPIC VER 寄存器读取: max_redir_entry + 1 */
u64 mmio_phys; /* IOAPIC MMIO 物理基址 */
volatile u32 *mmio; /* HHDM/MMIO 窗口映射后的虚拟地址, 0=未映射 */
};
struct iso_info {
u8 bus_source; /* ISA bus source IRQ (0-15) */
u32 gsi; /* 全局系统中断号 */
u16 flags; /* 极性/触发模式标志 */
};
struct lapic_entry {
u8 apic_id;
u32 flags; /* MADT LAPIC flags: bit0=enabled */
};
struct madt_info {
u64 lapic_phys;
u32 flags;
u32 lapic_count;
u32 ioapic_count;
u32 iso_count;
struct ioapic_info ioapics[MAX_IOAPIC];
struct iso_info isos[MAX_ISO];
struct lapic_entry lapics[MAX_LAPIC];
};
static const struct dkm_log_api *g_log;
static __inline__ void apic_mb(void) {
__asm__ volatile("" ::: "memory");
}
static int memeq(const char *a, const char *b, u32 n) {
for (u32 i = 0; i < n; i++) {
if (a[i] != b[i]) return 0;
@@ -255,19 +302,36 @@ static void parse_madt_entries(const acpi_madt *madt, struct madt_info *info) {
}
if (type == 0 && len >= 8) {
/* LAPIC entry */
u8 apic_id = entry[3];
u32 flags = *(const u32 *)(const void *)(entry + 4);
if (flags & 1u) info->lapic_count++;
log_hex("[apic] CPU LAPIC id=", apic_id);
if (flags & 1u) {
info->lapic_count++;
if (info->lapic_count <= MAX_LAPIC) {
info->lapics[info->lapic_count - 1].apic_id = apic_id;
info->lapics[info->lapic_count - 1].flags = flags;
}
}
} else if (type == 1 && len >= 12) {
/* IOAPIC entry */
u8 ioapic_id = entry[2];
u32 addr = *(const u32 *)(const void *)(entry + 4);
u32 gsi = *(const u32 *)(const void *)(entry + 8);
info->ioapic_count++;
log_hex("[apic] IOAPIC id=", ioapic_id);
log_hex("[apic] IOAPIC addr=", addr);
log_hex("[apic] IOAPIC gsi_base=", gsi);
if (info->ioapic_count < MAX_IOAPIC) {
struct ioapic_info *io = &info->ioapics[info->ioapic_count];
io->id = ioapic_id;
io->gsi_base = gsi;
io->mmio_phys = (u64)addr;
io->mmio = (volatile u32 *)(uintptr_t)(u64)addr; /* HHDM 直映射, 后续映射修正 */
io->gsi_count = 0;
info->ioapic_count++;
}
} else if (type == 2 && len >= 10) {
/* ISO (Interrupt Source Override) entry */
u8 source = entry[3];
u32 gsi = *(const u32 *)(const void *)(entry + 4);
u16 flags = *(const u16 *)(const void *)(entry + 8);
@@ -275,6 +339,12 @@ static void parse_madt_entries(const acpi_madt *madt, struct madt_info *info) {
log_hex("[apic] ISO source=", source);
log_hex("[apic] ISO gsi=", gsi);
log_hex("[apic] ISO flags=", flags);
if (info->iso_count <= MAX_ISO) {
struct iso_info *iso = &info->isos[info->iso_count - 1];
iso->bus_source = source;
iso->gsi = gsi;
iso->flags = flags;
}
} else if (type == 5 && len >= 12) {
u64 override = *(const u64 *)(const void *)(entry + 4);
info->lapic_phys = override;
@@ -285,6 +355,210 @@ static void parse_madt_entries(const acpi_madt *madt, struct madt_info *info) {
}
}
/* ---- IOAPIC MMIO 访问 ---- *
* IOAPIC 寄存器通过 MMIO 访问, 地址空间为 IOREGSEL(0x00) + IOWIN(0x10).
* 真机 IOAPIC 地址通常在 0xFEC00000, HHDM 通常覆盖此低 4G 地址。
* 写入 IOREGSEL 选择寄存器号, 读/写 IOWIN 访问数据。
*/
#define IOAPIC_IOREGSEL 0x00
#define IOAPIC_IOWIN 0x10
static u32 ioapic_read(volatile u32 *base, u8 reg) {
base[IOAPIC_IOREGSEL / 4] = (u32)reg;
apic_mb(); /* 寄存器选择必须先于数据读取 */
return base[IOAPIC_IOWIN / 4];
}
static void ioapic_write(volatile u32 *base, u8 reg, u32 val) {
base[IOAPIC_IOREGSEL / 4] = (u32)reg;
apic_mb(); /* 寄存器选择必须先于数据写入 */
base[IOAPIC_IOWIN / 4] = val;
}
/* IOAPIC 重定向表项 (64-bit, 分两次 32-bit 读写)
* bits 0-7: interrupt vector (0x20-0xFF)
* bit 8: delivery mode: 0=fixed, 1=lowest, 2=SMI, 4=NMI, 5=INIT, 7=ExtINT
* bit 9: destination mode: 0=physical, 1=logical
* bit 10: delivery status (RO)
* bit 11: polarity: 0=active high, 1=active low
* bit 12: remote IRR (RO, level-triggered only)
* bit 13: trigger mode: 0=edge, 1=level
* bit 14: mask: 0=enabled, 1=masked
* bit 15: reserved
* bits 16-55: reserved
* bits 56-63: destination APIC ID (physical mode) or MDA (logical mode)
*/
static u64 ioapic_read_redir(volatile u32 *base, u8 entry) {
u32 lo = ioapic_read(base, (u8)(0x10 + entry * 2));
u32 hi = ioapic_read(base, (u8)(0x10 + entry * 2 + 1));
return ((u64)hi << 32) | (u64)lo;
}
static void ioapic_write_redir(volatile u32 *base, u8 entry, u64 val) {
ioapic_write(base, (u8)(0x10 + entry * 2), (u32)(val & 0xffffffffu));
ioapic_write(base, (u8)(0x10 + entry * 2 + 1), (u32)(val >> 32));
}
/* ---- IOAPIC 初始化 ---- *
* 逐条目编程重定向表: ISA IRQ→vector 映射 + mask all。
* 真机关键: 处理 MADT ISO (IRQ0→GSI2 是最常见的 override)。
* PIC 兼容模式: vector = 0x20 + IRQ (与 PIC remap 布局一致)。
*
* **QEMU 无法测试但真机必需的代码路径**:
* 1. ISO 处理: 真机几乎总有 IRQ0→GSI2 override, QEMU 默认无 override
* 2. 极性标志: 真机 ISA IRQ0 (timer) 必须设 active-high,
* 但 ISO 可能指定 active-low (PCIe SCI 等)
* 3. 多 IOAPIC: 真机可能有 2+ IOAPIC, 每个 GSI 范围不同
*/
static void ioapic_init_one(struct ioapic_info *io, u64 hhdm_offset,
const struct iso_info *isos, u32 iso_count,
void *(*mm_map_mmio_fn)(u64, u64)) {
/* 映射 IOAPIC MMIO — 真机地址通常在 0xFECxxxxx, HHDM 通常覆盖,
* 但使用 mm_map_mmio 更安全 (PCD|PWT 属性) */
if (mm_map_mmio_fn) {
void *mapped = mm_map_mmio_fn(io->mmio_phys, 0x1000);
if (mapped) {
io->mmio = (volatile u32 *)mapped;
g_log->info("[apic] IOAPIC mapped via mm_map_mmio");
} else {
g_log->warn("[apic] mm_map_mmio failed for IOAPIC; trying HHDM");
io->mmio = (volatile u32 *)(uintptr_t)(hhdm_offset + io->mmio_phys);
}
} else {
io->mmio = (volatile u32 *)(uintptr_t)(hhdm_offset + io->mmio_phys);
}
/* 读取 IOAPIC 版本寄存器获取最大重定向条目数 */
u32 ver = ioapic_read(io->mmio, 0x01);
u32 max_redir = ((ver >> 16) & 0xff) + 1;
io->gsi_count = max_redir;
log_hex("[apic] IOAPIC VER=", ver);
log_hex("[apic] IOAPIC max_redir=", max_redir);
/* 读取 IOAPIC ID 验证 */
u32 id_reg = ioapic_read(io->mmio, 0x00);
log_hex("[apic] IOAPIC ID reg=", id_reg);
/* 构建默认 ISA IRQ→GSI→vector 映射表 (identity map + ISO override)
* 默认: GSI = ISA_IRQ (0-15), vector = 0x20 + ISA_IRQ
* ISO override: 修改特定 IRQ 的 GSI 和极性/触发模式 */
u32 gsi_to_vector[256]; /* GSI → vector 映射 */
u32 gsi_flags[256]; /* GSI → polar/trigger flags from ISO */
for (u32 i = 0; i < 256; i++) {
gsi_to_vector[i] = 0;
gsi_flags[i] = 0;
}
/* 先建立 identity 映射: GSI 0-15 → vector 0x20-0x2F */
for (u32 gsi = 0; gsi < 16; gsi++) {
gsi_to_vector[gsi] = 0x20 + gsi;
}
/* 应用 ISO override */
for (u32 i = 0; i < iso_count; i++) {
const struct iso_info *iso = &isos[i];
u8 src = iso->bus_source;
u32 gsi = iso->gsi;
if (gsi < 256) {
gsi_to_vector[gsi] = 0x20 + src; /* vector 仍基于 ISA IRQ 编号 */
gsi_flags[gsi] = iso->flags;
g_log->info("[apic] ISO: ISA IRQ -> GSI override");
log_hex("[apic] ISA IRQ=", src);
log_hex("[apic] GSI=", gsi);
log_hex("[apic] vector=", 0x20 + src);
}
}
/* 编程重定向表: 全部 mask, 编入正确的 vector/极性/触发模式/目标 APIC */
for (u32 pin = 0; pin < max_redir && pin < 256; pin++) {
u32 gsi = io->gsi_base + pin;
u64 entry = 0;
if (gsi < 256 && gsi_to_vector[gsi] != 0) {
u32 vec = gsi_to_vector[gsi];
u16 flags = gsi_flags[gsi];
entry = (u64)vec; /* vector */
/* delivery mode = fixed (0) */
/* destination mode = physical (0) */
/* 极性: bit 11. ISA 默认 active-high (0).
* ISO flags bit 1: 0=conforms (active-high for ISA), 1=active-low */
if (flags & 0x03) {
if (flags & 0x02) entry |= (1ULL << 11); /* active low */
}
/* 触发模式: bit 13. ISA 默认 edge (0).
* ISO flags bit 3: 0=conforms (edge for ISA), 1=level */
if (flags & 0x08) {
if (flags & 0x04) entry |= (1ULL << 13); /* level triggered */
}
/* destination: BSP APIC ID (读自 LAPIC) */
/* 暂时硬编码 destination = 0 (BSP), 后续从 LAPIC ID 寄存器获取 */
entry |= (0ULL << 56); /* destination APIC ID = 0 */
}
entry |= (1ULL << 14); /* mask = 1, 所有条目默认屏蔽 */
ioapic_write_redir(io->mmio, (u8)pin, entry);
}
g_log->info("[apic] IOAPIC redirect table programmed (all masked)");
}
/* ---- LAPIC 使能 ---- *
* 真机必须:
* 1. 写 IA32_APIC_BASE MSR 启用 bit 11 (global enable)
* 2. 写 LAPIC SVR 寄存器设置 Spurious Interrupt Vector (建议 0xFF)
* 3. 设置 SVR bit 8 (APIC software enable)
*
* **QEMU 无法测试但真机必需**: LAPIC SVR 设置 — QEMU 默认已启用 LAPIC,
* 但实机 BIOS 可能留 LAPIC 为 software-disable 状态。
*/
static void wrmsr(u32 msr, u64 val) {
u32 lo = (u32)(val & 0xffffffffu);
u32 hi = (u32)(val >> 32);
__asm__ volatile("wrmsr" :: "a"(lo), "d"(hi), "c"(msr));
}
static void lapic_enable(u64 hhdm_offset, u64 lapic_phys) {
volatile u32 *lapic = (volatile u32 *)(uintptr_t)(hhdm_offset + lapic_phys);
/* 确保 IA32_APIC_BASE 的 global enable 和 BSP 位已设置 */
u64 apic_base = rdmsr(0x1B);
apic_base |= (1ULL << 11); /* global enable */
/* 保持 BSP 位不变 (bit 8) */
wrmsr(0x1B, apic_base);
g_log->info("[apic] LAPIC global enable set in MSR");
/* 读当前 SVR */
u32 svr = lapic[0xF0 / 4];
log_hex("[apic] LAPIC SVR before=", svr);
/* 设置 Spurious Interrupt Vector = 0xFF + APIC software enable (bit 8) */
svr = 0xFF | (1u << 8);
lapic[0xF0 / 4] = svr;
apic_mb();
/* 回读验证 */
svr = lapic[0xF0 / 4];
log_hex("[apic] LAPIC SVR after=", svr);
if (svr & (1u << 8)) {
g_log->info("[apic] LAPIC software enabled");
} else {
g_log->warn("[apic] LAPIC SVR bit8 not set — hardware may not support");
}
/* 读 LAPIC ID 和 version 做诊断 dump */
log_hex("[apic] LAPIC ID=", lapic[0x20 / 4]);
log_hex("[apic] LAPIC LDR=", lapic[0xD0 / 4]);
log_hex("[apic] LAPIC version=", lapic[0x30 / 4]);
}
__attribute__((visibility("default")))
int driver_init(const struct dkm_kernel_api *api,
struct dkm_driver_handle *handle) {
@@ -346,7 +620,21 @@ int driver_init(const struct dkm_kernel_api *api,
g_log->warn("[apic] HHDM unavailable; skip LAPIC MMIO read");
}
g_log->info("[apic] discovery complete; PIC routing retained");
/* ---- LAPIC 使能（真机必需，QEMU 也可安全执行） ---- */
if (api->hhdm_offset && info.lapic_phys) {
lapic_enable(api->hhdm_offset, info.lapic_phys);
}
/* ---- IOAPIC 初始化（真机必需，QEMU 也可安全执行） ---- */
for (u32 i = 0; i < info.ioapic_count; i++) {
g_log->info("[apic] initializing IOAPIC");
log_hex("[apic] index=", i);
ioapic_init_one(&info.ioapics[i], api->hhdm_offset,
info.isos, info.iso_count,
api->mm_map_mmio);
}
g_log->info("[apic] discovery + init complete; PIC routing retained as fallback");
g_log->info("[apic] driver ready");
return 0;
}
CODE/DKM/dkm_instr.h
+87
View File
@@ -0,0 +1,87 @@
/* dkm_instr.h — DKM 驱动专用插桩宏（无 UTSM 头文件依赖）
*
* 设计原则:
* - 使用 dkm_shared.h 已有的 dkm_rdtsc()/dkm_tsc_per_ms
* - 日志通过 dkm_kernel_api->log 输出
* - 统计计数器是 file-local static
* - 禁用时全部宏展开为空（零开销）
* - 需在 driver_init 开头调用 dkm_instr_init(api) 初始化
*
* 使用方式:
* 1. #include "../dkm_instr.h"
* 2. 在 driver_init 开头: dkm_instr_init(api);
* 3. 使用 DKM_STAT_INC / DKM_TS / DKM_LOG_TRACE 宏
*/
#ifndef DKM_INSTR_H
#define DKM_INSTR_H
#include "dkm_shared.h"
/* ---- 全局开关（dkm_instr.c 定义，每个 .drv 引用同一符号） ----
* 注意: DKM .drv 是 ET_REL 可重定位对象，每个驱动有独立的数据段副本。
* 因此 dkm_instr_global_enable 在每个 .drv 中独立控制，由
* dkm_instr_init() 在 driver_init 中根据 kernel_api 设置。
*/
static u32 dkm_instr_global_enable __attribute__((unused)) = 0;
/* ---- DKM_STAT: 轻量级计数器 ----
* DKM_STAT_DECL(name) — 在函数/文件作用域声明计数器
* DKM_STAT_INC(name) — 自增（仅当 enabled）
* DKM_STAT_DUMP(name, log_info_fn) — 输出当前计数值
*/
#define DKM_STAT_DECL(name) static u64 name##_count = 0
#define DKM_STAT_INC(name) do { \
if (dkm_instr_global_enable) { name##_count++; } \
} while(0)
#define DKM_STAT_DUMP(name, log_info_fn) do { \
if (dkm_instr_global_enable && name##_count > 0) { \
log_info_fn("[DKM:STAT] " #name " count="); \
/* 简单 u64 to hex 串口输出 */ \
static const char _hx[] = "0123456789abcdef"; \
char _buf[19]; _buf[0]='0'; _buf[1]='x'; \
for(int _i=0;_i<16;_i++) _buf[2+_i]=_hx[(name##_count>>((15-_i)*4))&0xf]; \
_buf[18]=0; log_info_fn(_buf); \
} \
} while(0)
/* ---- DKM_TS: 时间戳测量 ----
* DKM_TS_DECL(name) — 声明时间戳变量
* DKM_TS_BEGIN(name) — 记录起始 TSC
* DKM_TS_END(name, log_info_fn, label) — 计算耗时并输出
*/
#define DKM_TS_DECL(name) static u64 name##_ts = 0
#define DKM_TS_BEGIN(name) do { name##_ts = dkm_rdtsc(); } while(0)
#define DKM_TS_END(name, log_info_fn, label) do { \
if (dkm_instr_global_enable && dkm_tsc_per_ms) { \
u64 _d = dkm_rdtsc() - name##_ts; \
u64 _ms = _d / dkm_tsc_per_ms; \
log_info_fn("[DKM:TS] " label " elapsed_ms="); \
static const char _hx[] = "0123456789abcdef"; \
char _buf[19]; _buf[0]='0'; _buf[1]='x'; \
for(int _i=0;_i<16;_i++) _buf[2+_i]=_hx[(_ms>>((15-_i)*4))&0xf]; \
_buf[18]=0; log_info_fn(_buf); \
} \
} while(0)
/* ---- DKM_LOG_TRACE: 调试级别日志 ----
* 仅当插桩启用时通过 api->log->info 输出
*/
#define DKM_LOG_TRACE(log_api, msg) do { \
if (dkm_instr_global_enable && (log_api)) (log_api)->info(msg); \
} while(0)
/* ---- 初始化：读取 kernel_api 中的插桩标志 ----
* kernel_api->feature_bits bit0 = 插桩启用标志
* 由 UTSM dkm_fill_platform_info() 根据 FUCK debug.dkm_trace 设置
*/
static __inline__ void dkm_instr_init(const struct dkm_kernel_api *api) {
if (api && (api->feature_bits & 0x01)) {
dkm_instr_global_enable = 1;
}
}
#endif /* DKM_INSTR_H */
CODE/DKM/dkm_shared.h
+25 -1
View File
@@ -109,6 +109,15 @@ struct dkm_net_device_desc {
int (*is_wireless)(void *ctx);
};
struct dkm_net_stats {
u64 tx_ok;
u64 tx_err;
u64 rx_ok;
u64 rx_err;
u64 rx_overflow;
u64 link_changes;
};
struct dkm_net_api {
int (*register_device)(const struct dkm_net_device_desc *desc);
u32 (*device_count)(void);
@@ -119,6 +128,7 @@ struct dkm_net_api {
int (*scan_count)(u32 index);
int (*scan_result)(u32 index, u32 n, struct dkm_net_scan_result *out);
int (*is_wireless)(u32 index);
int (*device_stats)(u32 index, struct dkm_net_stats *out);
};
typedef int (*dkm_block_read_fn)(void *ctx, u64 lba, u32 count, void *buffer);
@@ -143,6 +153,16 @@ struct dkm_block_api {
int (*set_write_fn)(u32 index, dkm_block_write_fn fn);
};
/* 与 UTSM/include/utsm/paging.h 中的 dkm_mmio_api 布局一致 */
struct dkm_mmio_api {
/* 四级页表 walk。返回 0=未映射；1=4K PTE；2=2M PDE；3=1G PDPTE */
int (*is_mapped)(u64 vaddr);
/* 把物理区间映射到 hhdm_offset + phys（4KiB UC 页），返回 0 成功 */
int (*map_mmio)(u64 phys, u64 size);
/* 当前 CR3 物理地址（诊断用） */
u64 (*cr3)(void);
};
/* 与 UTSM/include/utsm/dkm.h 中的 dkm_kernel_api 布局完全一致.
* 字段顺序/类型不可调整 — UTSM 端按此偏移填充. */
struct dkm_kernel_api {
@@ -168,7 +188,11 @@ struct dkm_kernel_api {
const void *boot_modules_response;
int (*irq_register)(u8 irq, void *handler);
u64 hhdm_offset;
const struct dkm_block_api *block; /* 末尾字段, 不使用 block 的驱动可不访问 */
const struct dkm_block_api *block; /* 不使用 block 的驱动可不访问 */
const struct dkm_mmio_api *mmio; /* 页表/高位 MMIO 映射服务（HHDM 空洞原地补映射） */
/* —— 新增字段只允许追加在末尾（DSK 以 api+0xA8 硬偏移读取 block） —— */
void *(*mm_map_mmio)(u64 phys, u64 size); /* MMIO 独立窗口映射（PCD|PWT），返回虚拟地址，失败返回 0 */
void (*mm_unmap_mmio)(void *virt, u64 size); /* 解除 MMIO 独立窗口映射 */
};
struct dkm_driver_handle;
CODE/DKM/e1000/e1000.c
+445 -79
View File
@@ -1,9 +1,16 @@
/* DKM e1000 Driver — Intel 8254x Gigabit Ethernet
/* DKM e1000 Driver — Intel 8254x/8257x Gigabit Ethernet
* Stage 3, optional, depends on "pci" and "irq", provides "netdev".
* Finds e1000 via PCI, maps MMIO, reads MAC address.
* Supports classic e1000 (82540EM/82545/82546) and e1000e (82574L/I217/I218/I219).
* Finds device via PCI, maps MMIO, reads MAC (RAL/RAH or EEPROM),
* initializes RX/TX rings, provides link/speed/duplex diagnostics.
*/
#include "../dkm_shared.h"
#include "../dkm_instr.h"
DKM_STAT_DECL(e1k_irq_count);
DKM_STAT_DECL(e1k_rx_packets);
DKM_STAT_DECL(e1k_tx_packets);
static const char *const g_depends[] = {"pci","irq"};
static const char *const g_provides[] = {"netdev"};
@@ -11,7 +18,7 @@ __attribute__((visibility("default"), used))
const struct dkm_driver_desc driver_desc = {
.magic=DKM_DRIVER_MAGIC,.abi_version=DKM_ABI_VERSION,
.desc_size=sizeof(struct dkm_driver_desc),
.name="e1000",.version="0.1.0",.vendor="Deshab",
.name="e1000",.version="0.2.0",.vendor="Deshab",
.driver_class=9,.stage=3,.flags=0,.priority=0,
.depends=g_depends,.depends_count=2,
.provides=g_provides,.provides_count=1,.min_kernel_abi=1,
@@ -41,13 +48,33 @@ const struct dkm_driver_desc driver_desc = {
#define E1000_TXDCTL 0x3828
#define E1000_TCTL 0x0400
#define E1000_TIPG 0x0410
#define E1000_MANC 0x0580
/* STATUS register bits (link/speed/duplex diagnostic) */
#define E1000_STATUS_FD (1u << 0) /* full duplex */
#define E1000_STATUS_LU (1u << 1) /* link up */
#define E1000_STATUS_FUNC_SHIFT 2 /* PCI function number (ro) */
#define E1000_STATUS_TXOFF (1u << 4) /* transmitter paused */
#define E1000_STATUS_SPEEDMASK (3u << 6)
#define E1000_STATUS_SPEED_10 (0u << 6)
#define E1000_STATUS_SPEED_100 (1u << 6)
#define E1000_STATUS_SPEED_1000 (2u << 6) /* classic e1000 only */
/* CTRL register bits */
#define E1000_CTRL_FD (1u << 0)
#define E1000_CTRL_SLU (1u << 6)
#define E1000_CTRL_RST (1u << 26) /* software reset */
#define E1000_CTRL_ASDE (1u << 11) /* auto-speed detect enable */
#define E1000_CTRL_FRCSPD (1u << 12) /* force speed */
#define E1000_CTRL_FRCDPLX (1u << 13) /* force duplex */
/* e1000e (82574L/I217/I219) speed encoding in STATUS differs */
#define E1000_STATUS_SPEED_1000_E1000E (3u << 6)
#define E1000_RX_DESC_COUNT 8u
#define E1000_TX_DESC_COUNT 8u
#define E1000_RX_BUF_SIZE 2048u
#define E1000_TX_BUF_SIZE 2048u
#define E1000_POOL_BYTES(count, size) ((u32)((count) * (size)))
#define E1000_POOL_PAGES(bytes) (((bytes) + 4095u) / 4096u)
#define E1000_RCTL_EN (1u << 1)
#define E1000_RCTL_SBP (1u << 2)
@@ -67,8 +94,97 @@ const struct dkm_driver_desc driver_desc = {
#define E1000_TX_CMD_RS (1u << 3)
#define E1000_TX_STA_DD (1u << 0)
#define E1000_RX_STA_DD (1u << 0)
#define E1000_CTRL_FD (1u << 0)
#define E1000_CTRL_SLU (1u << 6)
/* ---- e1000 device ID table ---- */
/* 分类: 0=经典 e1000 (8254x), 1=e1000e (8257x/I217/I218/I219) */
struct e1000_device_id {
u16 did;
u8 family; /* 0=classic, 1=e1000e */
const char *name;
};
static const struct e1000_device_id g_e1000_ids[] = {
/* 经典 e1000 (8254x 系列) — EERD 接口兼容 */
{0x100E, 0, "82540EM"}, /* QEMU e1000 default */
{0x1004, 0, "82543GC"}, /* Copper */
{0x100F, 0, "82545EM"}, /* Copper */
{0x1010, 0, "82546EB"}, /* Copper dual-port */
{0x1011, 0, "82545EM-Fiber"},
{0x1012, 0, "82546EB-Fiber"},
{0x1013, 0, "82541EI"},
{0x1015, 0, "82540EM-LOM"},
{0x1016, 0, "82540EP"},
{0x1017, 0, "82540EP-LOM"},
{0x1018, 0, "82541EI-LOM"},
{0x1019, 0, "82547EI"},
{0x101A, 0, "82547EI-LOM"},
{0x101D, 0, "82546EB-Quad"},
{0x1026, 0, "82545GM"},
{0x1027, 0, "82545GM-Fiber"},
{0x1028, 0, "82545GM-SerDes"},
{0x1075, 0, "82547GI"},
{0x1076, 0, "82541GI"},
{0x1077, 0, "82541GI-LOM"},
{0x1078, 0, "82541ER"},
{0x1079, 0, "82546GB"},
{0x107A, 0, "82546GB-Fiber"},
{0x107B, 0, "82546GB-SerDes"},
{0x107C, 0, "82541GI-Mobile"},
{0x108B, 0, "82573E"},
{0x108C, 0, "82573E-IAMT"},
{0x109A, 0, "82573L"},
/* e1000e (8257x/I217/I218/I219) 系列 — 寄存器兼容但 EERD/STATUS 编码有差异 */
{0x10D3, 1, "82574L"}, /* QEMU e1000e default */
{0x10F5, 1, "82578DM"},
{0x10F6, 1, "82578DC"},
{0x1502, 1, "82579V"},
{0x1503, 1, "82579V-2"},
{0x1533, 1, "I217-V"},
{0x1534, 1, "I217-LM"},
{0x153A, 1, "I218-V"},
{0x153B, 1, "I218-LM"},
{0x156F, 1, "I219-V"},
{0x1570, 1, "I219-LM"},
{0x157B, 1, "I219-V-2"},
{0x157A, 1, "I219-LM-2"},
{0x15D3, 1, "I219-V-3"},
{0x15D8, 1, "I219-LM-3"},
{0x15E3, 1, "I219-V-4"},
{0x15D6, 1, "I219-V-5"},
{0x15BD, 1, "I219-V-6"},
{0x15B8, 1, "I219-LM-4"},
{0x15BB, 1, "I219-LM-5"},
{0x15DF, 1, "I219-LM-6"},
{0x15E0, 1, "I219-V-7"},
{0x15E1, 1, "I219-LM-7"},
{0x15E2, 1, "I219-LM-8"},
{0x15E4, 1, "I219-V-8"},
{0x15E5, 1, "I219-V-9"},
{0x15F9, 1, "I219-LM-9"},
{0x15FA, 1, "I219-V-10"},
{0x15FB, 1, "I219-LM-10"},
{0x15FC, 1, "I219-LM-11"},
{0x15FD, 1, "I219-V-11"},
{0x15FE, 1, "I219-LM-12"},
{0x15FF, 1, "I219-V-12"},
/* I210/I211 (igb 系列) — 与 e1000e MMIO 兼容 */
{0x1537, 1, "I210"},
{0x1536, 1, "I211-AT"},
/* 82575/82576/82580 (igb 系列, 多队列, 基本兼容) */
{0x10A7, 1, "82575EB"},
{0x10A9, 1, "82575EB-SerDes"},
{0x10C9, 1, "82576"},
{0x10E6, 1, "82576-Fiber"},
{0x10E7, 1, "82576-Quad"},
{0x150D, 1, "82580"},
{0x1516, 1, "82580-Fiber"},
{0x1526, 1, "82576-2"},
{0, 0, 0} /* 终止符 */
};
struct e1000_rx_desc {
u64 addr;
@@ -89,6 +205,36 @@ struct e1000_tx_desc {
u16 special;
} __attribute__((packed));
/* ---- 统计计数器（用于真机诊断） ---- */
static u64 g_stat_tx_ok; /* TX 成功帧数 */
static u64 g_stat_tx_err; /* TX 失败帧数 */
static u64 g_stat_tx_timeout; /* TX 超时次数 */
static u64 g_stat_rx_ok; /* RX 成功帧数 */
static u64 g_stat_rx_err; /* RX 错误帧数 */
static u64 g_stat_rx_overflow; /* RX buffer 太小丢包 */
static u64 g_stat_irq_count; /* IRQ 中断次数 */
/* 前向声明 */
static void raw_log(const char *s);
static void raw_hex(const char *prefix, u64 v);
/* 每 256 次数据路径事件打印一行摘要（避免刷串口）。 */
static void net_stat_tick(void) {
u64 sum = g_stat_tx_ok + g_stat_tx_err + g_stat_tx_timeout +
g_stat_rx_ok + g_stat_rx_err + g_stat_rx_overflow;
if ((sum & 0xFF) != 0) return;
raw_log("[e1000.raw] stat tx_ok=");
raw_hex("", g_stat_tx_ok);
raw_log("[e1000.raw] stat tx_err=");
raw_hex("", g_stat_tx_err);
raw_log("[e1000.raw] stat rx_ok=");
raw_hex("", g_stat_rx_ok);
raw_log("[e1000.raw] stat rx_err=");
raw_hex("", g_stat_rx_err);
raw_log("[e1000.raw] stat rx_overflow=");
raw_hex("", g_stat_rx_overflow);
}
static const struct dkm_log_api *g_log;
static volatile u32 *g_mmio;
static u64 g_bar0_phys;
@@ -103,6 +249,8 @@ static u64 g_tx_buf_phys[E1000_TX_DESC_COUNT];
static u32 g_rx_tail;
static u32 g_tx_tail;
static int g_rings_ready;
static u8 g_device_family; /* 0=classic e1000, 1=e1000e */
static u16 g_device_id; /* PCI device ID */
#define COM1 0x3F8
@@ -132,6 +280,23 @@ static void raw_hex(const char *prefix, u64 v) {
raw_log("\n");
}
/* 打印 MAC 地址 */
static void raw_mac(const char *prefix, const u8 mac[6]) {
static const char h[] = "0123456789abcdef";
raw_log(prefix);
for (int i = 0; i < 6; i++) {
serial_wait_tx();
dkm_outb(COM1, (u8)h[(mac[i] >> 4) & 0xf]);
serial_wait_tx();
dkm_outb(COM1, (u8)h[mac[i] & 0xf]);
if (i < 5) {
serial_wait_tx();
dkm_outb(COM1, ':');
}
}
raw_log("\n");
}
static u32 pci_read(u8 bus, u8 dev, u8 func, u8 reg) {
return dkm_pci_read(bus, dev, func, reg);
}
@@ -140,40 +305,165 @@ static void pci_write(u8 bus, u8 dev, u8 func, u8 reg, u32 v) {
dkm_pci_write(bus, dev, func, reg, v);
}
static int e1000_find(u8 *bus, u8 *dev) {
for (u8 d=0; d<32; d++) {
u32 vd = pci_read(0,d,0,PCI_VENDOR_ID);
if ((vd&0xffff)==0xffff) continue;
if ((vd&0xffff)!=0x8086) continue;
u16 did = (u16)(vd>>16);
/* 82540EM(0x100E) / 82545 等经典 e1000，以及 82574L(0x10D3) e1000e */
if (did==0x100E || did==0x10D3 || did==0x1004 || did==0x100F ||
did==0x10D3 || did==0x153A || did==0x1533) {
*bus=0; *dev=d; return 0;
/* 根据 PCI Device ID 查找设备信息 */
static const struct e1000_device_id *e1000_lookup_id(u16 did) {
for (int i = 0; g_e1000_ids[i].did != 0; i++) {
if (g_e1000_ids[i].did == did) return &g_e1000_ids[i];
}
return 0;
}
/* 多总线扫描 e1000 设备。真机网卡可能在 bus>0 上。 */
static int e1000_find(u8 *out_bus, u8 *out_dev, u8 *out_func,
const struct e1000_device_id **out_id) {
for (u8 bus = 0; bus < 16; bus++) {
for (u8 dev = 0; dev < 32; dev++) {
u32 vd = pci_read(bus, dev, 0, PCI_VENDOR_ID);
if ((vd & 0xffff) == 0xffff) continue;
if ((vd & 0xffff) != 0x8086) continue;
/* 检查是否为多功能设备 */
u8 header = (u8)(pci_read(bus, dev, 0, PCI_HEADER) >> 16);
u8 func_count = (header & 0x80) ? 8 : 1;
for (u8 func = 0; func < func_count; func++) {
u32 vd2 = pci_read(bus, dev, func, PCI_VENDOR_ID);
if ((vd2 & 0xffff) == 0xffff) continue;
if ((vd2 & 0xffff) != 0x8086) continue;
u16 did = (u16)(vd2 >> 16);
const struct e1000_device_id *id = e1000_lookup_id(did);
if (id) {
*out_bus = bus;
*out_dev = dev;
*out_func = func;
if (out_id) *out_id = id;
return 0;
}
}
}
}
return -1;
}
/* 读取 EEPROM 一个 16-bit 字（经典 e1000 EERD 接口）。失败返回 0xffff。 */
/* 读取 EEPROM 一个 16-bit 字（经典 e1000 EERD 接口）。
* 经典 e1000: EERD bit0=START, addr<<8, 完成后 bit4=DONE, data 在高 16 位。
* e1000e: EERD 接口类似但地址字段位置不同 (addr<<2, bit1=START, bit2=DONE)。
* 失败返回 0xffff。 */
static u16 e1000_eeprom_read(u16 addr) {
/* EERD: bit0=START, addr<<8, 完成后 bit4=DONE, data 在高 16 位 */
g_mmio[E1000_EERD/4] = ((u32)addr << 8) | 1u;
/* 实机: 100ms TSC 超时 */
u64 deadline = dkm_rdtsc() + dkm_tsc_per_ms * 100;
while (dkm_rdtsc() < deadline) {
u32 v = g_mmio[E1000_EERD/4];
if (v & (1u<<4)) return (u16)(v >> 16);
__asm__ volatile("pause");
if (g_device_family == 1) {
/* e1000e: EERD addr<<2 | START(bit1), DONE=bit2, data=bits[31:16] */
g_mmio[E1000_EERD/4] = ((u32)addr << 2) | 0x2u;
u64 deadline = dkm_rdtsc() + dkm_tsc_per_ms * 100;
while (dkm_rdtsc() < deadline) {
u32 v = g_mmio[E1000_EERD/4];
if (v & (1u << 2)) return (u16)(v >> 16);
__asm__ volatile("pause");
}
} else {
/* 经典 e1000: EERD addr<<8 | START(bit0), DONE=bit4 */
g_mmio[E1000_EERD/4] = ((u32)addr << 8) | 1u;
u64 deadline = dkm_rdtsc() + dkm_tsc_per_ms * 100;
while (dkm_rdtsc() < deadline) {
u32 v = g_mmio[E1000_EERD/4];
if (v & (1u << 4)) return (u16)(v >> 16);
__asm__ volatile("pause");
}
}
return 0xffff;
}
/* 检测链路状态，返回 0=down, 1=up */
static int e1000_link_up(void) {
if (!g_mmio) return 0;
return (g_mmio[E1000_STATUS/4] & E1000_STATUS_LU) ? 1 : 0;
}
/* 读取当前速度 (Mbps)，返回 10/100/1000/0(未知) */
static u32 e1000_link_speed(void) {
if (!g_mmio) return 0;
u32 status = g_mmio[E1000_STATUS/4];
u32 speed_bits = status & E1000_STATUS_SPEEDMASK;
if (g_device_family == 1) {
/* e1000e speed encoding: 00=reserved, 01=100, 10=1000, 11=1000 */
if (speed_bits == E1000_STATUS_SPEED_1000_E1000E ||
speed_bits == (2u << 6))
return 1000;
if (speed_bits == E1000_STATUS_SPEED_100) return 100;
if (speed_bits == E1000_STATUS_SPEED_10) return 10;
return 0;
} else {
/* 经典 e1000 speed encoding: 00=10, 01=100, 10=1000 */
if (speed_bits == E1000_STATUS_SPEED_1000) return 1000;
if (speed_bits == E1000_STATUS_SPEED_100) return 100;
if (speed_bits == E1000_STATUS_SPEED_10) return 10;
return 0;
}
}
/* 读取当前双工模式，返回 1=全双工, 0=半双工 */
static int e1000_link_full_duplex(void) {
if (!g_mmio) return 0;
return (g_mmio[E1000_STATUS/4] & E1000_STATUS_FD) ? 1 : 0;
}
/* 打印链路诊断信息 */
static void e1000_log_link_status(void) {
int up = e1000_link_up();
if (up) {
u32 speed = e1000_link_speed();
int fd = e1000_link_full_duplex();
const char *speed_str = "unknown";
char speed_buf[8];
if (speed == 1000) speed_str = "1000";
else if (speed == 100) speed_str = "100";
else if (speed == 10) speed_str = "10";
else {
/* 手动转数字 */
speed_buf[0] = '0' + (char)(speed / 1000 % 10);
speed_buf[1] = '0' + (char)(speed / 100 % 10);
speed_buf[2] = '0' + (char)(speed / 10 % 10);
speed_buf[3] = '0' + (char)(speed % 10);
speed_buf[4] = 0;
speed_str = speed_buf;
}
raw_log("[e1000] link=up speed=");
raw_log(speed_str);
raw_log("Mbps duplex=");
raw_log(fd ? "full" : "half");
raw_log("\n");
} else {
raw_log("[e1000] link=down\n");
}
raw_hex("[e1000] STATUS=", g_mmio ? g_mmio[E1000_STATUS/4] : 0);
}
/* 等待链路就绪（最长 2 秒），实机 PHY 自动协商可能需要时间 */
static int e1000_wait_for_link(void) {
if (!g_mmio) return -1;
/* 设置 ASDE (Auto-Speed Detect Enable) 让 PHY 自动协商 */
if (g_device_family == 1) {
/* e1000e: 建议先清除 FRCSPD/FRCDPLX，让自动协商生效 */
u32 ctrl = g_mmio[E1000_CTRL/4];
ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPLX);
ctrl |= E1000_CTRL_SLU | E1000_CTRL_ASDE;
g_mmio[E1000_CTRL/4] = ctrl;
}
u64 deadline = dkm_rdtsc() + dkm_tsc_per_ms * 2000;
while (dkm_rdtsc() < deadline) {
if (e1000_link_up()) return 0;
__asm__ volatile("pause");
}
return -1; /* 链路未就绪但驱动继续初始化（后续可能 link up） */
}
static int irq_handler(u8 irq) {
(void)irq;
if (!g_mmio) return 0;
u32 icr = g_mmio[E1000_ICR/4];
if (icr) {
g_stat_irq_count++;
DKM_STAT_INC(e1k_irq_count);
g_mmio[E1000_ICR/4] = icr; /* clear */
}
return 0;
@@ -228,7 +518,7 @@ static int e1000_init_rings(const struct dkm_dma_api *dma) {
g_tx_desc[i].status = E1000_TX_STA_DD;
}
dma_fence();
raw_log("[e1000.raw] ring/buffers allocated\n");
raw_log("[e1000] ring/buffers allocated\n");
g_mmio[E1000_RCTL/4] = 0;
g_mmio[E1000_TCTL/4] = 0;
@@ -259,19 +549,23 @@ static int e1000_init_rings(const struct dkm_dma_api *dma) {
mmio_flush();
g_rings_ready = 1;
raw_log("[e1000.raw] RX/TX rings initialized\n");
raw_log("[e1000] RX/TX rings initialized\n");
return 0;
}
static int e1000_tx(void *ctx, const void *packet, u32 length) {
(void)ctx;
raw_log("[e1000.raw] tx enter\n");
if (!g_rings_ready || !packet || length == 0 || length > E1000_TX_BUF_SIZE) return -1;
if (!g_rings_ready || !packet || length == 0 || length > E1000_TX_BUF_SIZE) {
g_stat_tx_err++;
return -1;
}
u32 index = g_tx_tail;
if (!(g_tx_desc[index].status & E1000_TX_STA_DD)) return -2;
if (!(g_tx_desc[index].status & E1000_TX_STA_DD)) {
g_stat_tx_err++;
return -2; /* TX ring full */
}
copy_bytes(g_tx_buf[index], packet, length);
dma_fence();
raw_log("[e1000.raw] tx copied\n");
g_tx_desc[index].length = (u16)length;
g_tx_desc[index].cso = 0;
g_tx_desc[index].cmd = E1000_TX_CMD_EOP | E1000_TX_CMD_IFCS | E1000_TX_CMD_RS;
@@ -287,17 +581,20 @@ static int e1000_tx(void *ctx, const void *packet, u32 length) {
while (dkm_rdtsc() < deadline) {
dma_fence();
if (g_tx_desc[index].status & E1000_TX_STA_DD) {
raw_log("[e1000.raw] tx complete\n");
g_stat_tx_ok++;
DKM_STAT_INC(e1k_tx_packets);
net_stat_tick();
return 0;
}
__asm__ volatile("pause");
}
raw_log("[e1000.raw] tx timeout\n");
raw_hex("[e1000.raw] STATUS=", g_mmio[E1000_STATUS/4]);
raw_hex("[e1000.raw] TCTL=", g_mmio[E1000_TCTL/4]);
raw_hex("[e1000.raw] TDH=", g_mmio[E1000_TDH/4]);
raw_hex("[e1000.raw] TDT=", g_mmio[E1000_TDT/4]);
raw_hex("[e1000.raw] desc.status=", g_tx_desc[index].status);
g_stat_tx_timeout++;
g_stat_tx_err++;
raw_log("[e1000] tx timeout\n");
raw_hex("[e1000] STATUS=", g_mmio[E1000_STATUS/4]);
raw_hex("[e1000] TCTL=", g_mmio[E1000_TCTL/4]);
raw_hex("[e1000] TDH=", g_mmio[E1000_TDH/4]);
raw_hex("[e1000] TDT=", g_mmio[E1000_TDT/4]);
return -3;
}
@@ -307,9 +604,10 @@ static int e1000_rx_poll(void *ctx, void *buffer, u32 capacity, u32 *out_length)
if (!g_rings_ready || !buffer || !out_length) return -1;
u32 next = (g_rx_tail + 1) % E1000_RX_DESC_COUNT;
dma_fence();
if (!(g_rx_desc[next].status & E1000_RX_STA_DD)) return 1;
if (!(g_rx_desc[next].status & E1000_RX_STA_DD)) return 1; /* no data */
u32 len = g_rx_desc[next].length;
if (len > capacity) {
g_stat_rx_overflow++;
g_rx_desc[next].status = 0;
dma_fence();
g_rx_tail = next;
@@ -324,6 +622,9 @@ static int e1000_rx_poll(void *ctx, void *buffer, u32 capacity, u32 *out_length)
g_rx_tail = next;
g_mmio[E1000_RDT/4] = g_rx_tail;
mmio_flush();
g_stat_rx_ok++;
DKM_STAT_INC(e1k_rx_packets);
net_stat_tick();
return 0;
}
@@ -332,58 +633,81 @@ int driver_init(const struct dkm_kernel_api *api,
struct dkm_driver_handle *handle) {
/* 实机要求: 先校准 TSC, 再使用基于 CPU 频率的延迟 */
dkm_tsc_calibrate();
raw_log("[e1000.raw] driver_init entered\n");
raw_log("[e1000] driver_init entered\n");
(void)handle;
if (!api||!api->log) return -1;
g_log=api->log;
dkm_instr_init(api);
raw_log("[e1000.raw] before find\n");
u8 bus, dev;
if (e1000_find(&bus,&dev)!=0) {
raw_log("[e1000.raw] device not found\n");
u8 bus, dev, func;
const struct e1000_device_id *dev_id = 0;
if (e1000_find(&bus, &dev, &func, &dev_id) != 0) {
raw_log("[e1000] device not found\n");
return 0;
}
raw_log("[e1000.raw] found device\n");
g_device_id = (u16)(pci_read(bus, dev, func, PCI_VENDOR_ID) >> 16);
g_device_family = dev_id ? dev_id->family : 0;
raw_log("[e1000] found device: ");
raw_log(dev_id ? dev_id->name : "unknown");
raw_log(g_device_family == 1 ? " (e1000e)" : " (classic)");
raw_log("\n");
raw_hex("[e1000] PCI bus:dev:func=", ((u64)bus << 16) | ((u64)dev << 8) | func);
u32 cmd = pci_read(bus, dev, 0, PCI_COMMAND);
cmd |= 0x0007u; /* IO Space | Memory Space | Bus Master */
pci_write(bus, dev, 0, PCI_COMMAND, cmd);
raw_log("[e1000.raw] PCI command enabled\n");
/* 检查 PCI class code 确认是网络设备 (class=0x02) */
u32 class_reg = pci_read(bus, dev, func, 0x08);
u8 class_code = (u8)(class_reg >> 24);
if (class_code != 0x02) {
raw_log("[e1000] WARNING: PCI class is not Network\n");
}
u32 bar0 = pci_read(bus,dev,0,PCI_BAR0);
u32 cmd = pci_read(bus, dev, func, PCI_COMMAND);
cmd |= PCI_CMD_IO | PCI_CMD_MEM | PCI_CMD_BUSM;
pci_write(bus, dev, func, PCI_COMMAND, cmd);
raw_log("[e1000] PCI command enabled\n");
u32 bar0 = pci_read(bus, dev, func, PCI_BAR0);
if (bar0 & 1u) {
raw_log("[e1000.raw] IO BAR unsupported\n");
raw_log("[e1000] IO BAR unsupported\n");
return 0;
}
g_bar0_phys = (u64)(bar0 & 0xFFFFFFF0ULL);
if ((bar0 & 0x6u) == 0x4u) {
u32 bar1 = pci_read(bus,dev,0,PCI_BAR1);
u32 bar1 = pci_read(bus, dev, func, PCI_BAR1);
g_bar0_phys |= ((u64)bar1 << 32);
}
raw_hex("[e1000.raw] BAR0 raw=", bar0);
raw_hex("[e1000.raw] BAR0 phys=", g_bar0_phys);
raw_hex("[e1000] BAR0 phys=", g_bar0_phys);
if (!g_bar0_phys) {
raw_log("[e1000.raw] BAR0 unavailable\n");
raw_log("[e1000] BAR0 unavailable\n");
return 0;
}
raw_log("[e1000.raw] BAR0 ok\n");
/* 真机 BAR0 可能在 4G 以上（如 I219），需 mm_map_mmio 检查 */
u64 hhdm = api->hhdm_offset;
g_mmio = (volatile u32*)(uintptr_t)(hhdm + g_bar0_phys);
(void)g_mmio[E1000_STATUS/4];
raw_log("[e1000.raw] MMIO status read ok\n");
/* 尝试读取 STATUS 寄存器验证映射是否有效 */
u32 status_val = g_mmio[E1000_STATUS/4];
(void)status_val;
raw_log("[e1000] MMIO status read ok\n");
/* 软件复位，确保 RX/TX/RAL/RAH 从已知状态开始配置。 */
g_mmio[E1000_CTRL/4] = g_mmio[E1000_CTRL/4] | (1u << 26);
g_mmio[E1000_CTRL/4] = g_mmio[E1000_CTRL/4] | E1000_CTRL_RST;
/* 实机: 1秒 TSC 超时等待复位完成 */
u64 deadline = dkm_rdtsc() + dkm_tsc_per_ms * 1000;
while (dkm_rdtsc() < deadline) {
if (!(g_mmio[E1000_CTRL/4] & (1u << 26))) break;
if (!(g_mmio[E1000_CTRL/4] & E1000_CTRL_RST)) break;
__asm__ volatile("pause");
}
raw_log("[e1000.raw] reset done\n");
if (g_mmio[E1000_CTRL/4] & E1000_CTRL_RST) {
raw_log("[e1000] WARNING: reset did not complete\n");
} else {
raw_log("[e1000] reset done\n");
}
/* 等待 EEPROM 完成（实机复位后 EEPROM 状态机需要时间） */
dkm_delay_ms(1);
/* 读 MAC 地址：先尝试 RAL/RAH，空时走 EEPROM */
u32 ral = g_mmio[E1000_RAL/4];
u32 rah = g_mmio[E1000_RAH/4];
u8 mac[6];
@@ -403,60 +727,102 @@ int driver_init(const struct dkm_kernel_api *api,
mac[0]=(u8)(w0&0xff); mac[1]=(u8)(w0>>8);
mac[2]=(u8)(w1&0xff); mac[3]=(u8)(w1>>8);
mac[4]=(u8)(w2&0xff); mac[5]=(u8)(w2>>8);
raw_log("[e1000] MAC from EEPROM\n");
} else {
raw_log("[e1000] EEPROM read failed (all 0xffff)\n");
}
} else {
raw_log("[e1000] MAC from RAL/RAH\n");
}
/* 仍为全 0 时使用与虚拟机配置一致的回退 MAC，保证收发地址匹配 */
if (mac[0]==0&&mac[1]==0&&mac[2]==0&&mac[3]==0&&mac[4]==0&&mac[5]==0) {
/* 仍为全 0 或多播位错误时使用与虚拟机配置一致的回退 MAC */
if ((mac[0]==0&&mac[1]==0&&mac[2]==0&&mac[3]==0&&mac[4]==0&&mac[5]==0) ||
(mac[0] & 1)) {
mac[0]=0x52; mac[1]=0x54; mac[2]=0x00; mac[3]=0x12; mac[4]=0x34; mac[5]=0x56;
raw_log("[e1000.raw] using fallback MAC 52:54:00:12:34:56\n");
raw_log("[e1000] using fallback MAC 52:54:00:12:34:56\n");
}
raw_mac("[e1000] MAC=", mac);
/* 写入 RAL/RAH 并置 AV(bit31) 使能接收该单播地址 */
g_mmio[E1000_RAL/4] = (u32)mac[0] | ((u32)mac[1]<<8) | ((u32)mac[2]<<16) | ((u32)mac[3]<<24);
g_mmio[E1000_RAH/4] = (u32)mac[4] | ((u32)mac[5]<<8) | (1u<<31);
raw_log("[e1000.raw] MAC read ok\n");
dma_fence();
u32 irq_line = pci_read(bus,dev,0,PCI_IRQ_LINE) & 0xff;
u32 irq_line = pci_read(bus, dev, func, PCI_IRQ_LINE) & 0xff;
raw_hex("[e1000] IRQ line=", irq_line);
/* 设置链路：FD + SLU，并允许自动协商 */
g_mmio[E1000_CTRL/4] = g_mmio[E1000_CTRL/4] | E1000_CTRL_FD | E1000_CTRL_SLU;
raw_log("[e1000.raw] link setup\n");
mmio_flush();
g_mmio[E1000_IMC/4] = 0xffffffffu;
(void)g_mmio[E1000_ICR/4];
raw_log("[e1000.raw] interrupts masked\n");
raw_log("[e1000] interrupts masked\n");
/* 等待链路就绪（实机 PHY 自动协商可能需要 1-2 秒） */
int link_rc = e1000_wait_for_link();
if (link_rc == 0) {
raw_log("[e1000] link up after auto-negotiation\n");
} else {
raw_log("[e1000] link not yet up (will retry during operation)\n");
}
/* 打印链路诊断 */
e1000_log_link_status();
int ring_rc = e1000_init_rings(api->dma);
if (ring_rc != 0) raw_log("[e1000.raw] ring init failed\n");
if (ring_rc != 0) {
raw_log("[e1000] ring init failed\n");
raw_hex("[e1000] ring_rc=", (u64)(i32)ring_rc);
}
/* 根据链路状态设置 netdev flags */
u32 netdev_flags = 0;
if (e1000_link_up()) netdev_flags |= DKM_NET_F_LINK_UP;
if (g_rings_ready) netdev_flags |= DKM_NET_F_TX_READY | DKM_NET_F_RX_READY;
if (api->net && api->net->register_device) {
struct dkm_net_device_desc netdev;
zero_bytes(&netdev, sizeof(netdev));
netdev.name = "e1000";
for (int i=0;i<6;i++) netdev.mac[i] = mac[i];
netdev.flags = DKM_NET_F_LINK_UP;
if (g_rings_ready) netdev.flags |= DKM_NET_F_TX_READY | DKM_NET_F_RX_READY;
netdev.flags = netdev_flags;
netdev.ctx = 0;
netdev.tx = g_rings_ready ? e1000_tx : 0;
netdev.rx_poll = g_rings_ready ? e1000_rx_poll : 0;
int net_index = api->net->register_device(&netdev);
(void)net_index;
raw_log("[e1000.raw] netdev registered\n");
raw_hex("[e1000] netdev registered, index=", (u64)(i32)net_index);
} else {
raw_log("[e1000.raw] net API unavailable\n");
raw_log("[e1000] net API unavailable\n");
}
g_mmio[E1000_IMC/4] = 0xffffffffu;
if (api->irq_register && irq_line < 16) {
if (api->irq_register && irq_line < 16 && irq_line > 0) {
api->irq_register((u8)irq_line, (void*)(uintptr_t)irq_handler);
raw_log("[e1000.raw] IRQ registered\n");
raw_log("[e1000] IRQ registered\n");
} else {
raw_log("[e1000] IRQ not registered (polling mode)\n");
}
raw_log("[e1000.raw] driver ready\n");
/* 最终诊断快照 */
e1000_log_link_status();
raw_log("[e1000] driver ready\n");
return 0;
}
__attribute__((visibility("default")))
int driver_exit(struct dkm_driver_handle *handle) {
(void)handle; return 0;
(void)handle;
/* 关闭 RX/TX，释放 rings */
if (g_mmio) {
g_mmio[E1000_RCTL/4] = 0;
g_mmio[E1000_TCTL/4] = 0;
g_mmio[E1000_IMC/4] = 0xffffffffu;
mmio_flush();
}
g_rings_ready = 0;
g_mmio = 0;
return 0;
}
CODE/DKM/fat32/fat32.c
+10 -52
View File
@@ -6,60 +6,15 @@
#include <stdint.h>
#include "../dkm_shared.h"
#include "../dkm_instr.h"
DKM_STAT_DECL(fat0_reads);
DKM_STAT_DECL(fat0_fat_walks);
/* ---------------------------------------------------------------
* DKM ABI types
* FAT32-specific types (DKM ABI types come from dkm_shared.h)
* --------------------------------------------------------------- */
#define DKM_DRIVER_MAGIC 0x444B4D31u
#define DKM_ABI_VERSION 1u
typedef unsigned char u8;
typedef unsigned short u16;
typedef unsigned int u32;
typedef unsigned long long u64;
typedef long long i64;
#define NULL ((void *)0)
struct dkm_log_api {
void (*info)(const char *msg);
void (*warn)(const char *msg);
void (*error)(const char *msg);
void (*panic)(const char *msg);
};
struct dkm_block_api {
int (*register_device)(const void *desc);
u32 (*device_count)(void);
int (*read)(u32 index, u64 lba, u32 count, void *buffer);
int (*write)(u32 index, u64 lba, u32 count, const void *buffer);
u64 (*sector_size)(u32 index);
const char *(*device_name)(u32 index);
int (*set_write_fn)(u32 index, int (*fn)(void *ctx, u64 lba, u32 count, const void *buf));
};
struct dkm_kernel_api {
u32 version; u32 size; u64 feature_bits;
const struct dkm_log_api *log;
const void *mem,*utsm,*irq,*pci_api,*dma,*vfs_api,*net,*timer,*drr;
const void *rsdp_address;
const void *fb_address;
u64 fb_width,fb_height,fb_pitch; u16 fb_bpp;
const void *boot_modules_response;
int (*irq_register)(u8 irq, void *handler);
u64 hhdm_offset;
const struct dkm_block_api *block;
};
struct dkm_driver_handle;
struct dkm_driver_desc {
u32 magic; u16 abi_version; u16 desc_size;
const char *name,*version,*vendor;
u32 driver_class,stage,flags,priority;
const char *const *depends; u32 depends_count;
const char *const *provides; u32 provides_count;
u64 min_kernel_abi,feature_bits,reserved0,reserved1;
};
struct limine_file {
u64 revision; void *address; u64 size; char *path; char *cmdline; u8 _pad[56];
@@ -237,6 +192,7 @@ int driver_init(const struct dkm_kernel_api *api,
(void)handle;
if (!api||!api->log) return -1;
g_log=api->log;
dkm_instr_init(api);
u64 disk_size = 0;
const u8 *disk = fat32_select_disk_image(api, &disk_size);
@@ -279,6 +235,7 @@ int driver_init(const struct dkm_kernel_api *api,
/* try to read README.TXT content */
if (strneq(dir[e].name,"README TXT",11)) {
DKM_STAT_INC(fat0_reads);
u32 f_clus = read_u16_le((const u8*)&dir[e].cluster_low);
u32 f_off = data_start + (f_clus - 2)*cluster_size;
u32 f_size = dir[e].file_size;
@@ -297,6 +254,7 @@ int driver_init(const struct dkm_kernel_api *api,
/* read next cluster from FAT */
u32 fat_ent_off = fat_start + clus * 4;
clus = read_u32_le(disk + fat_ent_off) & 0x0FFFFFFF;
DKM_STAT_INC(fat0_fat_walks);
}
g_log->info("[fat32] driver ready");
CODE/DKM/nvme/nvme.c
+802 -208
View File
@@ -1,76 +1,27 @@
/* DKM NVMe Driver — PCI NVMe discovery and controller register enumeration
/* DKM NVMe Driver — 高位 BAR MMIO 映射 + admin/IO queue + block provider
*
* Stage 1 optional storage driver, depends on "pci" and "irq", provides "block".
* This first version only discovers NVMe controllers and reads BAR0 registers;
* it does not enable queues or submit admin commands.
*
* 实现要点:
* 1. 64-bit BAR 常位于 4G 以上（QEMU/OVMF 把 NVMe BAR0 放到 ~48GiB），
* HHDM 直映射不保证覆盖。访问前先用 kernel_api.mmio->is_mapped 做
* 四级页表 walk 核实；未映射则 map_mmio 原地补建 4KiB UC 页。
* 2. 同步轮询模型: 单 outstanding 命令 + CQE phase bit 轮询 + TSC 超时,
* 不依赖 IRQ/MSI（当前 PIC/APIC 后端未完工）。
* 3. 数据面: 32 页 (128KiB) 物理连续 DMA bounce buffer + 单页 PRP list。
* PRP 布局按传输页数分档: 1 页单 PRP1; 2 页 PRP2 直连第二页;
* >=3 页 PRP2 指向 PRP list 页 (512 项 u64, 上限 513 页 = 2052KiB)。
* chunk 上限 = min(buffer 页数, 2^MDTS 页, NLB 16-bit)。
* 读写一律 bounce: 调用方缓冲是任意虚拟地址 (DSK BSS / vmm dbuf),
* 物理底账未知, 统一经 DMA 缓冲中转, 一次命令读满 chunk 再 memcpy。
* WRITE 路径 memcpy 后 wbinvd (沿用 ahci BUG-P0-2 防陈旧 cache 先例),
* 每次写调用末尾随一个 FLUSH。admin/IO queue 各 64 项, 均每队列一页。
*/
#include <stdint.h>
#include "../dkm_shared.h"
#include "../dkm_instr.h"
#define DKM_DRIVER_MAGIC 0x444B4D31u
#define DKM_ABI_VERSION 1u
typedef unsigned char u8;
typedef unsigned short u16;
typedef unsigned int u32;
typedef unsigned long long u64;
typedef long long i64;
#define NULL ((void *)0)
struct dkm_log_api {
void (*info)(const char *msg);
void (*warn)(const char *msg);
void (*error)(const char *msg);
void (*panic)(const char *msg);
};
struct dkm_kernel_api {
u32 version;
u32 size;
u64 feature_bits;
const struct dkm_log_api *log;
const void *mem;
const void *utsm;
const void *irq;
const void *pci;
const void *dma;
const void *vfs;
const void *net;
const void *timer;
const void *drr;
const void *rsdp_address;
const void *fb_address;
u64 fb_width;
u64 fb_height;
u64 fb_pitch;
u16 fb_bpp;
const void *boot_modules_response;
int (*irq_register)(u8 irq, void *handler);
u64 hhdm_offset;
};
struct dkm_driver_handle;
struct dkm_driver_desc {
u32 magic;
u16 abi_version;
u16 desc_size;
const char *name;
const char *version;
const char *vendor;
u32 driver_class;
u32 stage;
u32 flags;
u32 priority;
const char *const *depends;
u32 depends_count;
const char *const *provides;
u32 provides_count;
u64 min_kernel_abi;
u64 feature_bits;
u64 reserved0;
u64 reserved1;
};
DKM_STAT_DECL(nvm0_pci_found);
static const char *const g_depends[] = { "pci", "irq" };
static const char *const g_provides[] = { "block" };
@@ -81,7 +32,7 @@ const struct dkm_driver_desc driver_desc = {
.abi_version = DKM_ABI_VERSION,
.desc_size = sizeof(struct dkm_driver_desc),
.name = "nvme",
.version = "0.1.0",
.version = "0.3.0",
.vendor = "Deshab",
.driver_class = 6, /* DKM_CLASS_STORAGE */
.stage = 1,
@@ -97,78 +48,69 @@ const struct dkm_driver_desc driver_desc = {
.reserved1 = 0
};
#define PCI_ADDR 0xCF8
#define PCI_DATA 0xCFC
#define PCI_VENDOR_ID 0x00
#define PCI_COMMAND 0x04
#define PCI_CLASS_REG 0x08
#define PCI_HEADER 0x0E
#define PCI_BAR0 0x10
#define PCI_BAR1 0x14
#define PCI_IRQ_LINE 0x3C
#define PCI_CMD_MEM (1u << 1)
#define PCI_CMD_BUSM (1u << 2)
/* ---- NVMe 控制器寄存器 ---- */
#define NVME_CAP 0x00 /* u64 capabilities */
#define NVME_VS 0x08 /* u32 version */
#define NVME_INTMS 0x0C /* interrupt mask set */
#define NVME_INTMC 0x10 /* interrupt mask clear */
#define NVME_CC 0x14 /* controller configuration */
#define NVME_CSTS 0x1C /* controller status */
#define NVME_AQA 0x24 /* admin queue attributes */
#define NVME_ASQ 0x28 /* u64 admin SQ base */
#define NVME_ACQ 0x30 /* u64 admin CQ base */
#define NVME_DB_BASE 0x1000 /* doorbell 起始偏移 */
#define NVME_CLASS_STORAGE 0x01
#define NVME_SUBCLASS_NVM 0x08
#define NVME_PROGIF_NVME 0x02
#define NVME_CAP 0x00
#define NVME_VS 0x08
#define NVME_INTMS 0x0C
#define NVME_INTMC 0x10
#define NVME_CC 0x14
#define NVME_CSTS 0x1C
#define NVME_NSSR 0x20
#define NVME_AQA 0x24
#define NVME_ASQ 0x28
#define NVME_ACQ 0x30
#define NVME_CMBLOC 0x38
#define NVME_CMBSZ 0x3C
/* admin 命令 opcode */
#define NVME_ADM_DELETE_IOSQ 0x00
#define NVME_ADM_CREATE_IOSQ 0x01
#define NVME_ADM_DELETE_IOCQ 0x04
#define NVME_ADM_CREATE_IOCQ 0x05
#define NVME_ADM_IDENTIFY 0x06
/* IO 命令 opcode（NVM 命令集: 00h=Flush, 01h=Write, 02h=Read） */
#define NVME_IO_FLUSH 0x00
#define NVME_IO_READ 0x02
#define NVME_IO_WRITE 0x01
#define ADMIN_QSIZE 64 /* entry 数（SQ 64*64B=4K 一页, CQ 64*16B=1K） */
#define IO_QSIZE 64
#define NVME_IDENT_BYTES 4096 /* identify 数据页 */
#define NVME_DATA_PAGES 32u /* IO bounce: 128KiB = 512B×256 扇区,
* 正好覆盖 DSK FAT32 的 256 扇区批量读 */
#define NVME_PRP_LIST_ENTRIES 512u /* 单 list 页 4KiB / 8B = 512 项 */
static const struct dkm_log_api *g_log;
static volatile u8 *g_regs;
static volatile u8 *g_regs; /* MMIO 基址（虚拟） */
static u32 g_db_stride; /* doorbell 步长 = 4 << CAP.DSTRD */
static u64 g_timeout_ms; /* CAP.TO * 500ms */
static __inline__ void outl(u16 port, u32 value) {
__asm__ volatile ("outl %0, %1" :: "a"(value), "Nd"(port));
}
static struct dkm_dma_buffer g_asq; /* admin SQ */
static struct dkm_dma_buffer g_acq; /* admin CQ */
static struct dkm_dma_buffer g_ident; /* identify 数据页 */
static struct dkm_dma_buffer g_data; /* IO 读写 bounce (NVME_DATA_PAGES 页连续) */
static struct dkm_dma_buffer g_prp; /* PRP list 页 */
static struct dkm_dma_buffer g_iosq; /* IO SQ (qid=1) */
static struct dkm_dma_buffer g_iocq; /* IO CQ (qid=1) */
static __inline__ u32 inl(u16 port) {
u32 value;
__asm__ volatile ("inl %1, %0" : "=a"(value) : "Nd"(port));
return value;
}
static u32 g_asq_tail;
static u32 g_acq_head;
static u32 g_acq_phase;
static u32 g_iosq_tail;
static u32 g_iocq_head;
static u32 g_iocq_phase;
static u16 g_cid;
static u32 pci_read(u8 bus, u8 dev, u8 func, u8 reg) {
u32 addr = (1u << 31)
| ((u32)bus << 16)
| ((u32)dev << 11)
| ((u32)func << 8)
| ((u32)reg & 0xFC);
outl(PCI_ADDR, addr);
return inl(PCI_DATA);
}
static u64 g_sector_size;
static u64 g_sector_count;
static u32 g_mdts; /* Identify Controller byte 77 */
static u32 g_chunk_max_sectors; /* 单命令扇区上限 (buffer/MDTS/NLB 取小) */
static int g_io_ready;
static int g_test_disk; /* LBA0 带 DESHABNVME0 签名的测试盘 */
static void pci_write(u8 bus, u8 dev, u8 func, u8 reg, u32 value) {
u32 addr = (1u << 31)
| ((u32)bus << 16)
| ((u32)dev << 11)
| ((u32)func << 8)
| ((u32)reg & 0xFC);
outl(PCI_ADDR, addr);
outl(PCI_DATA, value);
}
static u32 mmio_read32(u32 off) {
return *(volatile u32 *)(void *)(g_regs + off);
}
static u64 mmio_read64(u32 off) {
u32 lo = mmio_read32(off);
u32 hi = mmio_read32(off + 4);
return ((u64)hi << 32) | lo;
}
/* ---- 基础工具 ---- */
static void log_hex(const char *prefix, u64 value) {
static const char hex[] = "0123456789abcdef";
@@ -184,19 +126,66 @@ static void log_hex(const char *prefix, u64 value) {
g_log->info(buf);
}
/* 打印有界 ASCII 串（identify 数据中的 SN/MN 等定长字段） */
static void log_str(const char *prefix, const u8 *src, u32 len) {
char buf[48];
if (len > 40) len = 40;
for (u32 i = 0; i < len; i++) {
char c = (char)src[i];
buf[i] = (c >= 32 && c < 127) ? c : ' ';
}
buf[len] = 0;
g_log->info(prefix);
g_log->info(buf);
}
static void nvme_zero(void *ptr, u32 len) {
u8 *p = (u8 *)ptr;
for (u32 i = 0; i < len; i++) p[i] = 0;
}
static __inline__ void nvme_mb(void) {
/* x86 TSO 保证 store-store 顺序, 这里只需阻断编译器重排 */
__asm__ volatile("" ::: "memory");
}
static u32 mmio_read32(u32 off) {
return *(volatile u32 *)(void *)(g_regs + off);
}
static void mmio_write32(u32 off, u32 value) {
*(volatile u32 *)(void *)(g_regs + off) = value;
}
static u64 mmio_read64(u32 off) {
u32 lo = mmio_read32(off);
u32 hi = mmio_read32(off + 4);
return ((u64)hi << 32) | lo;
}
static void mmio_write64(u32 off, u64 value) {
mmio_write32(off, (u32)(value & 0xffffffffu));
mmio_write32(off + 4, (u32)(value >> 32));
}
static u32 sq_tail_db(u16 qid) { return NVME_DB_BASE + (2u * qid) * g_db_stride; }
static u32 cq_head_db(u16 qid) { return NVME_DB_BASE + (2u * qid + 1u) * g_db_stride; }
/* ---- PCI ---- */
static int nvme_find(u8 *out_bus, u8 *out_dev, u8 *out_func) {
for (u8 bus = 0; bus < 16; bus++) {
for (u8 dev = 0; dev < 32; dev++) {
u32 vd = pci_read(bus, dev, 0, PCI_VENDOR_ID);
u32 vd = dkm_pci_read(bus, dev, 0, PCI_VENDOR_ID);
if ((vd & 0xffff) == 0xffff) continue;
u8 header = (u8)(pci_read(bus, dev, 0, PCI_HEADER) >> 16);
u8 header = (u8)(dkm_pci_read(bus, dev, 0, PCI_HEADER) >> 16);
u8 func_count = (header & 0x80) ? 8 : 1;
for (u8 func = 0; func < func_count; func++) {
u32 vd2 = pci_read(bus, dev, func, PCI_VENDOR_ID);
u32 vd2 = dkm_pci_read(bus, dev, func, PCI_VENDOR_ID);
if ((vd2 & 0xffff) == 0xffff) continue;
u32 class_reg = pci_read(bus, dev, func, PCI_CLASS_REG);
u32 class_reg = dkm_pci_read(bus, dev, func, 0x08);
u8 prog_if = (u8)((class_reg >> 8) & 0xff);
u8 subclass = (u8)((class_reg >> 16) & 0xff);
u8 class_code = (u8)((class_reg >> 24) & 0xff);
@@ -215,37 +204,477 @@ static int nvme_find(u8 *out_bus, u8 *out_dev, u8 *out_func) {
return -1;
}
static void log_nvme_version(u32 vs) {
log_hex("[nvme] version major=", (vs >> 16) & 0xffff);
log_hex("[nvme] version minor=", (vs >> 8) & 0xff);
log_hex("[nvme] version tertiary=", vs & 0xff);
/* ---- CSTS 等待 ---- */
static int nvme_wait_csts(u32 mask, u32 expect, u64 timeout_ms) {
u64 deadline = dkm_rdtsc() + dkm_tsc_per_ms * timeout_ms;
for (;;) {
u32 csts = mmio_read32(NVME_CSTS);
if (csts & (1u << 1)) { /* CFS: controller fatal status */
g_log->error("[nvme] CSTS.CFS set");
log_hex("[nvme] CSTS=", csts);
return -2;
}
if ((csts & mask) == expect) return 0;
if (dkm_rdtsc() > deadline) {
g_log->error("[nvme] CSTS wait timeout");
log_hex("[nvme] CSTS=", csts);
log_hex("[nvme] wait mask=", mask);
return -1;
}
__asm__ volatile("pause");
}
}
static void log_cap_fields(u64 cap) {
log_hex("[nvme] CAP.MQES=", cap & 0xffff);
log_hex("[nvme] CAP.CQR=", (cap >> 16) & 1);
log_hex("[nvme] CAP.AMS=", (cap >> 17) & 3);
log_hex("[nvme] CAP.TO=", (cap >> 24) & 0xff);
log_hex("[nvme] CAP.DSTRD=", (cap >> 32) & 0xf);
log_hex("[nvme] CAP.NSSRS=", (cap >> 36) & 1);
log_hex("[nvme] CAP.CSS=", (cap >> 37) & 0xff);
log_hex("[nvme] CAP.MPSMIN=", (cap >> 48) & 0xf);
log_hex("[nvme] CAP.MPSMAX=", (cap >> 52) & 0xf);
/* 前向声明: nvme_dump_regs 在 nvme_submit 中使用 */
static void nvme_dump_regs(const char *ctx);
/* ---- 命令提交（同步轮询, 单 outstanding） ----
* dw[16] 为完整 SQE（dw0 低 16 位不含 CID, 由本函数填入）。
* 返回 0 成功；>0 = NVMe status code；<0 超时/内部错误。
*/
static int nvme_submit(volatile u32 *sq, u32 *sq_tail, u16 sq_qid,
volatile u32 *cq, u32 *cq_head, u32 *cq_phase,
u16 cq_qid, u32 qsize, u32 *dw, u32 *out_cqe_dw0) {
dw[0] = (dw[0] & 0xffffu) | ((u32)g_cid << 16);
u32 cid = g_cid;
g_cid++;
/* 逐 dword 写入 SQE（64B），避免 freestanding 下编译器生成 memcpy 调用 */
u32 pos = *sq_tail;
for (u32 i = 0; i < 16; i++) sq[pos * 16 + i] = dw[i];
*sq_tail = (pos + 1) % qsize;
nvme_mb(); /* SQ 内容先于 doorbell 可见 */
mmio_write32(sq_tail_db(sq_qid), *sq_tail);
/* 真机超时: 使用 CAP.TO * 500ms * 10 (留 10 倍余量), 下限 5s。
* 真机 NVMe 控制器在重负载下可能需要更长的完成时间。 */
u64 submit_timeout_ms = g_timeout_ms * 10;
if (submit_timeout_ms < 5000) submit_timeout_ms = 5000;
u64 deadline = dkm_rdtsc() + dkm_tsc_per_ms * submit_timeout_ms;
for (;;) {
u32 dw3 = cq[*cq_head * 4 + 3];
if (((dw3 >> 16) & 1u) == *cq_phase) {
u32 sc = (dw3 >> 17) & 0xffu;
u32 sct = (dw3 >> 25) & 0x7u;
if (out_cqe_dw0) *out_cqe_dw0 = cq[*cq_head * 4 + 0];
*cq_head = (*cq_head + 1) % qsize;
if (*cq_head == 0) *cq_phase ^= 1u;
nvme_mb();
mmio_write32(cq_head_db(cq_qid), *cq_head);
if (sc || sct) {
g_log->error("[nvme] command failed");
log_hex("[nvme] opcode=", dw[0] & 0xffu);
log_hex("[nvme] cid=", cid);
log_hex("[nvme] SC=", sc);
log_hex("[nvme] SCT=", sct);
/* SC 与 SCT 必须联合编码: SCT!=0 且 SC==0 时只返回 sc
* 会返回 0 被调用方误判为成功（CQID_INVALID 正是此类）。 */
return (int)(sc | (sct << 8));
}
return 0;
}
if (dkm_rdtsc() > deadline) {
g_log->error("[nvme] completion timeout");
log_hex("[nvme] opcode=", dw[0] & 0xffu);
nvme_dump_regs("completion timeout");
return -100;
}
__asm__ volatile("pause");
}
}
static int nvme_admin_submit(u32 *dw, u32 *out_cqe_dw0) {
return nvme_submit((volatile u32 *)g_asq.virt, &g_asq_tail, 0,
(volatile u32 *)g_acq.virt, &g_acq_head, &g_acq_phase,
0, ADMIN_QSIZE, dw, out_cqe_dw0);
}
static int nvme_io_submit(u32 *dw, u32 *out_cqe_dw0) {
return nvme_submit((volatile u32 *)g_iosq.virt, &g_iosq_tail, 1,
(volatile u32 *)g_iocq.virt, &g_iocq_head, &g_iocq_phase,
1, IO_QSIZE, dw, out_cqe_dw0);
}
/* ---- Identify ---- */
static int nvme_identify_controller(u32 *out_nn) {
u32 dw[16];
nvme_zero(dw, sizeof(dw));
nvme_zero(g_ident.virt, NVME_IDENT_BYTES);
dw[0] = NVME_ADM_IDENTIFY;
dw[1] = 0; /* NSID=0 for controller */
dw[6] = (u32)(g_ident.phys & 0xffffffffu);
dw[7] = (u32)(g_ident.phys >> 32);
dw[10] = 1; /* CNS=1: identify controller */
int rc = nvme_admin_submit(dw, 0);
if (rc != 0) return rc;
u8 *id = (u8 *)g_ident.virt;
log_str("[nvme] ctrl SN=", id + 4, 20);
log_str("[nvme] ctrl MN=", id + 24, 40);
log_str("[nvme] ctrl FR=", id + 64, 8);
/* Identify Controller 布局锚点核对（NVMe 1.4, CNS=1 数据结构）:
* byte 77 MDTS u8 最大传输 = 2^MDTS × CAP.MPSMIN 页, 0=无限制
* byte 512 SQES/CQES/MAXCMD —— QEMU 实测 0x00004466, 证明偏移基正确
* byte 516 NN u32 Number of Namespaces
* NN 核实结论 (QEMU 11.0 串口实证): NN=0x100 不是解析错位。NN 的 spec
* 语义是"控制器支持的最大合法 NSID 数"而非已挂载数量; QEMU hw/nvme
* 填的是 NVME_MAX_NAMESPACES=256 (0x100)。实际挂载的 NSID=1 由后续
* Identify Namespace(CNS=0) 成功返回确认。解析偏移 516 与 spec 一致,
* 无需修正。 */
u32 anchor512 = (u32)id[512] | ((u32)id[513] << 8) |
((u32)id[514] << 16) | ((u32)id[515] << 24);
log_hex("[nvme] ID dword@512(SQES/CQES/MAXCMD)=", anchor512);
u32 nn = (u32)id[516] | ((u32)id[517] << 8) | ((u32)id[518] << 16) | ((u32)id[519] << 24);
log_hex("[nvme] NN(max valid NSID)=", nn);
log_hex("[nvme] MDTS=", id[77]);
g_mdts = id[77];
*out_nn = nn;
return 0;
}
static int nvme_identify_namespace(u32 nsid, u64 *out_nsze, u32 *out_lbads) {
u32 dw[16];
nvme_zero(dw, sizeof(dw));
nvme_zero(g_ident.virt, NVME_IDENT_BYTES);
dw[0] = NVME_ADM_IDENTIFY;
dw[1] = nsid;
dw[6] = (u32)(g_ident.phys & 0xffffffffu);
dw[7] = (u32)(g_ident.phys >> 32);
dw[10] = 0; /* CNS=0: identify namespace */
int rc = nvme_admin_submit(dw, 0);
if (rc != 0) return rc;
u8 *id = (u8 *)g_ident.virt;
u64 nsze = 0;
for (u32 i = 0; i < 8; i++) nsze |= ((u64)id[i]) << (i * 8);
u8 flbas = id[26] & 0x0f;
u32 lbaf_off = 128 + (u32)flbas * 4;
u32 lbaf = (u32)id[lbaf_off] | ((u32)id[lbaf_off + 1] << 8) |
((u32)id[lbaf_off + 2] << 16) | ((u32)id[lbaf_off + 3] << 24);
u32 lbads = (lbaf >> 16) & 0xff;
log_hex("[nvme] NSZE=", nsze);
log_hex("[nvme] FLBAS=", flbas);
log_hex("[nvme] LBADS=", lbads);
*out_nsze = nsze;
*out_lbads = lbads;
return 0;
}
/* ---- IO queue 创建 ---- */
static int nvme_create_io_queues(void) {
u32 dw[16];
/* Create IO CQ (qid=1): PC=1, IEN=0 (轮询模式)
* CDW10 = QSIZE[31:16](0's based) | QID[15:0] —— QID 必须在低半字 */
nvme_zero(dw, sizeof(dw));
dw[0] = NVME_ADM_CREATE_IOCQ;
dw[6] = (u32)(g_iocq.phys & 0xffffffffu);
dw[7] = (u32)(g_iocq.phys >> 32);
dw[10] = ((u32)(IO_QSIZE - 1u) << 16) | 1u;
dw[11] = 1;
int rc = nvme_admin_submit(dw, 0);
if (rc != 0) {
g_log->error("[nvme] create IO CQ failed");
return rc;
}
/* Create IO SQ (qid=1, cqid=1): PC=1
* CDW10 同 Create IOCQ: QSIZE[31:16] | QID[15:0]; CDW11 = CQID[31:16] | PC */
nvme_zero(dw, sizeof(dw));
dw[0] = NVME_ADM_CREATE_IOSQ;
dw[6] = (u32)(g_iosq.phys & 0xffffffffu);
dw[7] = (u32)(g_iosq.phys >> 32);
dw[10] = ((u32)(IO_QSIZE - 1u) << 16) | 1u;
dw[11] = (1u << 16) | 1;
rc = nvme_admin_submit(dw, 0);
if (rc != 0) {
g_log->error("[nvme] create IO SQ failed");
return rc;
}
g_iosq_tail = 0;
g_iocq_head = 0;
g_iocq_phase = 1;
return 0;
}
/* ---- IO Read/Write（PRP1 + PRP2 直连 / PRP list 分档） ----
* buf_phys 必须 4KiB 对齐且物理连续（本驱动只传 g_data.phys）。
* 传输页数由 nlb × sector_size 推出，决定 PRP 布局:
* 1 页 : PRP2 = 0（单 PRP1，等价旧 bounce 路径）
* 2 页 : PRP2 = 第二页物理地址（spec 规定的两页直连形式）
* >=3 页: PRP2 = g_prp list 页物理地址, list[i] = 第 i+2 页物理地址
* 单 list 页 512 项, 上限 513 页 (2052KiB), 远大于 chunk 上限 32 页,
* 无需 list 链页。PRP list 由 CPU 写、控制器 DMA 读: x86 TSO + 编译屏障
* 保证 list 先于 doorbell 可见（与 SQE 提交路径同一约定）。
*/
static int nvme_io_rw(u8 opcode, u64 slba, u32 nlb, u64 buf_phys) {
u32 bytes = nlb * (u32)g_sector_size;
u32 pages = (bytes + 4095u) >> 12;
if (pages == 0 || (pages - 1u) > NVME_PRP_LIST_ENTRIES) return -3;
u32 dw[16];
nvme_zero(dw, sizeof(dw));
dw[0] = opcode;
dw[1] = 1; /* nsid=1 */
dw[6] = (u32)(buf_phys & 0xffffffffu);
dw[7] = (u32)(buf_phys >> 32);
if (pages == 2) {
u64 p2 = buf_phys + 4096u;
dw[8] = (u32)(p2 & 0xffffffffu);
dw[9] = (u32)(p2 >> 32);
} else if (pages >= 3) {
volatile u64 *list = (volatile u64 *)g_prp.virt;
for (u32 i = 0; i < pages - 1u; i++)
list[i] = buf_phys + 4096ULL * (u64)(i + 1u);
nvme_mb(); /* list 内容先于 doorbell 可见 */
dw[8] = (u32)(g_prp.phys & 0xffffffffu);
dw[9] = (u32)(g_prp.phys >> 32);
}
dw[10] = (u32)(slba & 0xffffffffu);
dw[11] = (u32)(slba >> 32);
dw[12] = nlb - 1u; /* NLB 0-based */
return nvme_io_submit(dw, 0);
}
/* NVM Flush (opcode 0x00): 无数据字段, 把 volatile write cache 刷到介质 */
static int nvme_io_flush(void) {
u32 dw[16];
nvme_zero(dw, sizeof(dw));
dw[0] = NVME_IO_FLUSH;
dw[1] = 1; /* nsid=1 */
return nvme_io_submit(dw, 0);
}
/* ---- block provider ----
* 调用方缓冲为任意虚拟地址（DSK 静态 BSS、vmm virtio_blk dbuf 等），
* 物理底账未知且不一定连续/对齐，不能直接进 PRP。一律 bounce 经
* g_data（物理连续 DMA 区）: 一次命令读/写满 chunk，再 memcpy 中转。
*/
static int nvme_block_read(void *ctx, u64 lba, u32 count, void *buffer) {
(void)ctx;
if (!g_io_ready || !buffer || count == 0) return -1;
u8 *out = (u8 *)buffer;
while (count > 0) {
u32 n = count > g_chunk_max_sectors ? g_chunk_max_sectors : count;
int rc = nvme_io_rw(NVME_IO_READ, lba, n, g_data.phys);
if (rc != 0) return rc;
u32 bytes = n * (u32)g_sector_size;
u8 *src = (u8 *)g_data.virt;
for (u32 i = 0; i < bytes; i++) out[i] = src[i];
out += bytes;
lba += n;
count -= n;
}
return 0;
}
static int nvme_block_write(void *ctx, u64 lba, u32 count, const void *buffer) {
(void)ctx;
if (!g_io_ready || !buffer || count == 0) return -1;
const u8 *in = (const u8 *)buffer;
while (count > 0) {
u32 n = count > g_chunk_max_sectors ? g_chunk_max_sectors : count;
u32 bytes = n * (u32)g_sector_size;
u8 *dst = (u8 *)g_data.virt;
for (u32 i = 0; i < bytes; i++) dst[i] = in[i];
/* 沿用 ahci BUG-P0-2 先例: 写前 flush CPU cache, 防 DMA 读到陈旧数据 */
__asm__ volatile("wbinvd" ::: "memory");
int rc = nvme_io_rw(NVME_IO_WRITE, lba, n, g_data.phys);
if (rc != 0) return rc;
in += bytes;
lba += n;
count -= n;
}
/* 每次写调用末尾 FLUSH 一次，保证 volatile write cache 落盘 */
return nvme_io_flush();
}
/* ---- 数据面自测（仅签名测试盘运行写测试，防实机盘数据损坏） ---- */
/* 读回 LBA0 并核对 DESHABNVME0 签名（写测试后复查无串扰用） */
static int nvme_lba0_sig_ok(void) {
static const char sig[] = "DESHABNVME0";
int rc = nvme_io_rw(NVME_IO_READ, 0, 1, g_data.phys);
if (rc != 0) return 0;
u8 *d = (u8 *)g_data.virt;
for (u32 i = 0; i < 11; i++) {
if (d[i] != (u8)sig[i]) return 0;
}
return 1;
}
/* 多页单命令读: LBA0 起 32 扇区 = 16KiB = 4 页 → PRP list 路径。
* 测试盘内容已知: LBA0 为 "DESHABNVME0" 重复填满 512B, LBA1..31 全零。 */
static void nvme_selftest_read_multipage(void) {
static u8 rbuf[16384];
static const char sig[] = "DESHABNVME0";
int rc = nvme_block_read(0, 0, 32, rbuf);
log_hex("[nvme] PRPLIST read 32sec rc=", (u64)(i64)rc);
if (rc != 0) return;
u32 bad = 0;
for (u32 i = 0; i < 512; i++) {
if (rbuf[i] != (u8)sig[i % 11]) {
bad = 1;
log_hex("[nvme] sig mismatch idx=", i);
break;
}
}
if (!bad) {
for (u32 i = 512; i < 16384; i++) {
if (rbuf[i] != 0) {
bad = 1;
log_hex("[nvme] nonzero idx=", i);
break;
}
}
}
if (bad) {
g_log->error("[nvme] PRPLIST read verify FAILED");
} else {
g_log->info("[nvme] PRPLIST read verify OK (LBA0 sig + LBA1-31 zero)");
}
}
/* 写 → FLUSH → 读回逐字节校验。sectors=16 走 PRP2 直连(2页),
* sectors=32 走 PRP list(4页)。pattern 为首 8 字节 "NVMEWRIT" + 全缓冲
* 确定式伪随机，重跑幂等（与上次写入内容一致）。 */
static void nvme_selftest_rw(u64 lba, u32 sectors) {
static u8 wpat[16384];
static u8 rbuf[16384];
u32 bytes = sectors * (u32)g_sector_size;
if (bytes > sizeof(wpat)) return;
for (u32 i = 0; i < bytes; i++) wpat[i] = (u8)(i * 31u + 17u);
wpat[0] = 'N'; wpat[1] = 'V'; wpat[2] = 'M'; wpat[3] = 'E';
wpat[4] = 'W'; wpat[5] = 'R'; wpat[6] = 'I'; wpat[7] = 'T';
log_hex("[nvme] selftest rw lba=", lba);
log_hex("[nvme] selftest rw sectors=", sectors);
int rc = nvme_block_write(0, lba, sectors, wpat);
log_hex("[nvme] write+flush rc=", (u64)(i64)rc);
if (rc != 0) return;
for (u32 i = 0; i < bytes; i++) rbuf[i] = 0;
rc = nvme_block_read(0, lba, sectors, rbuf);
log_hex("[nvme] readback rc=", (u64)(i64)rc);
if (rc != 0) return;
for (u32 i = 0; i < bytes; i++) {
if (rbuf[i] != wpat[i]) {
g_log->error("[nvme] readback MISMATCH");
log_hex("[nvme] first bad idx=", i);
log_hex("[nvme] expect=", wpat[i]);
log_hex("[nvme] actual=", rbuf[i]);
return;
}
}
g_log->info("[nvme] write+flush+readback verify OK");
}
/* ---- 真机诊断: dump 关键寄存器 ---- */
static void nvme_dump_regs(const char *ctx) {
g_log->info("[nvme] --- register dump: ");
g_log->info(ctx);
log_hex("[nvme] CAP =", mmio_read64(NVME_CAP));
log_hex("[nvme] VS =", mmio_read32(NVME_VS));
log_hex("[nvme] CC =", mmio_read32(NVME_CC));
log_hex("[nvme] CSTS =", mmio_read32(NVME_CSTS));
log_hex("[nvme] AQA =", mmio_read32(NVME_AQA));
log_hex("[nvme] ASQ =", mmio_read64(NVME_ASQ));
log_hex("[nvme] ACQ =", mmio_read64(NVME_ACQ));
/* doorbell 区域首个 entry 诊断 */
log_hex("[nvme] SQ0DB=", mmio_read32(NVME_DB_BASE));
log_hex("[nvme] CQ0DB=", mmio_read32(NVME_DB_BASE + g_db_stride));
}
/* ---- 高位 BAR MMIO 接入 ---- */
/* 真机 NVMe 控制器寄存器 + doorbell 空间可能远大于 8K。
* 典型实机: CAP.MQES 决定队列深度，doorbell 偏移 = DB_BASE + 2*QID*DSTRD*4，
* 需要映射足够大的范围覆盖至少 admin + 1 个 IO queue 对。
* 安全映射大小: 至少 64K（覆盖 QID 0-7 的 SQ/CQ doorbell）。 */
#define NVME_MAP_SIZE 0x10000
static volatile u8 *nvme_map_bar(const struct dkm_kernel_api *api, u64 bar_phys) {
u64 bar_virt = api->hhdm_offset + bar_phys;
/* 优先使用 mm_map_mmio（独立窗口映射, PCD|PWT, 不与 HHDM 空洞竞争） */
if (api->mm_map_mmio) {
void *mapped = api->mm_map_mmio(bar_phys, NVME_MAP_SIZE);
if (mapped) {
g_log->info("[nvme] BAR mapped via mm_map_mmio window");
return (volatile u8 *)mapped;
}
g_log->warn("[nvme] mm_map_mmio failed; trying HHDM fallback");
}
if (!api->mmio || !api->mmio->is_mapped) {
/* 内核无页表服务: 仅当 BAR 位于低 4G（HHDM 经验上覆盖）时冒险直用 */
if (bar_phys < 0x100000000ULL) {
g_log->warn("[nvme] no mmio api; assume HHDM covers low BAR");
return (volatile u8 *)(uintptr_t)bar_virt;
}
g_log->warn("[nvme] no mmio api and BAR above 4G; cannot access");
return (volatile u8 *)0;
}
log_hex("[nvme] CR3=", api->mmio->cr3 ? api->mmio->cr3() : 0);
/* 核实: HHDM 是否直接覆盖该 BAR（四级页表只读 walk, 无 #PF 风险） */
int level = api->mmio->is_mapped(bar_virt);
log_hex("[nvme] HHDM is_mapped(BAR)=", (u64)(i64)level);
if (level == 0) {
g_log->info("[nvme] HHDM does NOT cover BAR; mapping via page tables");
if (!api->mmio->map_mmio) return (volatile u8 *)0;
int rc = api->mmio->map_mmio(bar_phys, NVME_MAP_SIZE);
log_hex("[nvme] map_mmio rc=", (u64)(i64)rc);
if (rc != 0) return (volatile u8 *)0;
level = api->mmio->is_mapped(bar_virt);
log_hex("[nvme] post-map is_mapped=", (u64)(i64)level);
if (level == 0) {
g_log->error("[nvme] BAR still unmapped after map_mmio");
return (volatile u8 *)0;
}
} else {
g_log->info("[nvme] HHDM already covers BAR; direct access");
}
return (volatile u8 *)(uintptr_t)bar_virt;
}
/* ---- driver entry ---- */
__attribute__((visibility("default")))
int driver_init(const struct dkm_kernel_api *api,
struct dkm_driver_handle *handle) {
(void)handle;
dkm_tsc_calibrate();
if (!api || !api->log) return -1;
g_log = api->log;
dkm_instr_init(api);
g_log->info("[nvme] init begin");
u8 bus = 0;
u8 dev = 0;
u8 func = 0;
u8 bus = 0, dev = 0, func = 0;
if (nvme_find(&bus, &dev, &func) != 0) {
g_log->warn("[nvme] NVMe controller not found");
g_log->info("[nvme] driver ready");
@@ -253,89 +682,254 @@ int driver_init(const struct dkm_kernel_api *api,
}
g_log->info("[nvme] NVMe controller found");
DKM_STAT_INC(nvm0_pci_found);
log_hex("[nvme] bus=", bus);
log_hex("[nvme] dev=", dev);
log_hex("[nvme] func=", func);
u32 vd = pci_read(bus, dev, func, PCI_VENDOR_ID);
u32 vd = dkm_pci_read(bus, dev, func, PCI_VENDOR_ID);
log_hex("[nvme] vendor=", vd & 0xffff);
log_hex("[nvme] device=", vd >> 16);
u32 command = pci_read(bus, dev, func, PCI_COMMAND) & 0xffff;
command |= PCI_CMD_MEM | PCI_CMD_BUSM;
pci_write(bus, dev, func, PCI_COMMAND, command);
/* 启用 MEM + BUSM, 并禁用 INTx（轮询模式不需要中断） */
u32 command = dkm_pci_read(bus, dev, func, PCI_COMMAND) & 0xffff;
command |= PCI_CMD_MEM | PCI_CMD_BUSM | (1u << 10);
dkm_pci_write(bus, dev, func, PCI_COMMAND, command);
log_hex("[nvme] PCI command=", command);
u32 bar0_lo = pci_read(bus, dev, func, PCI_BAR0);
u32 bar1_hi = pci_read(bus, dev, func, PCI_BAR1);
u32 bar0_lo = dkm_pci_read(bus, dev, func, PCI_BAR0);
u32 bar1_hi = dkm_pci_read(bus, dev, func, PCI_BAR1);
u64 bar_phys;
if (bar0_lo & 1u) {
g_log->warn("[nvme] BAR0 is IO space; unsupported");
g_log->info("[nvme] driver ready");
return 0;
}
if ((bar0_lo & 0x6u) == 0x4u) {
bar_phys = ((u64)bar1_hi << 32) | (u64)(bar0_lo & 0xFFFFFFF0u);
} else {
bar_phys = (u64)(bar0_lo & 0xFFFFFFF0u);
}
u32 irq_line = pci_read(bus, dev, func, PCI_IRQ_LINE) & 0xff;
u32 irq_line = dkm_pci_read(bus, dev, func, PCI_IRQ_LINE) & 0xff;
log_hex("[nvme] BAR0 phys=", bar_phys);
log_hex("[nvme] PCI IRQ line=", irq_line);
if (!api->hhdm_offset || !bar_phys) {
g_log->warn("[nvme] missing HHDM or BAR0; skip MMIO enumeration");
g_log->info("[nvme] driver ready");
return 0;
}
if (bar_phys >= 0x100000000ULL) {
g_log->warn("[nvme] BAR0 is above 4G; current HHDM MMIO map cannot safely read it");
g_log->info("[nvme] discovery only; MMIO enumeration skipped");
g_log->info("[nvme] driver ready");
return 0;
}
g_regs = (volatile u8 *)(uintptr_t)(api->hhdm_offset + bar_phys);
log_hex("[nvme] HHDM offset=", api->hhdm_offset);
u64 cap = mmio_read64(NVME_CAP);
u32 vs = mmio_read32(NVME_VS);
u32 intms = mmio_read32(NVME_INTMS);
u32 intmc = mmio_read32(NVME_INTMC);
u32 cc = mmio_read32(NVME_CC);
u32 csts = mmio_read32(NVME_CSTS);
u32 nssr = mmio_read32(NVME_NSSR);
u32 aqa = mmio_read32(NVME_AQA);
u64 asq = mmio_read64(NVME_ASQ);
u64 acq = mmio_read64(NVME_ACQ);
u32 cmbloc = mmio_read32(NVME_CMBLOC);
u32 cmbsz = mmio_read32(NVME_CMBSZ);
log_hex("[nvme] CAP=", cap);
log_cap_fields(cap);
log_hex("[nvme] VS=", vs);
log_nvme_version(vs);
log_hex("[nvme] INTMS=", intms);
log_hex("[nvme] INTMC=", intmc);
log_hex("[nvme] CC=", cc);
log_hex("[nvme] CSTS=", csts);
log_hex("[nvme] NSSR=", nssr);
log_hex("[nvme] AQA=", aqa);
log_hex("[nvme] ASQ=", asq);
log_hex("[nvme] ACQ=", acq);
log_hex("[nvme] CMBLOC=", cmbloc);
log_hex("[nvme] CMBSZ=", cmbsz);
if (cc & 1u) {
g_log->warn("[nvme] controller already enabled; leaving state unchanged");
} else {
g_log->info("[nvme] controller disabled; queues not configured");
if (!api->hhdm_offset || !bar_phys) {
g_log->warn("[nvme] missing HHDM or BAR0; skip");
g_log->info("[nvme] driver ready");
return 0;
}
g_regs = nvme_map_bar(api, bar_phys);
if (!g_regs) {
g_log->error("[nvme] BAR MMIO unavailable; driver inactive");
g_log->info("[nvme] driver ready");
return 0;
}
/* ---- 寄存器枚举（验证 MMIO 可读） ---- */
u64 cap = mmio_read64(NVME_CAP);
u32 vs = mmio_read32(NVME_VS);
u32 cc = mmio_read32(NVME_CC);
u32 csts = mmio_read32(NVME_CSTS);
log_hex("[nvme] CAP=", cap);
log_hex("[nvme] VS=", vs);
log_hex("[nvme] CC=", cc);
log_hex("[nvme] CSTS=", csts);
log_hex("[nvme] CAP.MQES=", (cap & 0xffff) + 1);
log_hex("[nvme] CAP.DSTRD=", (cap >> 32) & 0xf);
log_hex("[nvme] CAP.TO=", (cap >> 24) & 0xff);
log_hex("[nvme] CAP.CSS=", (cap >> 37) & 0xff);
log_hex("[nvme] CAP.MPSMIN=", (cap >> 48) & 0xf);
log_hex("[nvme] CAP.MPSMAX=", (cap >> 52) & 0xf);
if (cap == 0 || cap == 0xFFFFFFFFFFFFFFFFULL) {
g_log->error("[nvme] CAP invalid; MMIO read broken");
g_log->info("[nvme] driver ready");
return 0;
}
if (!((cap >> 37) & 1u)) {
g_log->error("[nvme] NVM command set not supported");
g_log->info("[nvme] driver ready");
return 0;
}
g_db_stride = 4u << ((cap >> 32) & 0xf);
g_timeout_ms = ((cap >> 24) & 0xff) * 500;
if (!g_timeout_ms) g_timeout_ms = 500;
log_hex("[nvme] doorbell stride=", g_db_stride);
log_hex("[nvme] timeout ms=", g_timeout_ms);
if (!api->dma) {
g_log->warn("[nvme] DMA API unavailable; queues not configured");
g_log->info("[nvme] driver ready");
return 0;
}
/* ---- 分配队列与数据缓冲（低 4G, 4K 对齐, 清零, 物理连续） ---- */
if (api->dma->alloc_pages(1, 4096, 0x100000000ULL, &g_asq) != 0) goto dma_fail;
if (api->dma->alloc_pages(1, 4096, 0x100000000ULL, &g_acq) != 0) goto dma_fail;
if (api->dma->alloc_pages(1, 4096, 0x100000000ULL, &g_ident) != 0) goto dma_fail;
if (api->dma->alloc_pages(NVME_DATA_PAGES, 4096, 0x100000000ULL, &g_data) != 0) goto dma_fail;
if (api->dma->alloc_pages(1, 4096, 0x100000000ULL, &g_prp) != 0) goto dma_fail;
if (api->dma->alloc_pages(1, 4096, 0x100000000ULL, &g_iosq) != 0) goto dma_fail;
if (api->dma->alloc_pages(1, 4096, 0x100000000ULL, &g_iocq) != 0) goto dma_fail;
goto dma_ok;
dma_fail:
g_log->error("[nvme] DMA alloc failed");
g_log->info("[nvme] driver ready");
return 0;
dma_ok:
log_hex("[nvme] ASQ phys=", g_asq.phys);
log_hex("[nvme] ACQ phys=", g_acq.phys);
log_hex("[nvme] DATA phys=", g_data.phys);
log_hex("[nvme] PRP list phys=", g_prp.phys);
log_hex("[nvme] IOSQ phys=", g_iosq.phys);
log_hex("[nvme] IOCQ phys=", g_iocq.phys);
/* ---- 控制器复位: EN=0 等 RDY=0 ---- */
mmio_write32(NVME_INTMS, 0xFFFFFFFFu); /* 屏蔽全部中断向量 */
cc = mmio_read32(NVME_CC);
if (cc & 1u) {
mmio_write32(NVME_CC, cc & ~1u);
}
if (nvme_wait_csts(1u, 0u, g_timeout_ms) != 0) {
g_log->error("[nvme] disable failed");
nvme_dump_regs("controller disable timeout");
g_log->info("[nvme] driver ready");
return 0;
}
g_log->info("[nvme] controller disabled");
/* ---- 配置 admin queue ---- */
mmio_write32(NVME_AQA, ((u32)(ADMIN_QSIZE - 1) << 16) | (u32)(ADMIN_QSIZE - 1));
mmio_write64(NVME_ASQ, g_asq.phys);
mmio_write64(NVME_ACQ, g_acq.phys);
g_asq_tail = 0;
g_acq_head = 0;
g_acq_phase = 1;
g_cid = 1;
/* ---- 使能: EN=1, CSS=NVM, MPS=4K, AMS=RR, IOSQES=6, IOCQES=4 ---- */
mmio_write32(NVME_CC, 0x00460001u);
if (nvme_wait_csts(1u, 1u, g_timeout_ms) != 0) {
g_log->error("[nvme] enable failed");
nvme_dump_regs("controller enable timeout");
g_log->info("[nvme] driver ready");
return 0;
}
g_log->info("[nvme] controller enabled, admin queue live");
/* ---- Identify ---- */
u32 nn = 0;
if (nvme_identify_controller(&nn) != 0) {
g_log->error("[nvme] identify controller failed");
g_log->info("[nvme] driver ready");
return 0;
}
if (nn == 0) {
g_log->warn("[nvme] no namespace");
g_log->info("[nvme] driver ready");
return 0;
}
u64 nsze = 0;
u32 lbads = 0;
if (nvme_identify_namespace(1, &nsze, &lbads) != 0) {
g_log->error("[nvme] identify namespace failed");
g_log->info("[nvme] driver ready");
return 0;
}
if (lbads < 9 || lbads > 12 || nsze == 0) {
g_log->warn("[nvme] unsupported LBA format or empty NS");
log_hex("[nvme] LBADS=", lbads);
g_log->info("[nvme] driver ready");
return 0;
}
g_sector_size = 1ULL << lbads;
g_sector_count = nsze;
log_hex("[nvme] sector size=", g_sector_size);
log_hex("[nvme] sector count=", g_sector_count);
/* ---- 单命令扇区上限: min(bounce 缓冲, 2^MDTS 页, NLB 16-bit) ----
* QEMU MDTS=7 → 512KiB, bounce 32 页=128KiB 更紧, 故 chunk=256 扇区,
* 恰好覆盖 DSK FAT32 的 256 扇区批量读（一次命令读满）。 */
{
u64 buf_bytes = (u64)NVME_DATA_PAGES * 4096u;
u64 mdts_bytes = g_mdts ? ((1ULL << g_mdts) * 4096u) : buf_bytes;
u64 cap = buf_bytes < mdts_bytes ? buf_bytes : mdts_bytes;
g_chunk_max_sectors = (u32)(cap / g_sector_size);
if (g_chunk_max_sectors > 65536u) g_chunk_max_sectors = 65536u;
if (g_chunk_max_sectors == 0) g_chunk_max_sectors = 1;
log_hex("[nvme] chunk max sectors=", g_chunk_max_sectors);
}
/* ---- IO queue ---- */
if (nvme_create_io_queues() != 0) {
g_log->error("[nvme] IO queue creation failed");
g_log->info("[nvme] driver ready");
return 0;
}
g_io_ready = 1;
g_log->info("[nvme] IO queue live");
/* ---- LBA0 读取验证 ---- */
{
int rc = nvme_io_rw(NVME_IO_READ, 0, 1, g_data.phys);
log_hex("[nvme] READ LBA0 rc=", (u64)(i64)rc);
if (rc == 0) {
u8 *d = (u8 *)g_data.virt;
u32 *w = (u32 *)g_data.virt;
log_hex("[nvme] LBA0 dword0=", w[0]);
log_hex("[nvme] LBA0 dword1=", w[1]);
log_hex("[nvme] LBA0 dword2=", w[2]);
log_hex("[nvme] LBA0 dword3=", w[3]);
static const char sig[] = "DESHABNVME0";
u32 match = 1;
for (u32 i = 0; i < 11; i++) {
if (d[i] != (u8)sig[i]) { match = 0; break; }
}
if (match) {
g_log->info("[nvme] LBA0 signature OK (DESHABNVME0)");
g_test_disk = 1;
} else {
g_log->info("[nvme] LBA0 data read (no test signature)");
}
}
}
/* ---- 注册 block provider（读 + 写） ---- */
if (api->block && api->block->register_device) {
struct dkm_block_device_desc desc;
desc.name = "nvme0";
desc.sector_size = g_sector_size;
desc.sector_count = g_sector_count;
desc.ctx = 0;
desc.read = nvme_block_read;
desc.write = nvme_block_write;
int index = api->block->register_device(&desc);
log_hex("[nvme] block provider index=", (u64)(i64)index);
} else {
g_log->warn("[nvme] block API unavailable; provider not registered");
}
/* ---- 数据面自测: 写测试仅在签名测试盘上运行（防实机盘数据损坏） ---- */
if (g_test_disk) {
nvme_selftest_read_multipage(); /* 32 扇区 16KiB: PRP list 读 */
nvme_selftest_rw(1000, 16); /* 8KiB: PRP2 直连 (2 页) 写+读回 */
nvme_selftest_rw(2000, 32); /* 16KiB: PRP list (4 页) 写+读回 */
if (nvme_lba0_sig_ok()) {
g_log->info("[nvme] LBA0 sig intact after write tests");
} else {
g_log->error("[nvme] LBA0 sig CORRUPTED after write tests");
}
} else {
g_log->info("[nvme] not a test disk; write self-test skipped");
}
g_log->info("[nvme] discovery only; admin queues disabled");
g_log->info("[nvme] driver ready");
return 0;
}
CODE/DKM/pci/pci.c
+177 -1
View File
@@ -1,6 +1,11 @@
/* DKM PCI Driver — PCI bus enumeration via config space (0xCF8/0xCFC)
* Stage 0, required, depends on "irq", provides "pci".
* No IRQ needed for enumeration. Scans all buses/devices/functions.
*
* 真机增强:
* - 多总线扫描（桥接设备下游 bus > 0）
* - 网卡型号识别（常见 Intel/Realtek 网卡芯片自动标注）
* - PCI 桥检测和副总线号读取
*/
#include <stdint.h>
@@ -82,6 +87,15 @@ struct dkm_driver_desc {
#define PCI_HEADER_TYPE 0x0E
#define PCI_BAR0 0x10
/* PCI 桥配置 (header type 1) */
#define PCI_PRI_BUS 0x18
#define PCI_SEC_BUS 0x19
#define PCI_SUB_BUS 0x1A
#define PCI_CMD_IO (1u << 0)
#define PCI_CMD_MEM (1u << 1)
#define PCI_CMD_BUSM (1u << 2)
/* ---------------------------------------------------------------
* Driver descriptor
* --------------------------------------------------------------- */
@@ -94,7 +108,7 @@ const struct dkm_driver_desc driver_desc = {
.abi_version = DKM_ABI_VERSION,
.desc_size = sizeof(struct dkm_driver_desc),
.name = "pci",
.version = "0.1.0",
.version = "0.2.0",
.vendor = "Deshab",
.driver_class = 2, /* DKM_CLASS_BUS */
.stage = 0,
@@ -164,6 +178,114 @@ static void log_hex(const char *prefix, u64 val) {
g_log->info(buf);
}
/* ---- 网卡型号识别 ---- */
struct netchip_id {
u16 vendor;
u16 device;
const char *name;
u8 driver_hint; /* 0=e1000, 1=e1000e, 2=r8169, 3=igb, 4=ath9k */
};
static const struct netchip_id g_netchips[] = {
/* Intel e1000 经典 (8254x) */
{0x8086, 0x100E, "82540EM", 0},
{0x8086, 0x1004, "82543GC", 0},
{0x8086, 0x100F, "82545EM", 0},
{0x8086, 0x1010, "82546EB", 0},
{0x8086, 0x1013, "82541EI", 0},
{0x8086, 0x1019, "82547EI", 0},
{0x8086, 0x1026, "82545GM", 0},
{0x8086, 0x1075, "82547GI", 0},
{0x8086, 0x1076, "82541GI", 0},
{0x8086, 0x1079, "82546GB", 0},
{0x8086, 0x108B, "82573E", 0},
{0x8086, 0x109A, "82573L", 0},
/* Intel e1000e (8257x/I217/I218/I219) */
{0x8086, 0x10D3, "82574L", 1},
{0x8086, 0x10F5, "82578DM", 1},
{0x8086, 0x10F6, "82578DC", 1},
{0x8086, 0x1502, "82579V", 1},
{0x8086, 0x1533, "I217-V", 1},
{0x8086, 0x1534, "I217-LM", 1},
{0x8086, 0x153A, "I218-V", 1},
{0x8086, 0x153B, "I218-LM", 1},
{0x8086, 0x156F, "I219-V", 1},
{0x8086, 0x1570, "I219-LM", 1},
{0x8086, 0x157B, "I219-V-2", 1},
{0x8086, 0x15D3, "I219-V-3", 1},
{0x8086, 0x15D8, "I219-LM-3", 1},
{0x8086, 0x15BD, "I219-V-6", 1},
/* Intel I210/I211 (igb) */
{0x8086, 0x1537, "I210", 3},
{0x8086, 0x1536, "I211-AT", 3},
/* Intel 82575/82576/82580 (igb) */
{0x8086, 0x10A7, "82575EB", 3},
{0x8086, 0x10C9, "82576", 3},
{0x8086, 0x150D, "82580", 3},
{0x8086, 0x1526, "82576-2", 3},
/* Realtek RTL8111/8168/8125 (r8169) — 常见桌面/笔记本有线网卡 */
{0x10EC, 0x8167, "RTL8111/8168B", 2},
{0x10EC, 0x8168, "RTL8111/8168", 2},
{0x10EC, 0x8169, "RTL8169", 2},
{0x10EC, 0x8125, "RTL8125", 2},
{0x10EC, 0x3000, "RTL8169S", 2},
{0x10EC, 0x8136, "RTL8101E", 2},
/* Qualcomm Atheros WiFi (ath9k) */
{0x168C, 0x0023, "AR5416", 4},
{0x168C, 0x0024, "AR5418", 4},
{0x168C, 0x0027, "AR9160", 4},
{0x168C, 0x0029, "AR9280", 4},
{0x168C, 0x002A, "AR9285", 4},
{0x168C, 0x002B, "AR9287", 4},
{0x168C, 0x002D, "AR9287-2", 4},
{0x168C, 0x002E, "AR9287-3", 4},
{0x168C, 0x0030, "AR9300", 4},
{0x168C, 0x0032, "AR9485", 4},
{0x168C, 0x0034, "AR9462", 4},
{0x168C, 0x0036, "AR9485-2", 4},
{0x168C, 0x0037, "AR1111", 4},
/* Broadcom WiFi — 目前无驱动，标注识别 */
{0x14E4, 0x4315, "BCM4312-WiFi", 0xFF},
{0x14E4, 0x4365, "BCM4365-WiFi", 0xFF},
{0x14E4, 0x43A0, "BCM4360-WiFi", 0xFF},
{0x14E4, 0x43C3, "BCM4366-WiFi", 0xFF},
/* Qualcomm WiFi — 无驱动 */
{0x168C, 0x003E, "QCA6174-WiFi", 0xFF},
{0x168C, 0x0042, "QCA6390-WiFi", 0xFF},
/* Intel WiFi — 无驱动 */
{0x8086, 0x24FD, "Intel-8265-WiFi", 0xFF},
{0x8086, 0x2526, "Intel-AX200-WiFi",0xFF},
{0x8086, 0x2725, "Intel-AX210-WiFi",0xFF},
{0x8086, 0x51F0, "Intel-AX211-WiFi",0xFF},
{0x8086, 0x7A70, "Intel-BE200-WiFi",0xFF},
{0, 0, 0, 0} /* 终止符 */
};
static const char *netchip_name(u16 vendor, u16 device) {
for (int i = 0; g_netchips[i].name != 0; i++) {
if (g_netchips[i].vendor == vendor && g_netchips[i].device == device)
return g_netchips[i].name;
}
return 0;
}
static u8 netchip_driver(u16 vendor, u16 device) {
for (int i = 0; g_netchips[i].name != 0; i++) {
if (g_netchips[i].vendor == vendor && g_netchips[i].device == device)
return g_netchips[i].driver_hint;
}
return 0xFF;
}
static const char *pci_class_name(u8 base, u8 sub) {
switch (base) {
case 0x00: return "Legacy";
@@ -190,9 +312,26 @@ static const char *pci_class_name(u8 base, u8 sub) {
(void)sub;
}
/* PCI subclass names for Network class */
static const char *net_subclass_name(u8 sub) {
switch (sub) {
case 0x00: return "Ethernet";
case 0x01: return "TokenRing";
case 0x02: return "FDDI";
case 0x03: return "ATM";
case 0x04: return "ISDN";
case 0x05: return "WorldFIP";
case 0x06: return "PICMG";
case 0x80: return "Other";
default: return "Net-?";
}
}
/* ---------------------------------------------------------------
* Enumeration
* --------------------------------------------------------------- */
static u32 g_device_count;
static void pci_scan_bus(u8 bus) {
for (u8 dev = 0; dev < 32; dev++) {
u32 vid_dev = pci_cfg_read(bus, dev, 0, PCI_VENDOR_ID);
@@ -212,7 +351,9 @@ static void pci_scan_bus(u8 bus) {
u32 cc = pci_cfg_read(bus, dev, func, PCI_CLASS);
u8 class_code = (u8)(cc >> 24);
u8 subclass = (u8)((cc >> 16) & 0xff);
u8 prog_if = (u8)((cc >> 8) & 0xff);
g_device_count++;
g_log->info("[pci]");
log_hex("[pci] bus=", bus);
log_hex("[pci] dev=", dev);
@@ -223,6 +364,39 @@ static void pci_scan_bus(u8 bus) {
g_log->info(pci_class_name(class_code, subclass));
log_hex("[pci] class_hex=", class_code);
log_hex("[pci] subclass=", subclass);
/* 网卡自动识别与驱动匹配提示 */
if (class_code == 0x02) {
const char *chip_name = netchip_name(vendor2, device);
u8 drv = netchip_driver(vendor2, device);
g_log->info("[pci] NetChip");
if (chip_name) {
g_log->info(chip_name);
} else {
g_log->info("unknown");
}
g_log->info("[pci] NetSub");
g_log->info(net_subclass_name(subclass));
switch (drv) {
case 0: g_log->info("[pci] -> driver: e1000"); break;
case 1: g_log->info("[pci] -> driver: e1000 (e1000e compat)"); break;
case 2: g_log->info("[pci] -> driver: r8169 (NOT YET IMPLEMENTED)"); break;
case 3: g_log->info("[pci] -> driver: igb (e1000 compat)"); break;
case 4: g_log->info("[pci] -> driver: ath9k"); break;
case 0xFF: g_log->info("[pci] -> driver: NONE (unsupported)"); break;
default: break;
}
}
/* PCI-PCI 桥检测: 递归扫描下游总线 */
if (class_code == 0x06 && (subclass == 0x04 || subclass == 0x09)) {
u8 sec_bus = (u8)pci_cfg_read(bus, dev, func, PCI_SEC_BUS);
if (sec_bus > bus && sec_bus < 255) {
g_log->info("[pci] bridge -> secondary bus");
log_hex("[pci] sec_bus=", sec_bus);
pci_scan_bus(sec_bus);
}
}
}
}
}
@@ -238,8 +412,10 @@ int driver_init(const struct dkm_kernel_api *api,
if (!api || !api->log) return -1;
g_log = api->log;
g_device_count = 0;
g_log->info("[pci] scanning PCI bus");
pci_scan_bus(0);
log_hex("[pci] total devices=", g_device_count);
g_log->info("[pci] driver ready");
return 0;
}
CODE/DKM/ps2kbd/ps2kbd.c
+5 -36
View File
@@ -5,43 +5,10 @@
#include <stdint.h>
/* DKM ABI types */
#define DKM_DRIVER_MAGIC 0x444B4D31u
#define DKM_ABI_VERSION 1u
#include "../dkm_shared.h"
#include "../dkm_instr.h"
typedef unsigned char u8;
typedef unsigned short u16;
typedef unsigned int u32;
typedef unsigned long long u64;
typedef long long i64;
#define NULL ((void *)0)
struct dkm_log_api {
void (*info)(const char *msg);
void (*warn)(const char *msg);
void (*error)(const char *msg);
void (*panic)(const char *msg);
};
struct dkm_kernel_api {
u32 version; u32 size; u64 feature_bits;
const struct dkm_log_api *log;
const void *mem,*utsm,*irq_api,*pci_api,*dma,*vfs_api,*net,*timer,*drr;
const void *rsdp_address,*fb_address;
u64 fb_width,fb_height,fb_pitch; u16 fb_bpp;
const void *boot_modules_response;
int (*irq_register)(u8 irq, void *handler);
};
struct dkm_driver_handle;
struct dkm_driver_desc {
u32 magic; u16 abi_version; u16 desc_size;
const char *name,*version,*vendor;
u32 driver_class,stage,flags,priority;
const char *const *depends; u32 depends_count;
const char *const *provides; u32 provides_count;
u64 min_kernel_abi,feature_bits,reserved0,reserved1;
};
DKM_STAT_DECL(ps2kbd_irq_count);
/* Driver descriptor */
static const char *const g_depends[] = {"irq"};
@@ -86,6 +53,7 @@ static int kbd_handler(u8 irq) {
(void)irq;
g_last_sc = inb(0x60);
g_has_key = 1;
DKM_STAT_INC(ps2kbd_irq_count);
return 0; /* let kernel send EOI */
}
@@ -95,6 +63,7 @@ int driver_init(const struct dkm_kernel_api *api,
(void)handle;
if (!api||!api->log) return -1;
g_log=api->log;
dkm_instr_init(api);
if (!api->irq_register) {
g_log->warn("[kbd] irq_register not available");
CODE/DKM/virtio_net/virtio_net.c
+709 -42
View File
@@ -1,7 +1,19 @@
/* DKM virtio-net Driver — PCI virtio network discovery
/* DKM virtio-net Driver — virtio network device (legacy/transitional PCI)
* Stage 3 optional network driver, depends on "pci" and "irq", provides "netdev".
* This first version discovers virtio-net devices and logs PCI capabilities;
* it does not negotiate features, create virtqueues, or transmit packets.
*
* 数据路径实现（virtio spec 1.0 legacy interface，transitional device 1AF4:1001）:
* - PCI 探测 → BAR0 legacy I/O 窗口
* - reset → ACKNOWLEDGE → DRIVER → feature negotiation（MAC/STATUS 子集）
* → FEATURES_OK → virtqueue 建立（RXQ0/TXQ1, legacy split-ring 布局）
* → DRIVER_OK
* - RX: 预填 32×2048B buffer 到 RXQ avail；rx_poll 收割 used ring，
* 剥 10B virtio_net_hdr 后把以太网帧交给上层协议栈，buffer 回收重填
* - TX: 8×2048B buffer 池（desc 索引与 buffer 1:1 映射），hdr+帧单描述符，
* QueueNotify kick，与 e1000 一致的同步等待完成（TSC 超时兜底）
* - boot 自测: 经真实 QEMU user-net 后端向 10.0.2.2 DHCP server 发 DISCOVER、
* 收 OFFER，一次跑通证明 TX/RX 全链路（DMA/notify/used ring）
* - IRQ 按 IDT vector（irq_line+0x20）注册做 ISR 统计；PIC 未解屏蔽时
* 自动退化为纯轮询，不依赖中断正确性
*/
#include "../dkm_shared.h"
@@ -10,11 +22,7 @@
#define PCI_CLASS_REG 0x08 /* 32-bit class/subclass/prog_if/revision */
#define PCI_VENDOR_VIRTIO 0x1AF4u
#define VIRTIO_TRANS_DEVICE_MIN 0x1000u
#define VIRTIO_TRANS_DEVICE_MAX 0x103Fu
#define VIRTIO_MODERN_DEVICE_MIN 0x1040u
#define VIRTIO_MODERN_DEVICE_MAX 0x107Fu
#define VIRTIO_NET_DEVICE_ID 1u
/* PCI device ID 约定见 virtio_is_net_device(): transitional net=0x1000, modern net=0x1041 */
#define VIRTIO_PCI_CAP_COMMON_CFG 1u
#define VIRTIO_PCI_CAP_NOTIFY_CFG 2u
@@ -22,6 +30,76 @@
#define VIRTIO_PCI_CAP_DEVICE_CFG 4u
#define VIRTIO_PCI_CAP_PCI_CFG 5u
/* ---- legacy I/O 寄存器偏移（virtio spec 1.0 §4.1.4, BAR0 I/O space） ---- */
#define VP_HOST_FEATURES 0x00u /* u32 RO: device feature bits 0..31 */
#define VP_GUEST_FEATURES 0x04u /* u32 WO: driver 接受的 feature 子集 */
#define VP_QUEUE_PFN 0x08u /* u32 WO: 队列物理地址 >> 12 */
#define VP_QUEUE_NUM 0x0Cu /* u16 RO: 队列容量（2 的幂） */
#define VP_QUEUE_SEL 0x0Eu /* u16 WO: 选择操作的队列 */
#define VP_QUEUE_NOTIFY 0x10u /* u16 WO: kick 指定队列 */
#define VP_STATUS 0x12u /* u8 RW: device status */
#define VP_ISR 0x13u /* u8 RO: ISR，读即清除 */
#define VP_NET_CFG_MAC 0x14u /* 6B RO: MAC（device config 区起始） */
/* ---- device status bits ---- */
#define VS_ACKNOWLEDGE 0x01u
#define VS_DRIVER 0x02u
#define VS_DRIVER_OK 0x04u
#define VS_FEATURES_OK 0x08u
/* ---- virtio-net feature bits（spec §5.1.6），只取最小子集 ---- */
#define VNET_F_MAC (1u << 5) /* device config 提供 MAC */
#define VNET_F_STATUS (1u << 16) /* device config 提供 link status */
/* ---- vring ---- */
#define VRING_DESC_F_WRITE 2u /* descriptor 由 device 写（RX） */
#define VNET_HDR_SIZE 10u /* 未协商 MRG_RXBUF → virtio_net_hdr 为 10 字节 */
#define RX_BUF_COUNT 32u /* RX 预填 buffer 数（不必填满整个队列） */
#define TX_BUF_COUNT 8u /* TX buffer 池大小 */
#define VNET_BUF_SIZE 2048u /* 10B hdr + 最大 1518B 以太网帧 */
/* split-ring 结构（legacy，x86 上字段为 guest 原生小端序） */
struct vring_desc {
u64 addr;
u32 len;
u16 flags;
u16 next;
};
struct vring_used_elem {
u32 id;
u32 len;
};
struct vring_avail {
u16 flags;
u16 idx;
u16 ring[];
};
struct vring_used {
u16 flags;
u16 idx;
struct vring_used_elem ring[];
};
/* 单个 virtqueue 的运行时视图。
* legacy 布局（spec §2.4.2）:
* base+0 : descriptor table（16B × size）
* base+16*size : avail ring（4 + 2×size + 2B used_event）
* align4K(16*size + 6 + 2*size): used ring（4 + 8×size + 2B avail_event）
* 整段必须物理连续且 4KiB 对齐（QueuePFN 只接受页帧号）。 */
struct virtq {
u16 qsel; /* queue select 索引（0=RX, 1=TX） */
u16 size; /* device 报告的队列容量 */
u64 phys; /* 队列内存物理基址（页对齐） */
struct vring_desc *desc;
struct vring_avail *avail;
struct vring_used *used;
u16 last_used_idx; /* driver 侧 used ring 收割游标 */
};
static const char *const g_depends[] = { "pci", "irq" };
static const char *const g_provides[] = { "netdev" };
@@ -31,7 +109,7 @@ const struct dkm_driver_desc driver_desc = {
.abi_version = DKM_ABI_VERSION,
.desc_size = sizeof(struct dkm_driver_desc),
.name = "virtio_net",
.version = "0.1.0",
.version = "0.2.0",
.vendor = "Deshab",
.driver_class = 9, /* DKM_CLASS_NET */
.stage = 3,
@@ -49,6 +127,48 @@ const struct dkm_driver_desc driver_desc = {
static const struct dkm_log_api *g_log;
/* ---- 全局设备状态 ---- */
static u16 g_io_base; /* legacy I/O BAR 基址，0=未初始化 */
static struct virtq g_rxq;
static struct virtq g_txq;
static u8 *g_rx_buf[RX_BUF_COUNT];
static u64 g_rx_buf_phys[RX_BUF_COUNT];
static u8 *g_tx_buf[TX_BUF_COUNT];
static u64 g_tx_buf_phys[TX_BUF_COUNT];
static u8 g_tx_free[TX_BUF_COUNT]; /* 1=空闲可提交 */
static int g_ready; /* 数据路径就绪标志 */
static u8 g_mac[6];
/* ---- 统计计数器（串口可观测） ---- */
static u64 g_stat_tx_ok;
static u64 g_stat_tx_err;
static u64 g_stat_tx_timeout;
static u64 g_stat_rx_ok;
static u64 g_stat_rx_err;
static u64 g_stat_rx_overflow;
static u64 g_stat_irq_count;
/* ---- 自测缓冲区（静态 bss，避免内核栈压力） ---- */
static u8 g_st_frame[360]; /* DHCP DISCOVER 帧（342B） */
static u8 g_st_buf[2048]; /* RX 收割暂存 */
/* ---- 16-bit I/O port 访问（dkm_shared.h 只提供 8/32 位） ---- */
static __inline__ void vn_outw(u16 port, u16 value) {
__asm__ volatile ("outw %0, %1" :: "a"(value), "Nd"(port));
}
static __inline__ u16 vn_inw(u16 port) {
u16 value;
__asm__ volatile ("inw %1, %0" : "=a"(value) : "Nd"(port));
return value;
}
/* device DMA 内存屏障：描述符/ring 写入必须先于 idx 更新对设备可见。
* x86 store-store 有序，compiler fence + mfence 双保险（控制路径，开销可忽略）。 */
static __inline__ void vn_fence(void) {
__asm__ volatile("mfence" ::: "memory");
}
static u32 pci_read(u8 bus, u8 dev, u8 func, u8 reg) {
return dkm_pci_read(bus, dev, func, reg);
}
@@ -61,6 +181,17 @@ static u8 pci_read8(u8 bus, u8 dev, u8 func, u8 reg) {
return dkm_pci_read8(bus, dev, func, reg);
}
static void copy_bytes(void *dst, const void *src, u32 len) {
u8 *d = (u8 *)dst;
const u8 *s = (const u8 *)src;
for (u32 i = 0; i < len; i++) d[i] = s[i];
}
static void zero_bytes(void *dst, u32 len) {
u8 *d = (u8 *)dst;
for (u32 i = 0; i < len; i++) d[i] = 0;
}
static void log_hex(const char *prefix, u64 value) {
static const char hex[] = "0123456789abcdef";
char buf[19];
@@ -75,14 +206,51 @@ static void log_hex(const char *prefix, u64 value) {
g_log->info(buf);
}
static u16 virtio_subsystem_id(u16 device_id) {
if (device_id >= VIRTIO_TRANS_DEVICE_MIN && device_id <= VIRTIO_TRANS_DEVICE_MAX) {
return (u16)(device_id - VIRTIO_TRANS_DEVICE_MIN);
static u32 dec_u32(u32 v, char *out) {
char tmp[10];
u32 n = 0;
if (v == 0) { out[0] = '0'; return 1; }
while (v && n < 10) { tmp[n++] = (char)('0' + (v % 10)); v /= 10; }
for (u32 i = 0; i < n; i++) out[i] = tmp[n - 1 - i];
return n;
}
/* 打印 IPv4 地址。ip 为主机序（高字节 = 第一个 octet，如 0x0A00020F = 10.0.2.15）。 */
static void log_ipv4(const char *prefix, u32 ip) {
char buf[24];
u32 p = 0;
for (u32 i = 0; i < 4; i++) {
u8 octet = (u8)(ip >> ((3 - i) * 8));
p += dec_u32(octet, buf + p);
if (i < 3) buf[p++] = '.';
}
if (device_id >= VIRTIO_MODERN_DEVICE_MIN && device_id <= VIRTIO_MODERN_DEVICE_MAX) {
return (u16)(device_id - VIRTIO_MODERN_DEVICE_MIN);
buf[p] = 0;
g_log->info(prefix);
g_log->info(buf);
}
static void log_mac(const char *prefix, const u8 mac[6]) {
static const char hex[] = "0123456789abcdef";
char buf[18];
u32 p = 0;
for (u32 i = 0; i < 6; i++) {
buf[p++] = hex[(mac[i] >> 4) & 0xf];
buf[p++] = hex[mac[i] & 0xf];
if (i < 5) buf[p++] = ':';
}
return 0xffff;
buf[p] = 0;
g_log->info(prefix);
g_log->info(buf);
}
/* virtio-net PCI device ID 判定。
* QEMU 编号约定（virtio 1.0 spec §4.1.2.1 + QEMU hw/virtio/virtio-pci.c）:
* - transitional/legacy: 0x1000=net, 0x1001=blk, 0x1002=balloon, ...
* （历史 table，不是 0x1000+virtio_id；virtio device id 由 PCI Subsystem ID 携带）
* - modern-only: 0x1040+virtio_id → net = 0x1041
* class code (0x02=Network) 作为第二判据，与 virtio-blk(0x1001/Storage) 区分。 */
static int virtio_is_net_device(u16 device_id) {
return (device_id == 0x1000u || device_id == 0x1041u) ? 1 : 0;
}
static int virtio_net_find(u8 *out_bus, u8 *out_dev, u8 *out_func) {
@@ -99,10 +267,9 @@ static int virtio_net_find(u8 *out_bus, u8 *out_dev, u8 *out_func) {
u16 device = (u16)(vd2 >> 16);
if (vendor != PCI_VENDOR_VIRTIO) continue;
u16 virtio_id = virtio_subsystem_id(device);
u32 class_reg = pci_read(bus, dev, func, PCI_CLASS_REG);
u8 class_code = (u8)(class_reg >> 24);
if (virtio_id == VIRTIO_NET_DEVICE_ID && class_code == 0x02) {
if (virtio_is_net_device(device) && class_code == 0x02) {
*out_bus = bus;
*out_dev = dev;
*out_func = func;
@@ -178,28 +345,455 @@ static void log_virtio_caps(u8 bus, u8 dev, u8 func) {
}
}
/* ---- tx/rx_poll stub: 安全占位, 不实际收发, 防止 netdev 调用 NULL ---- */
static int virtio_net_tx(void *ctx, const void *packet, u32 length) {
(void)ctx;
(void)packet;
/* 仅记录日志, 避免每次发包刷屏: 仅记录长度 */
static u32 s_tx_log_guard = 0;
if (s_tx_log_guard < 4) {
g_log->info("[virtio_net] tx stub: packet dropped (virtqueues not enabled)");
log_hex("[virtio_net] tx stub len=", length);
s_tx_log_guard++;
/* ================= legacy device 初始化序列 ================= */
/* device status 寄存器读写（8 位） */
static void vdev_set_status(u8 status) {
dkm_outb((u16)(g_io_base + VP_STATUS), status);
}
static u8 vdev_get_status(void) {
return dkm_inb((u16)(g_io_base + VP_STATUS));
}
/* reset → ACKNOWLEDGE → DRIVER → feature 协商 → FEATURES_OK。
* 返回 0 成功；失败返回负数（调用方回退 stub 注册）。 */
static int vdev_negotiate(void) {
/* 1. reset: 写 0 并等待设备读回 0（spec §4.1.4.3 要求轮询确认） */
vdev_set_status(0);
u64 deadline = dkm_rdtsc() + dkm_tsc_per_ms * 100;
while (vdev_get_status() != 0) {
if (dkm_rdtsc() > deadline) {
g_log->error("[virtio_net] device reset timeout");
return -1;
}
__asm__ volatile("pause");
}
/* 2/3. ACKNOWLEDGE → DRIVER（status 位按序累积写入） */
vdev_set_status(VS_ACKNOWLEDGE);
vdev_set_status(VS_ACKNOWLEDGE | VS_DRIVER);
/* 4. feature negotiation: 只取 MAC + STATUS 子集。
* 不接受 MRG_RXBUF/CTRL_VQ/CSUM/GSO 等复杂特性 →
* virtio_net_hdr 固定 10 字节、无控制队列、无卸载，数据路径最简。 */
u32 dev_feat = dkm_inl((u16)(g_io_base + VP_HOST_FEATURES));
log_hex("[virtio_net] device features=", dev_feat);
u32 subset = dev_feat & (VNET_F_MAC | VNET_F_STATUS);
dkm_outl((u16)(g_io_base + VP_GUEST_FEATURES), subset);
log_hex("[virtio_net] guest features=", subset);
/* 5. FEATURES_OK 并回读确认（spec §3.1.1）。
* 纯 legacy（pre-1.0）设备没有该位概念；QEMU transitional 实现 1.0 语义会置位。
* 未置位时按 legacy 兼容策略 warn 后继续（与 Linux legacy 驱动一致）。 */
vdev_set_status(VS_ACKNOWLEDGE | VS_DRIVER | VS_FEATURES_OK);
u8 st = vdev_get_status();
log_hex("[virtio_net] status after FEATURES_OK=", st);
if (!(st & VS_FEATURES_OK)) {
g_log->warn("[virtio_net] FEATURES_OK not echoed; continuing as pre-1.0 legacy device");
} else {
g_log->info("[virtio_net] FEATURES_OK confirmed");
}
return 0;
}
/* QueuePFN = 物理地址 >> 12（legacy 队列地址寄存器语义） */
static void vn_outl_pfn(const struct virtq *q) {
dkm_outl((u16)(g_io_base + VP_QUEUE_PFN), (u32)(q->phys >> 12));
}
/* 建立单个 virtqueue：读容量 → 计算 legacy 布局 → 分配连续页 → 写 QueuePFN。 */
static int vq_setup(const struct dkm_dma_api *dma, struct virtq *q, u16 qsel) {
q->qsel = qsel;
q->last_used_idx = 0;
vn_outw((u16)(g_io_base + VP_QUEUE_SEL), qsel);
q->size = vn_inw((u16)(g_io_base + VP_QUEUE_NUM));
if (q->size == 0) {
g_log->error("[virtio_net] queue size is 0");
return -1;
}
/* legacy 布局（spec §2.4.2）:
* desc @ 0，avail @ 16*size，used @ 4KiB 对齐边界，整段物理连续。 */
u64 avail_off = 16ULL * q->size;
u64 used_off = (avail_off + 6ULL + 2ULL * q->size + 4095ULL) & ~4095ULL;
u64 total = used_off + 6ULL + 8ULL * q->size;
u64 pages = (total + 4095ULL) / 4096ULL;
struct dkm_dma_buffer buf;
/* 低 4G + 页对齐：QueuePFN 只接受 phys>>12，alloc_pages 返回已清零页 */
if (dma->alloc_pages(pages, 4096, 0x100000000ULL, &buf) != 0) {
g_log->error("[virtio_net] queue memory alloc failed");
return -2;
}
q->phys = buf.phys;
q->desc = (struct vring_desc *)buf.virt;
q->avail = (struct vring_avail *)((u8 *)buf.virt + avail_off);
q->used = (struct vring_used *)((u8 *)buf.virt + used_off);
vn_outl_pfn(q);
return 0;
}
/* kick 队列：写 queue index 到 QueueNotify */
static void vq_notify(const struct virtq *q) {
vn_outw((u16)(g_io_base + VP_QUEUE_NOTIFY), q->qsel);
}
/* 把描述符挂到 avail ring 并推进 idx。
* 顺序约束：desc 字段必须先写好（调用方责任），ring 写入 → fence → idx 推进。 */
static void vq_push_avail(struct virtq *q, u16 desc_idx) {
u16 slot = (u16)(q->avail->idx % q->size);
q->avail->ring[slot] = desc_idx;
vn_fence();
q->avail->idx = (u16)(q->avail->idx + 1u);
vn_fence();
}
/* 从 used ring 取一个完成项。返回 0=取到，1=空。 */
static int vq_pop_used(struct virtq *q, u16 *out_id, u32 *out_len) {
vn_fence();
if (q->used->idx == q->last_used_idx) return 1;
struct vring_used_elem *e = &q->used->ring[q->last_used_idx % q->size];
*out_id = (u16)e->id;
*out_len = e->len;
vn_fence();
q->last_used_idx = (u16)(q->last_used_idx + 1u);
return 0;
}
/* ================= RX 路径 ================= */
/* 回收 RX buffer：重置描述符并重新挂回 avail ring，保持 RX 水位。 */
static void rx_requeue(u16 id) {
g_rxq.desc[id].addr = g_rx_buf_phys[id];
g_rxq.desc[id].len = VNET_BUF_SIZE;
g_rxq.desc[id].flags = VRING_DESC_F_WRITE;
g_rxq.desc[id].next = 0;
vq_push_avail(&g_rxq, id);
vq_notify(&g_rxq);
}
/* 预填全部 RX buffer（单描述符覆盖 hdr+帧，device 可写）。 */
static int rx_prefill(const struct dkm_dma_api *dma) {
for (u32 i = 0; i < RX_BUF_COUNT; i++) {
struct dkm_dma_buffer b;
if (dma->alloc_pages(1, 4096, 0x100000000ULL, &b) != 0) {
g_log->error("[virtio_net] rx buffer alloc failed");
log_hex("[virtio_net] filled=", i);
return -1;
}
g_rx_buf[i] = (u8 *)b.virt;
g_rx_buf_phys[i] = b.phys;
g_rxq.desc[i].addr = b.phys;
g_rxq.desc[i].len = VNET_BUF_SIZE;
g_rxq.desc[i].flags = VRING_DESC_F_WRITE;
g_rxq.desc[i].next = 0;
g_rxq.avail->ring[i] = (u16)i;
}
vn_fence();
g_rxq.avail->idx = (u16)RX_BUF_COUNT;
vn_fence();
log_hex("[virtio_net] rx buffers prefilled=", RX_BUF_COUNT);
return 0;
}
/* netdev rx_poll 回调（契约与 e1000 一致）:
* 返回 0 且 *out_length>0 = 收到一帧；1 = 无数据；负数 = 错误。 */
static int virtio_net_rx_poll(void *ctx, void *buffer, u32 capacity, u32 *out_length) {
(void)ctx;
if (out_length) *out_length = 0;
if (!g_ready || !buffer || !out_length) return -1;
u16 id;
u32 total;
if (vq_pop_used(&g_rxq, &id, &total) != 0) return 1; /* 无完成项 */
/* 防御：id 越界或总长小于 hdr → 丢帧（id 无效时无法回收，只计数） */
if (id >= RX_BUF_COUNT) {
g_stat_rx_err++;
return -3;
}
if (total < VNET_HDR_SIZE) {
g_stat_rx_err++;
rx_requeue(id);
return -3;
}
u32 frame_len = total - VNET_HDR_SIZE; /* 剥掉 virtio_net_hdr */
if (frame_len > capacity) {
g_stat_rx_overflow++;
rx_requeue(id);
return -2;
}
copy_bytes(buffer, g_rx_buf[id] + VNET_HDR_SIZE, frame_len);
*out_length = frame_len;
rx_requeue(id);
g_stat_rx_ok++;
return 0;
}
/* ================= TX 路径 ================= */
/* 收割 TX used ring，把完成的 buffer 标回空闲。 */
static void tx_reclaim(void) {
u16 id;
u32 len;
while (vq_pop_used(&g_txq, &id, &len) == 0) {
(void)len; /* TX 的 used.len 无语义，仅 id 用于回收 */
if (id < TX_BUF_COUNT) g_tx_free[id] = 1;
}
}
static int tx_buffers_alloc(const struct dkm_dma_api *dma) {
for (u32 i = 0; i < TX_BUF_COUNT; i++) {
struct dkm_dma_buffer b;
if (dma->alloc_pages(1, 4096, 0x100000000ULL, &b) != 0) {
g_log->error("[virtio_net] tx buffer alloc failed");
return -1;
}
g_tx_buf[i] = (u8 *)b.virt;
g_tx_buf_phys[i] = b.phys;
g_tx_free[i] = 1;
}
return 0;
}
/* netdev tx 回调：hdr(10B 全零，无卸载) + 帧单描述符提交，kick 后同步等待完成。
* 与 e1000 行为一致：TSC 1 秒超时兜底，避免上层协议栈无限阻塞。 */
static int virtio_net_tx(void *ctx, const void *packet, u32 length) {
(void)ctx;
if (!g_ready || !packet || length == 0 || length + VNET_HDR_SIZE > VNET_BUF_SIZE) {
g_stat_tx_err++;
return -1;
}
tx_reclaim();
int slot = -1;
for (u32 i = 0; i < TX_BUF_COUNT; i++) {
if (g_tx_free[i]) { slot = (int)i; break; }
}
if (slot < 0) {
g_stat_tx_err++;
g_log->warn("[virtio_net] tx ring full");
return -2;
}
u8 *buf = g_tx_buf[slot];
zero_bytes(buf, VNET_HDR_SIZE); /* virtio_net_hdr: flags/gso 全 0 */
copy_bytes(buf + VNET_HDR_SIZE, packet, length);
/* desc 索引与 buffer 1:1 映射，回收时 used.id 即 buffer 索引 */
g_txq.desc[slot].addr = g_tx_buf_phys[slot];
g_txq.desc[slot].len = length + VNET_HDR_SIZE;
g_txq.desc[slot].flags = 0; /* device 只读 */
g_txq.desc[slot].next = 0;
g_tx_free[slot] = 0;
vq_push_avail(&g_txq, (u16)slot);
vq_notify(&g_txq);
u64 deadline = dkm_rdtsc() + dkm_tsc_per_ms * 1000;
while (dkm_rdtsc() < deadline) {
tx_reclaim();
if (g_tx_free[slot]) {
g_stat_tx_ok++;
return 0;
}
__asm__ volatile("pause");
}
g_stat_tx_timeout++;
g_log->warn("[virtio_net] tx timeout");
log_hex("[virtio_net] txq used idx=", g_txq.used->idx);
log_hex("[virtio_net] txq last_used=", g_txq.last_used_idx);
return -3;
}
/* ================= IRQ（辅助统计，数据路径不依赖） ================= */
static int virtio_net_irq(u8 irq) {
(void)irq;
if (!g_io_base) return 0;
/* ISR 读即清除；bit0=queue used buffer 通知，bit1=config change */
u8 isr = dkm_inb((u16)(g_io_base + VP_ISR));
if (isr & 0x1u) g_stat_irq_count++;
return 0; /* 不 suppress EOI，由 IDT 发 PIC EOI */
}
/* ================= boot 自测：DHCP DISCOVER/OFFER ================= */
#define ST_XID 0x4B1D3A5Fu
#define ST_FRAME_LEN 342u /* 14 eth + 20 ip + 8 udp + 300 bootp */
/* 构造 DHCP DISCOVER（全手工大端字段，避免 packed struct 字节序歧义）。
* BOOTP 载荷补齐到 300 字节（RFC 1542 最小值，slirp DHCP server 容忍度最高）。 */
static void st_build_discover(const u8 mac[6]) {
u8 *f = g_st_frame;
zero_bytes(f, ST_FRAME_LEN);
/* Ethernet: 广播 DISCOVER */
for (u32 i = 0; i < 6; i++) f[i] = 0xff;
for (u32 i = 0; i < 6; i++) f[6 + i] = mac[i];
f[12] = 0x08; f[13] = 0x00; /* IPv4 */
/* IPv4 @14 */
u8 *ip = f + 14;
ip[0] = 0x45; /* v4, ihl=5 */
ip[1] = 0x00;
ip[2] = 0x01; ip[3] = 0x48; /* total len = 328 */
ip[4] = 0x00; ip[5] = 0x00; /* id */
ip[6] = 0x00; ip[7] = 0x00; /* flags/frag */
ip[8] = 64; /* ttl */
ip[9] = 17; /* UDP */
ip[10] = 0x00; ip[11] = 0x00; /* cksum 占位 */
/* src 0.0.0.0 @12..15 保持 0 */
ip[16] = 0xff; ip[17] = 0xff; ip[18] = 0xff; ip[19] = 0xff;
/* IP header checksum（标准 1's complement，大端语义直接按字节对累加） */
u32 sum = 0;
for (u32 i = 0; i < 20; i += 2) sum += ((u32)ip[i] << 8) | ip[i + 1];
while (sum >> 16) sum = (sum & 0xffffu) + (sum >> 16);
u16 ck = (u16)(~sum & 0xffffu);
ip[10] = (u8)(ck >> 8); ip[11] = (u8)ck;
/* UDP @34: 68 → 67，校验和置 0（IPv4 下合法） */
u8 *udp = f + 34;
udp[0] = 0x00; udp[1] = 68;
udp[2] = 0x00; udp[3] = 67;
udp[4] = 0x01; udp[5] = 0x34; /* len = 308 */
udp[6] = 0x00; udp[7] = 0x00;
/* BOOTP @42（固定 236B + magic 4B + options，pad 到 300B） */
u8 *bp = f + 42;
bp[0] = 1; /* op = BOOTREQUEST */
bp[1] = 1; /* htype = Ethernet */
bp[2] = 6; /* hlen */
bp[3] = 0; /* hops */
bp[4] = (u8)(ST_XID >> 24);
bp[5] = (u8)(ST_XID >> 16);
bp[6] = (u8)(ST_XID >> 8);
bp[7] = (u8)ST_XID;
/* secs @8..9 = 0 */
bp[10] = 0x80; bp[11] = 0x00; /* flags = broadcast */
/* ciaddr/yiaddr/siaddr/giaddr @12..27 = 0 */
for (u32 i = 0; i < 6; i++) bp[28 + i] = mac[i]; /* chaddr（16B，后 10B 为 0） */
/* sname @44..107, file @108..235 = 0 */
bp[236] = 0x63; bp[237] = 0x82; bp[238] = 0x53; bp[239] = 0x63; /* magic cookie */
u8 *opt = bp + 240;
opt[0] = 53; opt[1] = 1; opt[2] = 1; /* DHCP msg type = DISCOVER */
opt[3] = 55; opt[4] = 4; /* param request list */
opt[5] = 1; opt[6] = 3; opt[7] = 6; opt[8] = 15; /* subnet/router/dns/domain */
opt[9] = 255; /* end */
}
/* 解析帧是否为匹配 XID 的 DHCP OFFER。
* 返回 2=OFFER（*out_yiaddr 有效，主机序），5=ACK，0=无关帧。 */
static int st_parse_reply(const u8 *f, u32 len, u32 *out_yiaddr) {
if (len < 14 + 20 + 8 + 240) return 0;
if (f[12] != 0x08 || f[13] != 0x00) return 0; /* 非 IPv4 */
u32 ihl = (u32)(f[14] & 0x0f) * 4u;
if (ihl < 20) return 0;
if (f[14 + 9] != 17) return 0; /* 非 UDP */
u32 udp = 14 + ihl;
if (len < udp + 8 + 240) return 0;
u16 dport = (u16)(((u16)f[udp + 2] << 8) | f[udp + 3]);
if (dport != 68) return 0; /* 非 DHCP 回包 */
u32 bp = udp + 8;
if (f[bp] != 2) return 0; /* 非 BOOTREPLY */
u32 xid = ((u32)f[bp + 4] << 24) | ((u32)f[bp + 5] << 16) |
((u32)f[bp + 6] << 8) | f[bp + 7];
if (xid != ST_XID) return 0; /* XID 不匹配 */
if (f[bp + 236] != 0x63 || f[bp + 237] != 0x82 ||
f[bp + 238] != 0x53 || f[bp + 239] != 0x63) return 0;
u32 yiaddr = ((u32)f[bp + 16] << 24) | ((u32)f[bp + 17] << 16) |
((u32)f[bp + 18] << 8) | f[bp + 19];
/* options 区扫描 msg type（53） */
u32 i = bp + 240;
while (i < len) {
u8 o = f[i];
if (o == 255) break;
if (o == 0) { i++; continue; }
if (i + 1 >= len) break;
u8 olen = f[i + 1];
if (o == 53 && olen == 1 && i + 2 < len) {
u8 mtype = f[i + 2];
if (mtype == 2 || mtype == 5) {
*out_yiaddr = yiaddr;
return mtype;
}
return 0;
}
i += 2u + olen;
}
return 0;
}
/* boot 自测：经真实网络后端验证 TX（desc+notify+used 回收）与
* RX（avail 预填 + used 收割 + hdr 剥离）全链路。
* 任何失败只记日志，绝不阻塞/崩溃启动流程。 */
static void virtio_net_selftest(void) {
if (!g_ready) return;
g_log->info("[virtio_net] selftest begin: DHCP DISCOVER -> expect OFFER from backend");
st_build_discover(g_mac);
int txrc = virtio_net_tx(0, g_st_frame, ST_FRAME_LEN);
log_hex("[virtio_net] selftest tx rc=", (u64)(i64)txrc);
if (txrc != 0) {
g_log->warn("[virtio_net] selftest: TX path FAILED");
return;
}
g_log->info("[virtio_net] selftest: TX path ok (descriptor consumed by device)");
u64 deadline = dkm_rdtsc() + dkm_tsc_per_ms * 2000;
u32 frames = 0;
while (dkm_rdtsc() < deadline) {
u32 flen = 0;
int rc = virtio_net_rx_poll(0, g_st_buf, sizeof(g_st_buf), &flen);
if (rc == 0 && flen > 0) {
frames++;
u32 ethertype = ((u32)g_st_buf[12] << 8) | g_st_buf[13];
log_hex("[virtio_net] selftest rx frame len=", flen);
log_hex("[virtio_net] ethertype=", ethertype);
u32 yiaddr = 0;
int t = st_parse_reply(g_st_buf, flen, &yiaddr);
if (t == 2) {
log_ipv4("[virtio_net] selftest: DHCP OFFER yiaddr=", yiaddr);
g_log->info("[virtio_net] selftest PASS: RX path ok (frame from real backend)");
return;
}
}
__asm__ volatile("pause");
}
g_log->warn("[virtio_net] selftest: no DHCP OFFER within 2000ms");
log_hex("[virtio_net] selftest rx frames seen=", frames);
}
/* ================= stub（初始化失败时的安全占位，与历史行为一致） ================= */
static int virtio_net_tx_stub(void *ctx, const void *packet, u32 length) {
(void)ctx;
(void)packet;
log_hex("[virtio_net] tx stub: packet dropped, len=", length);
return 0;
}
static int virtio_net_rx_poll_stub(void *ctx, void *buffer, u32 capacity, u32 *out_length) {
(void)ctx;
(void)buffer;
(void)capacity;
if (out_length) *out_length = 0;
return 0; /* 无数据, virtqueues 未启用 */
return 0;
}
/* ================= driver 入口 ================= */
__attribute__((visibility("default")))
int driver_init(const struct dkm_kernel_api *api,
struct dkm_driver_handle *handle) {
@@ -230,19 +824,11 @@ int driver_init(const struct dkm_kernel_api *api,
u32 vd = pci_read(bus, dev, func, PCI_VENDOR_ID);
u16 vendor = (u16)(vd & 0xffff);
u16 device = (u16)(vd >> 16);
u16 virtio_id = virtio_subsystem_id(device);
u32 class_reg = pci_read(bus, dev, func, PCI_CLASS_REG);
u8 revision = (u8)(class_reg & 0xff);
u8 prog_if = (u8)((class_reg >> 8) & 0xff);
u8 subclass = (u8)((class_reg >> 16) & 0xff);
u8 class_code = (u8)((class_reg >> 24) & 0xff);
log_hex("[virtio_net] vendor=", vendor);
log_hex("[virtio_net] device=", device);
log_hex("[virtio_net] virtio_id=", virtio_id);
log_hex("[virtio_net] class=", class_code);
log_hex("[virtio_net] subclass=", subclass);
log_hex("[virtio_net] prog_if=", prog_if);
log_hex("[virtio_net] revision=", revision);
u32 command = pci_read(bus, dev, func, PCI_COMMAND) & 0xffff;
@@ -256,21 +842,96 @@ int driver_init(const struct dkm_kernel_api *api,
log_bars(bus, dev, func);
log_virtio_caps(bus, dev, func);
/* ---- legacy I/O BAR 检查：transitional 设备 BAR0 必须是 I/O space ---- */
u32 bar0 = pci_read(bus, dev, func, PCI_BAR0);
int datapath_ok = 0;
if (!(bar0 & 1u)) {
g_log->warn("[virtio_net] BAR0 is not I/O space (modern-only device?); legacy path unavailable");
} else if (!api->dma || !api->dma->alloc_pages) {
g_log->warn("[virtio_net] dma API unavailable");
} else {
g_io_base = (u16)(bar0 & 0xfffcU);
log_hex("[virtio_net] legacy io_base=", g_io_base);
if (vdev_negotiate() != 0) {
g_log->warn("[virtio_net] feature negotiation failed");
} else if (vq_setup(api->dma, &g_rxq, 0) != 0) {
g_log->warn("[virtio_net] RXQ setup failed");
} else if (vq_setup(api->dma, &g_txq, 1) != 0) {
g_log->warn("[virtio_net] TXQ setup failed");
} else if (rx_prefill(api->dma) != 0) {
g_log->warn("[virtio_net] RX prefill failed");
} else if (tx_buffers_alloc(api->dma) != 0) {
g_log->warn("[virtio_net] TX buffer alloc failed");
} else {
log_hex("[virtio_net] rxq size=", g_rxq.size);
log_hex("[virtio_net] rxq phys=", g_rxq.phys);
log_hex("[virtio_net] txq size=", g_txq.size);
log_hex("[virtio_net] txq phys=", g_txq.phys);
/* MAC: device config @ io_base+0x14（协商 MAC feature 后有效） */
for (u32 i = 0; i < 6; i++) {
g_mac[i] = dkm_inb((u16)(g_io_base + VP_NET_CFG_MAC + i));
}
u8 mac_sum = 0;
for (u32 i = 0; i < 6; i++) mac_sum |= g_mac[i];
if (mac_sum == 0 || (g_mac[0] & 1u)) {
/* 全 0 或组播位异常 → fallback */
g_mac[0] = 0x52; g_mac[1] = 0x54; g_mac[2] = 0x00;
g_mac[3] = 0x12; g_mac[4] = 0x34; g_mac[5] = 0x57;
g_log->warn("[virtio_net] invalid device MAC, using fallback");
}
log_mac("[virtio_net] MAC=", g_mac);
/* DRIVER_OK：设备开始处理队列；随后 kick RXQ 让设备吃掉预填 buffer */
vdev_set_status(VS_ACKNOWLEDGE | VS_DRIVER | VS_FEATURES_OK | VS_DRIVER_OK);
vq_notify(&g_rxq);
g_ready = 1;
datapath_ok = 1;
g_log->info("[virtio_net] DRIVER_OK set; virtqueues live");
}
}
/* ---- IRQ 注册（辅助统计；数据路径为纯轮询，不依赖中断） ----
* 注意: kernel irq_register 按 IDT vector 索引（PIC IRQn → vector 0x20+n），
* 传裸 IRQ 号会落到异常向量槽位永不触发（e1000 当前如此）。
* PIC 未解屏蔽该线时自动退化为纯轮询。 */
if (datapath_ok && api->irq_register && irq_line > 0 && irq_line < 16) {
api->irq_register((u8)(irq_line + 0x20u), (void *)(uintptr_t)virtio_net_irq);
g_log->info("[virtio_net] IRQ handler registered (vector = irq + 0x20)");
} else {
g_log->info("[virtio_net] IRQ not registered (polling mode)");
}
/* ---- 注册 netdev ---- */
if (api->net && api->net->register_device) {
struct dkm_net_device_desc netdev;
zero_bytes(&netdev, sizeof(netdev));
netdev.name = "virtio-net";
for (int i = 0; i < 6; i++) netdev.mac[i] = 0;
netdev.flags = DKM_NET_F_LINK_UP;
for (u32 i = 0; i < 6; i++) netdev.mac[i] = g_mac[i];
netdev.ctx = 0;
netdev.tx = virtio_net_tx; /* stub: 安全占位, 不 NULL */
netdev.rx_poll = virtio_net_rx_poll;
if (datapath_ok) {
netdev.flags = DKM_NET_F_LINK_UP | DKM_NET_F_TX_READY | DKM_NET_F_RX_READY;
netdev.tx = virtio_net_tx;
netdev.rx_poll = virtio_net_rx_poll;
} else {
/* 安全占位：flags 仅 LINK_UP，netman 不会选它跑 DHCP（与历史行为一致） */
netdev.flags = DKM_NET_F_LINK_UP;
netdev.tx = virtio_net_tx_stub;
netdev.rx_poll = virtio_net_rx_poll_stub;
}
int net_index = api->net->register_device(&netdev);
log_hex("[virtio_net] netdev register rc=", (u64)(i64)net_index);
log_hex("[virtio_net] netdev registered, index=", (u64)(i64)net_index);
} else {
g_log->warn("[virtio_net] net API unavailable; netdev not registered");
}
g_log->info("[virtio_net] discovery only; virtqueues disabled");
/* ---- boot 自测（证明 TX/RX 全链路，失败仅记日志） ---- */
virtio_net_selftest();
log_hex("[virtio_net] stat tx_ok=", g_stat_tx_ok);
log_hex("[virtio_net] stat rx_ok=", g_stat_rx_ok);
g_log->info("[virtio_net] driver ready");
return 0;
}
@@ -278,5 +939,11 @@ int driver_init(const struct dkm_kernel_api *api,
__attribute__((visibility("default")))
int driver_exit(struct dkm_driver_handle *handle) {
(void)handle;
/* reset 设备：停止一切 DMA 与队列活动 */
if (g_io_base) {
vdev_set_status(0);
}
g_ready = 0;
g_io_base = 0;
return 0;
}
CODE/DKM/xhci/xhci.c
+1783
View File
@@ -0,0 +1,1783 @@
/* DKM xHCI Driver — USB xHCI host controller + Mass Storage Class (BOT/SCSI)
*
* Stage 1 optional storage driver, depends on "pci" and "irq", provides "block".
*
* Architecture:
* 1. PCI discovery: class=0x0C/03/30 (Serial Bus / USB / xHCI)
* 2. MMIO mapping: 64-bit BAR0 via mm_map_mmio or HHDM fallback
* 3. Controller init: BIOS handoff, HC reset, parse capabilities
* 4. Ring setup: Command Ring, Event Ring, ERST, DCBAA, Scratchpad
* 5. Port scan: detect connected devices, port reset
* 6. USB enumeration: Enable Slot, Address Device, GET_DESCRIPTOR
* 7. MSC protocol: BOT (Bulk-Only Transport) + SCSI commands
* 8. Block provider: register usb0 via kernel_api.block
*
* Synchronous polling model (no IRQ/MSI in first version).
* All hardware waits use TSC deadline — no infinite loops.
*/
#include "../dkm_shared.h"
#include "../dkm_instr.h"
DKM_STAT_DECL(xhci_pci_found);
DKM_STAT_DECL(xhci_port_reset_ok);
DKM_STAT_DECL(xhci_msc_found);
DKM_STAT_DECL(xhci_block_reads);
DKM_STAT_DECL(xhci_block_writes);
static const char *const g_depends[] = { "pci", "irq" };
static const char *const g_provides[] = { "block" };
__attribute__((visibility("default"), used))
const struct dkm_driver_desc driver_desc = {
.magic = DKM_DRIVER_MAGIC,
.abi_version = DKM_ABI_VERSION,
.desc_size = sizeof(struct dkm_driver_desc),
.name = "xhci",
.version = "0.1.0",
.vendor = "Deshab",
.driver_class = 6, /* DKM_CLASS_STORAGE */
.stage = 1,
.flags = 0,
.priority = 0,
.depends = g_depends,
.depends_count = 2,
.provides = g_provides,
.provides_count = 1,
.min_kernel_abi = 1,
.feature_bits = 0,
.reserved0 = 0,
.reserved1 = 0
};
/* ================================================================
* Constants — PCI, xHCI registers, TRB types, USB
* ================================================================ */
#define XHCI_CLASS_SERIAL 0x0C
#define XHCI_SUBCLASS_USB 0x03
#define XHCI_PROGIF_XHCI 0x30
/* Capability Registers (MMIO + 0x00) */
#define XHCI_CAP_HCSPARAMS1 0x00
#define XHCI_CAP_HCSPARAMS2 0x04
#define XHCI_CAP_HCSPARAMS3 0x08
#define XHCI_CAP_HCCPARAMS1 0x0C
#define XHCI_CAP_DBOFF 0x14
#define XHCI_CAP_RTSOFF 0x18
/* Operational Registers (MMIO + cap_length) */
#define XHCI_OP_USBCMD 0x00
#define XHCI_OP_USBSTS 0x04
#define XHCI_OP_PAGESIZE 0x08
#define XHCI_OP_DNCTRL 0x14
#define XHCI_OP_CRCR_LO 0x18
#define XHCI_OP_CRCR_HI 0x1C
#define XHCI_OP_DCBAAP_LO 0x30
#define XHCI_OP_DCBAAP_HI 0x34
#define XHCI_OP_CONFIG 0x38
/* Port Registers (MMIO + 0x400 + port * 0x10) */
#define XHCI_PORT_BASE_OFF 0x400
#define XHCI_PORT_STRIDE 0x10
#define XHCI_PORT_SC 0x00
/* Runtime Registers (MMIO + rtsoff) */
#define XHCI_RT_MFINDEX 0x00
#define XHCI_RT_IR0_IMAN 0x20
#define XHCI_RT_IR0_IMOD 0x24
#define XHCI_RT_IR0_ERSTSZ 0x28
#define XHCI_RT_IR0_ERSTBA_LO 0x30
#define XHCI_RT_IR0_ERSTBA_HI 0x34
#define XHCI_RT_IR0_ERDP_LO 0x38
#define XHCI_RT_IR0_ERDP_HI 0x3C
/* USBCMD bits */
#define USBCMD_RS (1u << 0)
#define USBCMD_RST (1u << 1)
#define USBCMD_INTE (1u << 2)
/* USBSTS bits */
#define USBSTS_HCH (1u << 0)
#define USBSTS_EINT (1u << 3)
#define USBSTS_CNR (1u << 11)
/* PORTSC bits */
#define PORTSC_CCS (1u << 0)
#define PORTSC_PED (1u << 1)
#define PORTSC_OCA (1u << 3)
#define PORTSC_PR (1u << 4)
#define PORTSC_PLS_SHIFT 5
#define PORTSC_PLS_MASK 0xF
#define PORTSC_SPEED_SHIFT 17
#define PORTSC_SPEED_MASK 0x7
/* TRB types */
#define TRB_TYPE_NORMAL 0x01
#define TRB_TYPE_SETUP_STAGE 0x02
#define TRB_TYPE_DATA_STAGE 0x03
#define TRB_TYPE_STATUS_STAGE 0x04
#define TRB_TYPE_LINK 0x06
#define TRB_TYPE_ENABLE_SLOT 0x09
#define TRB_TYPE_DISABLE_SLOT 0x0A
#define TRB_TYPE_ADDRESS_DEV 0x0B
#define TRB_TYPE_CONFIGURE_EP 0x0C
#define TRB_TYPE_NOOP 0x17
/* Event TRB types — same namespace as command/transfer TRB types.
* Per xHCI spec §6.4: these are the TRB Type field values in the
* Event TRB control dword [15:10]. */
#define EVT_TYPE_TRANSFER 0x01 /* Transfer Event */
#define EVT_TYPE_CMD_COMPLETE 0x02 /* Command Completion Event */
#define EVT_TYPE_PORT_CHANGE 0x21 /* Port Status Change Event */
/* TRB control field helpers */
#define TRB_TYPE_SHIFT 10
#define TRB_TYPE_MASK 0x3F
#define TRB_IOC (1u << 5) /* Interrupt On Completion */
#define TRB_CH (1u << 6) /* Chain bit */
#define TRB_ENT (1u << 7) /* Evaluate Next TRB (for Link) */
#define TRB_ISP (1u << 8) /* Interrupt on Short Packet */
#define TRB_CYCLE (1u << 0)
#define TRB_TC (1u << 1) /* Toggle Cycle (for Link) */
/* Setup Stage TRB direction */
#define SETUP_DIR_OUT 0
#define SETUP_DIR_IN 1
/* USB speeds */
#define USB_SPEED_FULL 1
#define USB_SPEED_LOW 2
#define USB_SPEED_HIGH 3
#define USB_SPEED_SUPER 4
/* Endpoint types for EP Context */
#define EP_TYPE_CTRL_OUT 0
#define EP_TYPE_CTRL_IN 4
#define EP_TYPE_BULK_OUT 2
#define EP_TYPE_BULK_IN 6
/* Slot states */
#define SLOT_STATE_DISABLED 0
#define SLOT_STATE_ENABLED 1
#define SLOT_STATE_ADDRESSED 2
#define SLOT_STATE_CONFIGURED 3
/* Ring sizes */
#define CMD_RING_SIZE 256
#define EVT_RING_SIZE 256
#define XFER_RING_SIZE 256
/* xHCI MMIO mapping size (64 KB covers most controllers) */
#define XHCI_MAP_SIZE 0x10000
/* BOT (Bulk-Only Transport) signatures */
#define BOT_CBW_SIG 0x43425355u /* "USBC" */
#define BOT_CSW_SIG 0x53425355u /* "USBS" */
/* SCSI opcodes */
#define SCSI_TEST_UNIT_READY 0x00
#define SCSI_INQUIRY 0x12
#define SCSI_READ_CAPACITY10 0x25
#define SCSI_READ10 0x28
#define SCSI_WRITE10 0x2A
/* ================================================================
* Data structures
* ================================================================ */
typedef struct {
u64 parameter; /* DW0-DW1 */
u32 status; /* DW2 */
u32 control; /* DW3 */
} xhci_trb;
/* TRB Ring */
typedef struct {
struct dkm_dma_buffer dma;
u32 size; /* TRB count */
u32 enqueue; /* producer index */
u32 ccs; /* producer Cycle State */
} xhci_ring;
/* ERST entry */
typedef struct {
u64 seg_addr;
u32 seg_size;
u32 rsvd;
} xhci_erst_entry;
/* MSC device state */
typedef struct {
u8 slot_id;
u8 speed;
u8 bulk_out_ep; /* EP number for Bulk OUT */
u8 bulk_in_ep; /* EP number for Bulk IN */
u16 bulk_out_mps; /* Max Packet Size */
u16 bulk_in_mps; /* Max Packet Size */
u32 cbw_tag; /* BOT tag counter */
u64 sector_count;
u32 sector_size;
int ready;
} xhci_msc_dev;
/* ================================================================
* Global state
* ================================================================ */
static const struct dkm_kernel_api *g_api;
static const struct dkm_log_api *g_log;
static volatile u8 *g_mmio; /* MMIO base virtual address */
static u32 g_cap_length; /* Capability register space length */
static u32 g_doorbell_off; /* Doorbell register offset */
static u32 g_runtime_off; /* Runtime register space offset */
static u32 g_max_slots;
static u32 g_max_ports;
static u32 g_max_intrs;
static u32 g_ctx_size; /* 32 or 64 bytes */
static u32 g_page_size; /* controller page size in bytes */
static u32 g_spb_count; /* scratchpad buffer count */
static u32 g_port_base; /* absolute MMIO offset of port register set (cap_length + 0x400) */
static u32 g_ppc; /* Per-Port Power Control (HCCPARAMS1 bit 3) */
static xhci_ring g_cmd_ring;
static xhci_ring g_evt_ring;
static u32 g_evt_ccs; /* consumer cycle state for event ring */
static struct dkm_dma_buffer g_erst; /* ERST DMA buffer */
static struct dkm_dma_buffer g_dcbaa; /* DCBAA DMA buffer */
static struct dkm_dma_buffer g_sp_bufs; /* Scratchpad buffer array */
/* Scratchpad individual pages — max 32 scratchpads for safety */
static struct dkm_dma_buffer g_sp_pages[32];
/* Per-device DMA buffers */
static struct dkm_dma_buffer g_input_ctx; /* Input Context */
static struct dkm_dma_buffer g_dev_ctx; /* Device Context (output) */
static xhci_ring g_ep0_ring; /* EP0 control transfer ring */
static xhci_ring g_bulk_out_ring;
static xhci_ring g_bulk_in_ring;
static struct dkm_dma_buffer g_xfer_buf; /* Data transfer bounce buffer */
static struct dkm_dma_buffer g_csw_buf; /* CSW receive buffer */
static xhci_msc_dev g_msc;
/* PCI device location */
static u8 g_pci_bus, g_pci_dev, g_pci_func;
/* ================================================================
* Utility functions
* ================================================================ */
static void log_hex(const char *prefix, u64 value) {
static const char hex[] = "0123456789abcdef";
char buf[19];
u32 pos = 0;
buf[pos++] = '0';
buf[pos++] = 'x';
for (int i = 15; i >= 0; i--)
buf[pos++] = hex[(value >> (i * 4)) & 0xf];
buf[pos] = 0;
g_log->info(prefix);
g_log->info(buf);
}
static void xhci_zero(void *ptr, u32 len) {
u8 *p = (u8 *)ptr;
for (u32 i = 0; i < len; i++) p[i] = 0;
}
static void xhci_memcpy(void *dst, const void *src, u32 len) {
u8 *d = (u8 *)dst;
const u8 *s = (const u8 *)src;
for (u32 i = 0; i < len; i++) d[i] = s[i];
}
/* MMIO read/write */
static u32 mmio_read32(u32 off) {
return *(volatile u32 *)(void *)(g_mmio + off);
}
static void mmio_write32(u32 off, u32 value) {
*(volatile u32 *)(void *)(g_mmio + off) = value;
}
static u64 mmio_read64(u32 off) {
u32 lo = mmio_read32(off);
u32 hi = mmio_read32(off + 4);
return ((u64)hi << 32) | lo;
}
static void mmio_write64(u32 off, u64 value) {
mmio_write32(off, (u32)(value & 0xffffffffu));
mmio_write32(off + 4, (u32)(value >> 32));
}
/* Memory barrier (compiler only — x86 TSO guarantees HW ordering) */
static __inline__ void xhci_mb(void) {
__asm__ volatile("" ::: "memory");
}
/* ================================================================
* Phase 1: PCI discovery + MMIO mapping
* ================================================================ */
static int xhci_find(u8 *out_bus, u8 *out_dev, u8 *out_func) {
for (u16 bus = 0; bus < 256; bus++) {
for (u8 dev = 0; dev < 32; dev++) {
u32 vd = dkm_pci_read((u8)bus, dev, 0, PCI_VENDOR_ID);
if ((vd & 0xffff) == 0xffff) continue;
u8 header = (u8)(dkm_pci_read((u8)bus, dev, 0, PCI_HEADER) >> 16);
u8 func_count = (header & 0x80) ? 8 : 1;
for (u8 func = 0; func < func_count; func++) {
u32 vd2 = dkm_pci_read((u8)bus, dev, func, PCI_VENDOR_ID);
if ((vd2 & 0xffff) == 0xffff) continue;
u32 class_reg = dkm_pci_read((u8)bus, dev, func, 0x08);
u8 prog_if = (u8)((class_reg >> 8) & 0xff);
u8 subclass = (u8)((class_reg >> 16) & 0xff);
u8 class_code = (u8)((class_reg >> 24) & 0xff);
if (class_code == XHCI_CLASS_SERIAL &&
subclass == XHCI_SUBCLASS_USB &&
prog_if == XHCI_PROGIF_XHCI) {
*out_bus = (u8)bus;
*out_dev = dev;
*out_func = func;
return 0;
}
}
}
}
return -1;
}
static volatile u8 *xhci_map_bar(const struct dkm_kernel_api *api, u64 bar_phys) {
u64 bar_virt = api->hhdm_offset + bar_phys;
/* Prefer mm_map_mmio independent window */
if (api->mm_map_mmio) {
void *mapped = api->mm_map_mmio(bar_phys, XHCI_MAP_SIZE);
if (mapped) {
g_log->info("[xhci] BAR mapped via mm_map_mmio");
return (volatile u8 *)mapped;
}
g_log->warn("[xhci] mm_map_mmio failed; trying HHDM fallback");
}
/* Check if HHDM covers this BAR */
if (api->mmio && api->mmio->is_mapped) {
int level = api->mmio->is_mapped(bar_virt);
if (level > 0) {
g_log->info("[xhci] HHDM covers BAR; direct access");
return (volatile u8 *)(uintptr_t)bar_virt;
}
/* Map via page tables */
if (api->mmio->map_mmio) {
int rc = api->mmio->map_mmio(bar_phys, XHCI_MAP_SIZE);
if (rc == 0 && api->mmio->is_mapped(bar_virt) > 0) {
g_log->info("[xhci] BAR mapped via page tables");
return (volatile u8 *)(uintptr_t)bar_virt;
}
}
}
/* Low BAR fallback */
if (bar_phys < 0x100000000ULL) {
g_log->warn("[xhci] assuming HHDM covers low BAR");
return (volatile u8 *)(uintptr_t)bar_virt;
}
g_log->error("[xhci] BAR MMIO unavailable");
return (volatile u8 *)0;
}
/* ================================================================
* Phase 1: BIOS Handoff via Extended Capabilities
* ================================================================ */
static void xhci_bios_handoff(void) {
u32 hcc1 = mmio_read32(XHCI_CAP_HCCPARAMS1);
u32 ext_ptr = (hcc1 >> 16) & 0xFFFF;
if (!ext_ptr) return;
/* Walk extended capabilities (offsets in 32-bit words from MMIO base) */
u32 off = ext_ptr;
for (int i = 0; i < 16 && off != 0; i++) {
u32 dw0 = mmio_read32(off * 4);
u8 id = (u8)(dw0 & 0xFF);
u8 next = (u8)((dw0 >> 8) & 0xFF);
if (id == 1) {
/* USB Legacy Support Capability */
u32 legsup = mmio_read32(off * 4 + 4);
log_hex("[xhci] USBLEGSUP=", legsup);
if (legsup & 0x0000FFFFu) {
/* BIOS owns controller — request ownership */
mmio_write32(off * 4 + 4, legsup | (1u << 16));
u64 deadline = dkm_rdtsc() + dkm_tsc_per_ms * 1000;
while (dkm_rdtsc() < deadline) {
u32 cur = mmio_read32(off * 4 + 4);
if (!(cur & 0x0000FFFFu)) {
g_log->info("[xhci] BIOS handoff complete");
/* Clear SMI triggers */
mmio_write32(off * 4 + 8, 0);
break;
}
__asm__ volatile("pause");
}
}
}
off = next ? (off + next) : 0;
}
}
/* ================================================================
* Phase 1: Controller reset and init
* ================================================================ */
static int xhci_controller_reset(void) {
u32 usbcmd = mmio_read32(g_cap_length + XHCI_OP_USBCMD);
u32 usbsts = mmio_read32(g_cap_length + XHCI_OP_USBSTS);
/* If controller is running, halt it first */
if (!(usbsts & USBSTS_HCH)) {
mmio_write32(g_cap_length + XHCI_OP_USBCMD, usbcmd & ~USBCMD_RS);
u64 deadline = dkm_rdtsc() + dkm_tsc_per_ms * 1000;
while (dkm_rdtsc() < deadline) {
if (mmio_read32(g_cap_length + XHCI_OP_USBSTS) & USBSTS_HCH) break;
__asm__ volatile("pause");
}
}
/* Wait for CNR to clear */
{
u64 deadline = dkm_rdtsc() + dkm_tsc_per_ms * 1000;
while (dkm_rdtsc() < deadline) {
if (!(mmio_read32(g_cap_length + XHCI_OP_USBSTS) & USBSTS_CNR)) break;
__asm__ volatile("pause");
}
}
/* Assert HC reset */
usbcmd = mmio_read32(g_cap_length + XHCI_OP_USBCMD);
mmio_write32(g_cap_length + XHCI_OP_USBCMD, usbcmd | USBCMD_RST);
/* Wait for reset to complete (RST bit clears) */
{
u64 deadline = dkm_rdtsc() + dkm_tsc_per_ms * 2000;
while (dkm_rdtsc() < deadline) {
usbcmd = mmio_read32(g_cap_length + XHCI_OP_USBCMD);
if (!(usbcmd & USBCMD_RST)) {
g_log->info("[xhci] controller reset complete");
return 0;
}
__asm__ volatile("pause");
}
}
g_log->error("[xhci] controller reset timeout");
return -1;
}
static int xhci_parse_caps(void) {
/* Read CAPLENGTH (low byte of MMIO+0) */
g_cap_length = mmio_read32(0) & 0xFF;
u32 hcs1 = mmio_read32(XHCI_CAP_HCSPARAMS1);
u32 hcs2 = mmio_read32(XHCI_CAP_HCSPARAMS2);
u32 hcc1 = mmio_read32(XHCI_CAP_HCCPARAMS1);
g_max_slots = hcs1 & 0xFF;
g_max_intrs = (hcs1 >> 8) & 0x7FF;
g_max_ports = (hcs1 >> 24) & 0xFF;
/* Context size: CSZ bit4 of HCCPARAMS1 */
g_ctx_size = (hcc1 & (1u << 4)) ? 64 : 32;
/* Per-Port Power Control: PPC bit3 of HCCPARAMS1 */
g_ppc = (hcc1 >> 3) & 1;
/* Scratchpad buffer count from HCSPARAMS2 */
g_spb_count = ((hcs2 >> 21) & 0x1F) | ((hcs2 >> 27) & 0x1F);
/*
* Port Register Set offset: absolute from MMIO base.
* xHCI spec: "Port Register Sets are located at offset 0x400
* from the beginning of the Operational Register Space."
* Operational Register Space starts at offset CAPLENGTH.
* Therefore absolute port offset = CAPLENGTH + 0x400.
* Verified against QEMU source (XHCI_REGS_OFFSET_PORT =
* XHCI_REGS_OFFSET_OPER + XHCI_REGS_LENGTH_OPER) and Linux
* kernel (op_regs + PORTSC_OFFSET where op_regs = base + cap_length).
*/
g_port_base = g_cap_length + XHCI_PORT_BASE_OFF;
/* Doorbell and Runtime offsets — full 32-bit, clear reserved low bits */
g_doorbell_off = mmio_read32(XHCI_CAP_DBOFF) & 0xFFFFFFF0u;
g_runtime_off = mmio_read32(XHCI_CAP_RTSOFF) & 0xFFFFFFE0u;
/* Page size */
u32 ps_reg = mmio_read32(g_cap_length + XHCI_OP_PAGESIZE);
g_page_size = 1u << ((ps_reg & 0xF) + 12);
log_hex("[xhci] CAPLEN=", g_cap_length);
log_hex("[xhci] MaxSlots=", g_max_slots);
log_hex("[xhci] MaxPorts=", g_max_ports);
log_hex("[xhci] MaxIntrs=", g_max_intrs);
log_hex("[xhci] ContextSize=", g_ctx_size);
log_hex("[xhci] PPC=", g_ppc);
log_hex("[xhci] PortBaseOff=", g_port_base);
log_hex("[xhci] ScratchpadBufs=", g_spb_count);
log_hex("[xhci] DBOFF=", g_doorbell_off);
log_hex("[xhci] RTSOFF=", g_runtime_off);
log_hex("[xhci] PageSize=", g_page_size);
if (g_max_slots == 0 || g_max_ports == 0) {
g_log->error("[xhci] invalid capability parameters");
return -1;
}
if (g_max_intrs == 0) {
g_log->warn("[xhci] MaxIntrs=0 (no interrupt register sets); polling mode only");
}
return 0;
}
/* ================================================================
* Phase 2: TRB Ring management
* ================================================================ */
static int xhci_ring_init(xhci_ring *ring, u32 size) {
if (!g_api->dma) return -1;
/* Allocate one page (must be 4K aligned for DMA) */
if (g_api->dma->alloc_pages(1, 4096, 0x100000000ULL, &ring->dma) != 0)
return -2;
xhci_zero(ring->dma.virt, ring->dma.size);
ring->size = size;
ring->enqueue = 0;
ring->ccs = 1; /* Producer Cycle State starts at 1 */
/* Append Link TRB at end of ring */
xhci_trb *trbs = (xhci_trb *)ring->dma.virt;
u32 link_idx = size - 1;
trbs[link_idx].parameter = ring->dma.phys;
trbs[link_idx].status = 0;
trbs[link_idx].control = (TRB_TYPE_LINK << TRB_TYPE_SHIFT) | TRB_TC | TRB_CYCLE;
return 0;
}
/* Enqueue a TRB onto a ring and return the enqueue index before advance */
static u32 xhci_ring_enqueue(xhci_ring *ring, u64 param, u32 status, u32 control) {
xhci_trb *trbs = (xhci_trb *)ring->dma.virt;
u32 idx = ring->enqueue;
/* Set cycle bit in control */
control &= ~TRB_CYCLE;
if (ring->ccs) control |= TRB_CYCLE;
trbs[idx].parameter = param;
trbs[idx].status = status;
trbs[idx].control = control;
/* Advance enqueue */
ring->enqueue = (idx + 1) % (ring->size - 1); /* -1 to skip Link TRB */
/* If we wrapped, toggle CCS */
if (idx + 1 >= ring->size - 1)
ring->ccs ^= 1;
return idx;
}
/* Ring a doorbell: slot_id=0 for command, otherwise endpoint doorbell */
static void xhci_ring_doorbell(u32 slot_id, u32 target) {
mmio_write32(g_doorbell_off + slot_id * 0x20, target);
}
/* ================================================================
* Phase 2: Event Ring polling
* ================================================================ */
/* Poll event ring for a specific TRB type with TSC timeout.
* Returns 0 on success, fills out_param/out_status/out_control.
* Returns -1 on timeout, -2 on error completion code. */
static int xhci_poll_event(u32 expected_type, u64 timeout_ms,
u64 *out_param, u32 *out_status, u32 *out_control) {
xhci_trb *trbs = (xhci_trb *)g_evt_ring.dma.virt;
u64 deadline = dkm_rdtsc() + dkm_tsc_per_ms * timeout_ms;
for (;;) {
xhci_trb *evt = &trbs[g_evt_ring.enqueue];
u32 ctrl = evt->control;
u8 cycle = (u8)(ctrl & TRB_CYCLE);
/* Check if this TRB is owned by us (consumer) */
if (cycle == (u8)g_evt_ccs) {
u8 type = (u8)((ctrl >> TRB_TYPE_SHIFT) & TRB_TYPE_MASK);
/* Process this event */
if (type == expected_type) {
if (out_param) *out_param = evt->parameter;
if (out_status) *out_status = evt->status;
if (out_control)*out_control= evt->control;
/* Advance dequeue */
g_evt_ring.enqueue = (g_evt_ring.enqueue + 1) % (g_evt_ring.size - 1);
if (g_evt_ring.enqueue == 0) g_evt_ccs ^= 1;
/* Update ERDP */
u64 erdp = g_evt_ring.dma.phys + (u64)g_evt_ring.enqueue * sizeof(xhci_trb);
mmio_write64(g_runtime_off + XHCI_RT_IR0_ERDP_LO, erdp | g_evt_ccs);
/* Check completion code */
u32 cc = (evt->status >> 24) & 0xFF;
if (cc != 1) { /* 1 = Success */
if (cc != 0) {
log_hex("[xhci] event completion code=", cc);
return -2;
}
}
return 0;
}
/* Unexpected event type — handle or skip */
if (type == EVT_TYPE_PORT_CHANGE) {
/* Port Status Change Event: clear PORTSC change bits */
u32 port_id = (u32)((evt->parameter >> 24) & 0xFF);
if (port_id > 0 && port_id <= g_max_ports) {
u32 port_off = g_port_base + (port_id - 1) * XHCI_PORT_STRIDE + XHCI_PORT_SC;
/* Read PORTSC and write back to clear change bits (W1C) */
u32 portsc = mmio_read32(port_off);
mmio_write32(port_off, portsc);
log_hex("[xhci] port change event, port=", port_id);
}
} else {
log_hex("[xhci] unexpected event type=", type);
}
g_evt_ring.enqueue = (g_evt_ring.enqueue + 1) % (g_evt_ring.size - 1);
if (g_evt_ring.enqueue == 0) g_evt_ccs ^= 1;
u64 erdp2 = g_evt_ring.dma.phys + (u64)g_evt_ring.enqueue * sizeof(xhci_trb);
mmio_write64(g_runtime_off + XHCI_RT_IR0_ERDP_LO, erdp2 | g_evt_ccs);
continue;
}
if (dkm_rdtsc() > deadline) {
g_log->warn("[xhci] event poll timeout");
return -1;
}
__asm__ volatile("pause");
}
}
/* ================================================================
* Phase 2: Command submission
* ================================================================ */
static int xhci_cmd_submit(u64 param, u32 status, u32 control,
u64 timeout_ms,
u64 *out_param, u32 *out_status) {
/* Clear Event Ring interrupt pending */
mmio_write32(g_runtime_off + XHCI_RT_IR0_IMAN,
mmio_read32(g_runtime_off + XHCI_RT_IR0_IMAN) | 2u);
/* Enqueue command TRB */
xhci_ring_enqueue(&g_cmd_ring, param, status, control);
xhci_mb();
/* Debug: verify CRCR and command ring state */
log_hex("[xhci] CRCR=", mmio_read64(g_cap_length + XHCI_OP_CRCR_LO));
log_hex("[xhci] cmd ring enqueue=", g_cmd_ring.enqueue);
log_hex("[xhci] cmd ring ccs=", g_cmd_ring.ccs);
xhci_ring_doorbell(0, 0); /* Command ring doorbell */
/* Debug: check USBSTS after doorbell */
log_hex("[xhci] USBSTS after db=", mmio_read32(g_cap_length + XHCI_OP_USBSTS));
/* Poll for Command Completion Event */
/* Debug: dump event ring head entry */
{
xhci_trb *evts = (xhci_trb *)g_evt_ring.dma.virt;
log_hex("[xhci] evt ring head=", g_evt_ring.enqueue);
log_hex("[xhci] evt[0] ctrl=", evts[g_evt_ring.enqueue].control);
}
int rc = xhci_poll_event(EVT_TYPE_CMD_COMPLETE, timeout_ms,
out_param, out_status, 0);
/* Clear EINT */
mmio_write32(g_cap_length + XHCI_OP_USBSTS,
mmio_read32(g_cap_length + XHCI_OP_USBSTS) | USBSTS_EINT);
return rc;
}
/* ================================================================
* Phase 2: Setup controller rings + DCBAA + Scratchpad
* ================================================================ */
static int xhci_setup_rings(void) {
if (!g_api->dma) {
g_log->warn("[xhci] DMA API unavailable");
return -1;
}
/* Command Ring */
if (xhci_ring_init(&g_cmd_ring, CMD_RING_SIZE) != 0) {
g_log->error("[xhci] cmd ring alloc failed");
return -2;
}
log_hex("[xhci] cmd ring phys=", g_cmd_ring.dma.phys);
/* Event Ring */
if (xhci_ring_init(&g_evt_ring, EVT_RING_SIZE) != 0) {
g_log->error("[xhci] evt ring alloc failed");
return -3;
}
g_evt_ccs = 1; /* Consumer Cycle State starts at 1 */
log_hex("[xhci] evt ring phys=", g_evt_ring.dma.phys);
/* ERST (Event Ring Segment Table) */
if (g_api->dma->alloc_pages(1, 4096, 0x100000000ULL, &g_erst) != 0) {
g_log->error("[xhci] ERST alloc failed");
return -4;
}
xhci_erst_entry *erst = (xhci_erst_entry *)g_erst.virt;
xhci_zero(erst, sizeof(xhci_erst_entry));
erst->seg_addr = g_evt_ring.dma.phys;
erst->seg_size = EVT_RING_SIZE;
/* DCBAA (Device Context Base Address Array) */
u32 dcbaa_size = (g_max_slots + 1) * 8;
u32 dcbaa_pages = (dcbaa_size + 4095) / 4096;
if (dcbaa_pages == 0) dcbaa_pages = 1;
if (g_api->dma->alloc_pages(dcbaa_pages, 4096, 0x100000000ULL, &g_dcbaa) != 0) {
g_log->error("[xhci] DCBAA alloc failed");
return -5;
}
xhci_zero(g_dcbaa.virt, g_dcbaa.size);
log_hex("[xhci] DCBAA phys=", g_dcbaa.phys);
/* Scratchpad Buffer Array (if needed) */
if (g_spb_count > 0) {
u32 sp_arr_size = g_spb_count * 8;
u32 sp_arr_pages = (sp_arr_size + 4095) / 4096;
if (sp_arr_pages == 0) sp_arr_pages = 1;
if (g_api->dma->alloc_pages(sp_arr_pages, 4096, 0x100000000ULL, &g_sp_bufs) != 0) {
g_log->error("[xhci] scratchpad array alloc failed");
return -6;
}
xhci_zero(g_sp_bufs.virt, g_sp_bufs.size);
/* Allocate individual scratchpad buffer pages */
u32 sp_count = g_spb_count;
if (sp_count > 32) sp_count = 32; /* safety cap */
for (u32 i = 0; i < sp_count; i++) {
if (g_api->dma->alloc_pages(1, 4096, 0x100000000ULL, &g_sp_pages[i]) != 0) {
g_log->error("[xhci] scratchpad page alloc failed");
return -7;
}
xhci_zero(g_sp_pages[i].virt, g_sp_pages[i].size);
/* Fill scratchpad buffer array with physical addresses */
u64 *sp_arr = (u64 *)g_sp_bufs.virt;
sp_arr[i] = g_sp_pages[i].phys;
}
/* DCBAA slot 0 points to scratchpad buffer array */
u64 *dcbaa_entries = (u64 *)g_dcbaa.virt;
dcbaa_entries[0] = g_sp_bufs.phys;
log_hex("[xhci] SPB array phys=", g_sp_bufs.phys);
}
return 0;
}
static int xhci_controller_start(void) {
u32 cap_off = g_cap_length;
/* Configure Command Ring */
u64 crcr = g_cmd_ring.dma.phys | (u64)g_cmd_ring.ccs;
mmio_write64(cap_off + XHCI_OP_CRCR_LO, crcr);
/* Configure DCBAAP */
mmio_write64(cap_off + XHCI_OP_DCBAAP_LO, g_dcbaa.phys);
/* Configure MaxSlotsEn */
mmio_write32(cap_off + XHCI_OP_CONFIG, g_max_slots);
/* Configure Event Ring */
mmio_write32(g_runtime_off + XHCI_RT_IR0_ERSTSZ, 1);
mmio_write64(g_runtime_off + XHCI_RT_IR0_ERSTBA_LO, g_erst.phys);
u64 erdp = g_evt_ring.dma.phys | (u64)g_evt_ccs;
mmio_write64(g_runtime_off + XHCI_RT_IR0_ERDP_LO, erdp);
/* Enable interrupt (IMAN.IE=1) */
mmio_write32(g_runtime_off + XHCI_RT_IR0_IMAN,
mmio_read32(g_runtime_off + XHCI_RT_IR0_IMAN) | (1u << 1));
/* Enable controller interrupts + start controller */
u32 usbcmd = mmio_read32(cap_off + XHCI_OP_USBCMD);
usbcmd |= USBCMD_INTE | USBCMD_RS;
mmio_write32(cap_off + XHCI_OP_USBCMD, usbcmd);
/* Wait for HCH to clear (controller running) */
u64 deadline = dkm_rdtsc() + dkm_tsc_per_ms * 2000;
while (dkm_rdtsc() < deadline) {
u32 usbsts = mmio_read32(cap_off + XHCI_OP_USBSTS);
if (!(usbsts & USBSTS_HCH)) {
g_log->info("[xhci] controller started");
return 0;
}
__asm__ volatile("pause");
}
g_log->error("[xhci] controller start timeout");
return -1;
}
/* ================================================================
* Phase 3: Port detection and reset
* ================================================================ */
static int xhci_reset_port(u32 port_idx) {
u32 port_off = g_port_base + port_idx * XHCI_PORT_STRIDE + XHCI_PORT_SC;
u32 portsc = mmio_read32(port_off);
/* Check if device is connected */
if (!(portsc & PORTSC_CCS)) return -1;
/* Already enabled? */
if (portsc & PORTSC_PED) return 0;
/* Clear any change bits (W1C), then assert port reset */
mmio_write32(port_off, portsc | PORTSC_PR);
/* Wait for PED (Port Enabled) with 500ms timeout */
u64 deadline = dkm_rdtsc() + dkm_tsc_per_ms * 500;
while (dkm_rdtsc() < deadline) {
portsc = mmio_read32(port_off);
if (portsc & PORTSC_PED) {
/* Clear port change bits (W1C: write 1 to clear) */
mmio_write32(port_off, portsc);
DKM_STAT_INC(xhci_port_reset_ok);
/* Drain any Port Status Change Events from the event ring.
* Port reset generates a Port Status Change Event that must
* be consumed before submitting new commands, otherwise the
* event ring gets congested and command completion events
* may not be delivered. */
dkm_delay_ms(10); /* Allow controller to post the event */
xhci_trb *evts = (xhci_trb *)g_evt_ring.dma.virt;
for (int drain = 0; drain < 16; drain++) {
xhci_trb *evt = &evts[g_evt_ring.enqueue];
u32 ctrl = evt->control;
u8 cycle = (u8)(ctrl & TRB_CYCLE);
if (cycle != (u8)g_evt_ccs) break; /* No more events */
u8 type = (u8)((ctrl >> TRB_TYPE_SHIFT) & TRB_TYPE_MASK);
if (type == EVT_TYPE_PORT_CHANGE) {
u32 port_id = (u32)((evt->parameter >> 24) & 0xFF);
log_hex("[xhci] drained port change event, port=", port_id);
}
/* Advance dequeue */
g_evt_ring.enqueue = (g_evt_ring.enqueue + 1) % (g_evt_ring.size - 1);
if (g_evt_ring.enqueue == 0) g_evt_ccs ^= 1;
u64 erdp = g_evt_ring.dma.phys + (u64)g_evt_ring.enqueue * sizeof(xhci_trb);
mmio_write64(g_runtime_off + XHCI_RT_IR0_ERDP_LO, erdp | g_evt_ccs);
}
return 0;
}
/* Check if device disconnected during reset */
if (!(portsc & PORTSC_CCS)) return -2;
__asm__ volatile("pause");
}
g_log->warn("[xhci] port reset timeout");
return -3;
}
static u8 xhci_get_port_speed(u32 port_idx) {
u32 port_off = g_port_base + port_idx * XHCI_PORT_STRIDE + XHCI_PORT_SC;
u32 portsc = mmio_read32(port_off);
return (u8)((portsc >> PORTSC_SPEED_SHIFT) & PORTSC_SPEED_MASK);
}
/* ================================================================
* Phase 3: Enable Slot
* ================================================================ */
static int xhci_enable_slot(u8 *out_slot_id) {
/* Submit Enable Slot Command TRB */
u32 control = (TRB_TYPE_ENABLE_SLOT << TRB_TYPE_SHIFT);
u64 out_param = 0;
u32 out_status = 0;
int rc = xhci_cmd_submit(0, 0, control, 5000, &out_param, &out_status);
if (rc != 0) {
g_log->error("[xhci] Enable Slot failed");
return rc;
}
/* Slot ID is in the upper bits of the completion event parameter */
*out_slot_id = (u8)((out_param >> 24) & 0xFF);
log_hex("[xhci] slot_id=", *out_slot_id);
return 0;
}
/* ================================================================
* Phase 3: Address Device
* ================================================================ */
static int xhci_address_device(u8 slot_id, int bsr) {
/* Input Context physical address */
u64 input_ctx_phys = g_input_ctx.phys;
u32 control = (TRB_TYPE_ADDRESS_DEV << TRB_TYPE_SHIFT);
if (bsr) control |= (1u << 9); /* BSR (Block Set Address) */
/* Slot ID goes in control bits [31:24] */
control |= ((u32)slot_id << 24);
u64 out_param = 0;
u32 out_status = 0;
int rc = xhci_cmd_submit(input_ctx_phys, 0, control, 5000, &out_param, &out_status);
if (rc != 0) {
g_log->error("[xhci] Address Device failed");
return rc;
}
return 0;
}
/* ================================================================
* Phase 3: Configure Endpoint
* ================================================================ */
static int xhci_configure_endpoint(u8 slot_id) {
u64 input_ctx_phys = g_input_ctx.phys;
u32 control = (TRB_TYPE_CONFIGURE_EP << TRB_TYPE_SHIFT) | ((u32)slot_id << 24);
u64 out_param = 0;
u32 out_status = 0;
int rc = xhci_cmd_submit(input_ctx_phys, 0, control, 5000, &out_param, &out_status);
if (rc != 0) {
g_log->error("[xhci] Configure Endpoint failed");
return rc;
}
return 0;
}
/* ================================================================
* Phase 3: Control Transfer (EP0)
* ================================================================ */
static int xhci_control_transfer(const u8 *setup_pkt, u8 *data, u32 data_len,
u8 direction) {
/* Setup Stage TRB */
u64 setup_val = ((u64)setup_pkt[4] << 32) | ((u64)setup_pkt[5] << 40) |
((u64)setup_pkt[6] << 48) | ((u64)setup_pkt[7] << 56);
setup_val |= (u64)setup_pkt[0] | ((u64)setup_pkt[1] << 8) |
((u64)setup_pkt[2] << 16) | ((u64)setup_pkt[3] << 24);
u32 setup_status = 8; /* Setup packet length */
u32 setup_control = (TRB_TYPE_SETUP_STAGE << TRB_TYPE_SHIFT) | TRB_IOC;
/* Set direction in TRB: bit 16 of Setup Stage TRB */
if (direction) setup_control |= (1u << 16);
xhci_ring_enqueue(&g_ep0_ring, setup_val, setup_status, setup_control);
/* Data Stage TRB (if data_len > 0) */
if (data_len > 0 && data) {
/* Copy data to transfer buffer for OUT direction */
if (direction == 0) {
xhci_memcpy(g_xfer_buf.virt, data, data_len);
__asm__ volatile("wbinvd" ::: "memory");
}
u64 data_phys = direction ? g_xfer_buf.phys : g_xfer_buf.phys;
u32 data_status = data_len;
u32 data_control = (TRB_TYPE_DATA_STAGE << TRB_TYPE_SHIFT) | TRB_IOC;
if (direction) data_control |= (1u << 16); /* DIR=IN */
xhci_ring_enqueue(&g_ep0_ring, data_phys, data_status, data_control);
}
/* Status Stage TRB */
u32 status_dir = direction ? 0 : 1; /* opposite of data direction */
u32 status_control = (TRB_TYPE_STATUS_STAGE << TRB_TYPE_SHIFT) | TRB_IOC;
if (status_dir) status_control |= (1u << 16);
xhci_ring_enqueue(&g_ep0_ring, 0, 0, status_control);
xhci_mb();
xhci_ring_doorbell(g_msc.slot_id, 1); /* EP1 = EP0+1 */
/* Poll for Transfer Event */
u64 timeout_ms = 5000;
u64 out_param = 0;
u32 out_status = 0;
int rc = xhci_poll_event(EVT_TYPE_TRANSFER, timeout_ms,
&out_param, &out_status, 0);
if (rc != 0) {
g_log->warn("[xhci] control transfer failed");
return rc;
}
/* For IN direction, copy data from DMA buffer */
if (direction && data_len > 0 && data) {
xhci_memcpy(data, g_xfer_buf.virt, data_len);
}
/* Clear EINT */
mmio_write32(g_cap_length + XHCI_OP_USBSTS,
mmio_read32(g_cap_length + XHCI_OP_USBSTS) | USBSTS_EINT);
return 0;
}
/* ================================================================
* Phase 3: USB Descriptor reads
* ================================================================ */
static int xhci_get_device_descriptor(u8 *out_desc) {
u8 setup[8];
setup[0] = 0x80; /* bmRequestType: Device-to-Host, Standard, Device */
setup[1] = 0x06; /* bRequest: GET_DESCRIPTOR */
setup[2] = 0x00; /* wValue low: Descriptor Index */
setup[3] = 0x01; /* wValue high: Device Descriptor */
setup[4] = 0x00; /* wIndex low */
setup[5] = 0x00; /* wIndex high */
setup[6] = 0x12; /* wLength low: 18 bytes */
setup[7] = 0x00; /* wLength high */
xhci_zero(out_desc, 18);
return xhci_control_transfer(setup, out_desc, 18, 1);
}
static int xhci_get_config_descriptor(u8 *out_desc, u32 max_len) {
u8 setup[8];
setup[0] = 0x80; /* Device-to-Host, Standard, Device */
setup[1] = 0x06; /* GET_DESCRIPTOR */
setup[2] = 0x00; /* Index */
setup[3] = 0x02; /* Configuration Descriptor */
setup[4] = 0x00;
setup[5] = 0x00;
setup[6] = (u8)(max_len & 0xFF);
setup[7] = (u8)((max_len >> 8) & 0xFF);
xhci_zero(out_desc, max_len);
return xhci_control_transfer(setup, out_desc, max_len, 1);
}
/* ================================================================
* Phase 4: Bulk Transfer
* ================================================================ */
static int xhci_bulk_transfer(xhci_ring *ring, u8 ep_num,
u8 direction, /* 0=OUT, 1=IN */
const void *data, u32 data_len) {
if (data_len == 0) return -1;
/* For OUT, copy data to DMA buffer */
if (direction == 0) {
xhci_memcpy(g_xfer_buf.virt, data, data_len);
__asm__ volatile("wbinvd" ::: "memory");
}
/* Enqueue Normal TRB(s) — single TRB for now (up to 64KB) */
u32 control = (TRB_TYPE_NORMAL << TRB_TYPE_SHIFT) | TRB_IOC;
xhci_ring_enqueue(ring, g_xfer_buf.phys, data_len, control);
xhci_mb();
xhci_ring_doorbell(g_msc.slot_id, ep_num);
/* Poll for Transfer Event */
u64 out_param = 0;
u32 out_status = 0;
int rc = xhci_poll_event(EVT_TYPE_TRANSFER, 10000,
&out_param, &out_status, 0);
if (rc != 0) {
g_log->warn("[xhci] bulk transfer failed");
return rc;
}
/* For IN, copy data from DMA buffer */
if (direction == 1) {
xhci_memcpy((void *)data, g_xfer_buf.virt, data_len);
}
/* Clear EINT */
mmio_write32(g_cap_length + XHCI_OP_USBSTS,
mmio_read32(g_cap_length + XHCI_OP_USBSTS) | USBSTS_EINT);
return 0;
}
/* ================================================================
* Phase 4: BOT (Bulk-Only Transport) + SCSI
* ================================================================ */
static int xhci_bot_send_cbw(u8 lun, u8 flags, u32 data_len,
const u8 *cb, u8 cb_len) {
u8 cbw[31];
xhci_zero(cbw, 31);
/* Signature */
cbw[0] = 0x55; cbw[1] = 0x53; cbw[2] = 0x42; cbw[3] = 0x43;
/* Tag (little-endian) */
u32 tag = g_msc.cbw_tag++;
cbw[4] = (u8)(tag & 0xFF);
cbw[5] = (u8)((tag >> 8) & 0xFF);
cbw[6] = (u8)((tag >> 16) & 0xFF);
cbw[7] = (u8)((tag >> 24) & 0xFF);
/* Data Transfer Length (little-endian) */
cbw[8] = (u8)(data_len & 0xFF);
cbw[9] = (u8)((data_len >> 8) & 0xFF);
cbw[10] = (u8)((data_len >> 16) & 0xFF);
cbw[11] = (u8)((data_len >> 24) & 0xFF);
/* Flags */
cbw[12] = flags;
/* LUN */
cbw[13] = lun;
/* CB Length */
cbw[14] = cb_len;
/* Command Block */
for (u8 i = 0; i < cb_len && i < 16; i++)
cbw[15 + i] = cb[i];
return xhci_bulk_transfer(&g_bulk_out_ring, g_msc.bulk_out_ep,
0, cbw, 31);
}
static int xhci_bot_receive_csw(void) {
int rc = xhci_bulk_transfer(&g_bulk_in_ring, g_msc.bulk_in_ep,
1, g_csw_buf.virt, 13);
if (rc != 0) return rc;
/* Verify CSW signature */
u8 *csw = (u8 *)g_csw_buf.virt;
if (csw[0] != 0x55 || csw[1] != 0x53 || csw[2] != 0x42 || csw[3] != 0x53) {
g_log->error("[xhci] CSW signature mismatch");
return -2;
}
/* CSW status: byte 12, 0=OK */
u8 status = csw[12];
if (status != 0) {
log_hex("[xhci] CSW status=", status);
return -3;
}
return 0;
}
/* SCSI INQUIRY */
static int xhci_scsi_inquiry(void) {
u8 cb[16];
xhci_zero(cb, 16);
cb[0] = SCSI_INQUIRY;
cb[4] = 36; /* allocation length */
int rc = xhci_bot_send_cbw(0, 0x80, 36, cb, 6);
if (rc != 0) return rc;
/* Data phase: IN 36 bytes */
u8 inq_data[36];
rc = xhci_bulk_transfer(&g_bulk_in_ring, g_msc.bulk_in_ep,
1, inq_data, 36);
if (rc != 0) return rc;
/* CSW */
rc = xhci_bot_receive_csw();
if (rc != 0) return rc;
/* Parse INQUIRY data */
u8 dev_type = inq_data[0] & 0x1F;
log_hex("[xhci] INQ PeripheralType=", dev_type);
g_log->info("[xhci] INQ Vendor:");
g_log->info((const char *)(inq_data + 8)); /* Not null-terminated but safe for log */
return (dev_type == 0x00) ? 0 : -1; /* 0 = Direct Access Block */
}
/* SCSI READ CAPACITY(10) */
static int xhci_scsi_read_capacity(u64 *out_sectors, u32 *out_blk_size) {
u8 cb[16];
xhci_zero(cb, 16);
cb[0] = SCSI_READ_CAPACITY10;
int rc = xhci_bot_send_cbw(0, 0x80, 8, cb, 10);
if (rc != 0) return rc;
/* Data phase: IN 8 bytes */
u8 cap_data[8];
rc = xhci_bulk_transfer(&g_bulk_in_ring, g_msc.bulk_in_ep,
1, cap_data, 8);
if (rc != 0) return rc;
/* CSW */
rc = xhci_bot_receive_csw();
if (rc != 0) return rc;
/* Parse big-endian */
u32 max_lba = ((u32)cap_data[0] << 24) | ((u32)cap_data[1] << 16) |
((u32)cap_data[2] << 8) | (u32)cap_data[3];
u32 blk_size = ((u32)cap_data[4] << 24) | ((u32)cap_data[5] << 16) |
((u32)cap_data[6] << 8) | (u32)cap_data[7];
*out_sectors = (u64)max_lba + 1; /* READ CAPACITY returns max LBA */
*out_blk_size = blk_size;
log_hex("[xhci] capacity sectors=", *out_sectors);
log_hex("[xhci] block size=", blk_size);
return 0;
}
/* SCSI TEST UNIT READY */
static int xhci_scsi_test_unit_ready(void) {
u8 cb[16];
xhci_zero(cb, 16);
cb[0] = SCSI_TEST_UNIT_READY;
int rc = xhci_bot_send_cbw(0, 0x00, 0, cb, 6);
if (rc != 0) return rc;
return xhci_bot_receive_csw();
}
/* SCSI READ(10) */
static int xhci_scsi_read10(u64 lba, u32 count, void *buffer) {
u8 cb[16];
xhci_zero(cb, 16);
cb[0] = SCSI_READ10;
cb[2] = (u8)((lba >> 24) & 0xFF);
cb[3] = (u8)((lba >> 16) & 0xFF);
cb[4] = (u8)((lba >> 8) & 0xFF);
cb[5] = (u8)(lba & 0xFF);
cb[7] = (u8)((count >> 8) & 0xFF);
cb[8] = (u8)(count & 0xFF);
u32 data_len = count * 512;
int rc = xhci_bot_send_cbw(0, 0x80, data_len, cb, 10);
if (rc != 0) return rc;
/* Data phase: IN */
rc = xhci_bulk_transfer(&g_bulk_in_ring, g_msc.bulk_in_ep,
1, buffer, data_len);
if (rc != 0) return rc;
return xhci_bot_receive_csw();
}
/* SCSI WRITE(10) */
static int xhci_scsi_write10(u64 lba, u32 count, const void *buffer) {
u8 cb[16];
xhci_zero(cb, 16);
cb[0] = SCSI_WRITE10;
cb[2] = (u8)((lba >> 24) & 0xFF);
cb[3] = (u8)((lba >> 16) & 0xFF);
cb[4] = (u8)((lba >> 8) & 0xFF);
cb[5] = (u8)(lba & 0xFF);
cb[7] = (u8)((count >> 8) & 0xFF);
cb[8] = (u8)(count & 0xFF);
u32 data_len = count * 512;
int rc = xhci_bot_send_cbw(0, 0x00, data_len, cb, 10);
if (rc != 0) return rc;
/* Data phase: OUT */
rc = xhci_bulk_transfer(&g_bulk_out_ring, g_msc.bulk_out_ep,
0, buffer, data_len);
if (rc != 0) return rc;
return xhci_bot_receive_csw();
}
/* ================================================================
* Phase 4+5: Block device interface
* ================================================================ */
static int xhci_block_read(void *ctx, u64 lba, u32 count, void *buffer) {
(void)ctx;
if (!g_msc.ready || !buffer || count == 0) return -1;
DKM_STAT_INC(xhci_block_reads);
u8 *buf = (u8 *)buffer;
while (count > 0) {
u32 chunk = count > 16 ? 16 : count; /* max 16 sectors (8KB) per SCSI cmd */
int rc = xhci_scsi_read10(lba, chunk, g_xfer_buf.virt);
if (rc != 0) {
log_hex("[xhci] READ10 failed lba=", lba);
return rc;
}
xhci_memcpy(buf, g_xfer_buf.virt, chunk * 512);
buf += chunk * 512;
lba += chunk;
count -= chunk;
}
return 0;
}
static int xhci_block_write(void *ctx, u64 lba, u32 count, const void *buffer) {
(void)ctx;
if (!g_msc.ready || !buffer || count == 0) return -1;
DKM_STAT_INC(xhci_block_writes);
const u8 *buf = (const u8 *)buffer;
while (count > 0) {
u32 chunk = count > 16 ? 16 : count;
xhci_memcpy(g_xfer_buf.virt, buf, chunk * 512);
__asm__ volatile("wbinvd" ::: "memory"); /* Cache flush for DMA */
int rc = xhci_scsi_write10(lba, chunk, g_xfer_buf.virt);
if (rc != 0) {
log_hex("[xhci] WRITE10 failed lba=", lba);
return rc;
}
buf += chunk * 512;
lba += chunk;
count -= chunk;
}
return 0;
}
/* ================================================================
* Phase 3: Build Input Context for Address Device
* ================================================================ */
static void xhci_build_input_ctx_slot(u8 slot_id, u8 speed, u16 mps0) {
(void)slot_id;
u32 ctx_sz = g_ctx_size;
u8 *ic = (u8 *)g_input_ctx.virt;
xhci_zero(ic, g_input_ctx.size);
/* Input Control Context: enable Slot Context (bit 0) and EP0 (bit 1) */
u32 *icc = (u32 *)ic;
icc[0] = (1u << 1) | (1u << 0); /* A0=1 (Slot), A1=1 (EP0) */
/* Slot Context starts at offset ctx_sz */
u32 *slot_ctx = (u32 *)(ic + ctx_sz);
u32 route_string = 0; /* direct-connect, no hub */
slot_ctx[0] = route_string | ((u32)speed << 29);
slot_ctx[1] = (u32)mps0; /* Max Packet Size for EP0 */
slot_ctx[2] = (1u << 27); /* Context Entries = 1 (only EP0) */
/* EP0 Context starts at offset ctx_sz * 2 */
u32 *ep0_ctx = (u32 *)(ic + ctx_sz * 2);
/* EP Type = Control, Max Packet Size, etc. */
ep0_ctx[1] = (4u << 3) | ((u32)mps0 << 16); /* EP Type=4 (Control IN), MPS */
ep0_ctx[4] = 8; /* Average TRB Length */
/* Dequeue Pointer: EP0 transfer ring */
u64 ep0_deq = g_ep0_ring.dma.phys | (u64)g_ep0_ring.ccs;
ep0_ctx[6] = (u32)(ep0_deq & 0xFFFFFFFFu);
ep0_ctx[7] = (u32)(ep0_deq >> 32);
}
static void xhci_build_input_ctx_bulk_eps(u8 bulk_out_ep, u8 bulk_in_ep,
u16 out_mps, u16 in_mps) {
u32 ctx_sz = g_ctx_size;
u8 *ic = (u8 *)g_input_ctx.virt;
/* Update Input Control Context: enable EP0, Bulk OUT, Bulk IN */
u32 *icc = (u32 *)ic;
icc[0] = (1u << 1) | (1u << 0) |
(1u << bulk_out_ep) | (1u << bulk_in_ep);
/* Update Slot Context: Context Entries = max(bulk_in_ep, bulk_out_ep) */
u32 *slot_ctx = (u32 *)(ic + ctx_sz);
u32 max_ep = bulk_out_ep > bulk_in_ep ? bulk_out_ep : bulk_in_ep;
slot_ctx[2] = (max_ep << 27);
/* Bulk OUT Endpoint Context (at offset ctx_sz * (1 + bulk_out_ep)) */
u32 *out_ctx = (u32 *)(ic + ctx_sz * (1 + bulk_out_ep));
out_ctx[1] = (EP_TYPE_BULK_OUT << 3) | ((u32)out_mps << 16);
out_ctx[4] = 512; /* Average TRB Length */
u64 out_deq = g_bulk_out_ring.dma.phys | (u64)g_bulk_out_ring.ccs;
out_ctx[6] = (u32)(out_deq & 0xFFFFFFFFu);
out_ctx[7] = (u32)(out_deq >> 32);
/* Bulk IN Endpoint Context (at offset ctx_sz * (1 + bulk_in_ep)) */
u32 *in_ctx = (u32 *)(ic + ctx_sz * (1 + bulk_in_ep));
in_ctx[1] = (EP_TYPE_BULK_IN << 3) | ((u32)in_mps << 16);
in_ctx[4] = 512; /* Average TRB Length */
u64 in_deq = g_bulk_in_ring.dma.phys | (u64)g_bulk_in_ring.ccs;
in_ctx[6] = (u32)(in_deq & 0xFFFFFFFFu);
in_ctx[7] = (u32)(in_deq >> 32);
}
/* ================================================================
* Phase 3: Full device enumeration
* ================================================================ */
static int xhci_enum_msc_device(u32 port_idx) {
u8 speed = xhci_get_port_speed(port_idx);
log_hex("[xhci] port speed=", speed);
/* Default MaxPacketSize for EP0 based on speed */
u16 mps0 = 64; /* High/Super-Speed default */
if (speed == USB_SPEED_FULL) mps0 = 64;
if (speed == USB_SPEED_LOW) mps0 = 8;
/* Step 1: Enable Slot */
u8 slot_id = 0;
if (xhci_enable_slot(&slot_id) != 0) return -1;
g_msc.slot_id = slot_id;
g_msc.speed = speed;
/* Step 2: Allocate per-device DMA buffers */
if (g_api->dma->alloc_pages(4, 4096, 0x100000000ULL, &g_input_ctx) != 0) return -2;
if (g_api->dma->alloc_pages(4, 4096, 0x100000000ULL, &g_dev_ctx) != 0) return -2;
if (g_api->dma->alloc_pages(4, 4096, 0x100000000ULL, &g_xfer_buf) != 0) return -2;
if (g_api->dma->alloc_pages(1, 4096, 0x100000000ULL, &g_csw_buf) != 0) return -2;
if (xhci_ring_init(&g_ep0_ring, XFER_RING_SIZE) != 0) return -2;
if (xhci_ring_init(&g_bulk_out_ring, XFER_RING_SIZE) != 0) return -2;
if (xhci_ring_init(&g_bulk_in_ring, XFER_RING_SIZE) != 0) return -2;
/* Step 3: Build Input Context and Address Device (BSR=1 first) */
xhci_build_input_ctx_slot(slot_id, speed, mps0);
if (xhci_address_device(slot_id, 1) != 0) {
/* BSR=1 failed, try without BSR */
xhci_build_input_ctx_slot(slot_id, speed, mps0);
if (xhci_address_device(slot_id, 0) != 0) return -3;
}
/* Step 4: Get Device Descriptor */
u8 dev_desc[18];
if (xhci_get_device_descriptor(dev_desc) != 0) {
g_log->warn("[xhci] GET_DESCRIPTOR(Device) failed");
return -4;
}
u8 dev_class = dev_desc[4];
u16 vid = (u16)dev_desc[8] | ((u16)dev_desc[9] << 8);
u16 pid = (u16)dev_desc[10] | ((u16)dev_desc[11] << 8);
u8 real_mps0 = dev_desc[7];
log_hex("[xhci] dev class=", dev_class);
log_hex("[xhci] VID=", vid);
log_hex("[xhci] PID=", pid);
log_hex("[xhci] bMaxPacketSize0=", real_mps0);
/* Step 5: Re-address with real MPS if different */
if (real_mps0 != mps0 && real_mps0 >= 8) {
mps0 = real_mps0;
xhci_build_input_ctx_slot(slot_id, speed, mps0);
if (xhci_address_device(slot_id, 0) != 0) {
g_log->warn("[xhci] re-address failed");
/* Continue anyway — device may still work */
}
}
/* Step 6: Get Configuration Descriptor */
u8 cfg_desc[255];
if (xhci_get_config_descriptor(cfg_desc, 255) != 0) {
g_log->warn("[xhci] GET_DESCRIPTOR(Config) failed");
return -5;
}
/* Parse configuration descriptor to find MSC interface and endpoints */
u16 total_len = (u16)cfg_desc[2] | ((u16)cfg_desc[3] << 8);
if (total_len < 9) return -5;
u8 bulk_out_ep = 0, bulk_in_ep = 0;
u16 bulk_out_mps = 512, bulk_in_mps = 512;
int msc_found = 0;
/* Walk through descriptors: config(9) + interface(9) + endpoints(7*N) */
u32 pos = 9; /* skip config descriptor */
while (pos + 2 <= (u32)total_len && pos + cfg_desc[pos] <= (u32)total_len) {
u8 desc_len = cfg_desc[pos];
u8 desc_type = cfg_desc[pos + 1];
if (desc_type == 4 && desc_len >= 9) {
/* Interface Descriptor */
u8 iface_class = cfg_desc[pos + 5];
u8 iface_subclass = cfg_desc[pos + 6];
u8 iface_protocol = cfg_desc[pos + 7];
if (iface_class == 0x08 && iface_subclass == 0x06 && iface_protocol == 0x50) {
msc_found = 1;
g_log->info("[xhci] MSC BOT interface found");
/* Scan following endpoint descriptors */
u32 ep_pos = pos + desc_len;
while (ep_pos + 7 <= (u32)total_len &&
cfg_desc[ep_pos + 1] == 5) { /* endpoint descriptor */
u8 ep_addr = cfg_desc[ep_pos + 2];
u8 ep_attr = cfg_desc[ep_pos + 3];
u16 ep_mps = (u16)cfg_desc[ep_pos + 4] | ((u16)cfg_desc[ep_pos + 5] << 8);
if ((ep_attr & 0x03) == 0x02) { /* Bulk */
if (ep_addr & 0x80) {
bulk_in_ep = ep_addr & 0x0F;
bulk_in_mps = ep_mps;
} else {
bulk_out_ep = ep_addr & 0x0F;
bulk_out_mps = ep_mps;
}
}
ep_pos += cfg_desc[ep_pos];
}
break;
}
}
pos += desc_len;
}
if (!msc_found || bulk_out_ep == 0 || bulk_in_ep == 0) {
g_log->warn("[xhci] no MSC BOT interface found");
return -6;
}
log_hex("[xhci] Bulk OUT EP=", bulk_out_ep);
log_hex("[xhci] Bulk IN EP=", bulk_in_ep);
log_hex("[xhci] Bulk OUT MPS=", bulk_out_mps);
log_hex("[xhci] Bulk IN MPS=", bulk_in_mps);
g_msc.bulk_out_ep = bulk_out_ep;
g_msc.bulk_in_ep = bulk_in_ep;
g_msc.bulk_out_mps = bulk_out_mps;
g_msc.bulk_in_mps = bulk_in_mps;
/* Step 7: Configure Endpoint */
xhci_zero(g_input_ctx.virt, g_input_ctx.size);
xhci_build_input_ctx_bulk_eps(bulk_out_ep, bulk_in_ep,
bulk_out_mps, bulk_in_mps);
if (xhci_configure_endpoint(slot_id) != 0) {
g_log->warn("[xhci] Configure Endpoint failed");
return -7;
}
/* Step 8: SCSI INQUIRY to verify MSC device */
if (xhci_scsi_inquiry() != 0) {
g_log->warn("[xhci] INQUIRY failed or not block device");
/* Continue anyway — some devices return non-zero peripheral type */
}
/* Step 9: TEST UNIT READY (retry up to 5 times) */
for (int i = 0; i < 5; i++) {
if (xhci_scsi_test_unit_ready() == 0) break;
dkm_delay_ms(100);
}
/* Step 10: READ CAPACITY */
u64 sectors = 0;
u32 blk_size = 512;
if (xhci_scsi_read_capacity(&sectors, &blk_size) != 0) {
g_log->warn("[xhci] READ CAPACITY failed");
/* Use defaults */
sectors = 0;
blk_size = 512;
}
g_msc.sector_count = sectors;
g_msc.sector_size = blk_size;
g_msc.cbw_tag = 1;
g_msc.ready = 1;
DKM_STAT_INC(xhci_msc_found);
log_hex("[xhci] MSC device ready, sectors=", sectors);
log_hex("[xhci] MSC device block_size=", blk_size);
return 0;
}
/* ================================================================
* driver_init — main entry point
* ================================================================ */
__attribute__((visibility("default")))
int driver_init(const struct dkm_kernel_api *api,
struct dkm_driver_handle *handle) {
(void)handle;
dkm_tsc_calibrate();
if (!api || !api->log) return -1;
g_api = api;
g_log = api->log;
dkm_instr_init(api);
g_log->info("[xhci] init begin");
/* ---- Phase 1: PCI discovery ---- */
u8 bus = 0, dev = 0, func = 0;
if (xhci_find(&bus, &dev, &func) != 0) {
g_log->info("[xhci] xHCI controller not found");
g_log->info("[xhci] driver ready");
return 0;
}
g_pci_bus = bus; g_pci_dev = dev; g_pci_func = func;
DKM_STAT_INC(xhci_pci_found);
g_log->info("[xhci] xHCI controller found");
log_hex("[xhci] bus=", bus);
log_hex("[xhci] dev=", dev);
log_hex("[xhci] func=", func);
u32 vd = dkm_pci_read(bus, dev, func, PCI_VENDOR_ID);
log_hex("[xhci] vendor=", vd & 0xffff);
log_hex("[xhci] device=", vd >> 16);
/* Enable PCI MEM + BUSM, disable INTx (polling mode) */
u32 command = dkm_pci_read(bus, dev, func, PCI_COMMAND) & 0xffff;
command |= PCI_CMD_MEM | PCI_CMD_BUSM | (1u << 10);
dkm_pci_write(bus, dev, func, PCI_COMMAND, command);
log_hex("[xhci] PCI command=", command);
/* Read BAR0 (64-bit) */
u32 bar0_lo = dkm_pci_read(bus, dev, func, PCI_BAR0);
u32 bar1_hi = dkm_pci_read(bus, dev, func, PCI_BAR1);
u64 bar_phys;
if (bar0_lo & 1u) {
g_log->warn("[xhci] BAR0 is IO space; unsupported");
g_log->info("[xhci] driver ready");
return 0;
}
if ((bar0_lo & 0x6u) == 0x4u) {
bar_phys = ((u64)bar1_hi << 32) | (u64)(bar0_lo & 0xFFFFFFF0u);
} else {
bar_phys = (u64)(bar0_lo & 0xFFFFFFF0u);
}
u32 irq_line = dkm_pci_read(bus, dev, func, PCI_IRQ_LINE) & 0xff;
log_hex("[xhci] BAR0 phys=", bar_phys);
log_hex("[xhci] IRQ line=", irq_line);
log_hex("[xhci] HHDM offset=", api->hhdm_offset);
if (!api->hhdm_offset || !bar_phys) {
g_log->warn("[xhci] missing HHDM or BAR0; skip");
g_log->info("[xhci] driver ready");
return 0;
}
/* ---- Phase 1: MMIO mapping ---- */
g_mmio = xhci_map_bar(api, bar_phys);
if (!g_mmio) {
g_log->error("[xhci] BAR MMIO unavailable; driver inactive");
g_log->info("[xhci] driver ready");
return 0;
}
/* ---- Phase 1: Parse capabilities ---- */
if (xhci_parse_caps() != 0) {
g_log->error("[xhci] capability parse failed");
g_log->info("[xhci] driver ready");
return 0;
}
/* ---- Phase 1: BIOS Handoff ---- */
xhci_bios_handoff();
/* ---- Phase 1: Controller Reset ---- */
if (xhci_controller_reset() != 0) {
g_log->error("[xhci] controller reset failed");
g_log->info("[xhci] driver ready");
return 0;
}
/* ---- Phase 2: Setup Rings + DCBAA + Scratchpad ---- */
if (!api->dma) {
g_log->warn("[xhci] DMA API unavailable");
g_log->info("[xhci] driver ready");
return 0;
}
if (xhci_setup_rings() != 0) {
g_log->error("[xhci] ring setup failed");
g_log->info("[xhci] driver ready");
return 0;
}
/* ---- Phase 2: Start Controller ---- */
if (xhci_controller_start() != 0) {
g_log->error("[xhci] controller start failed");
g_log->info("[xhci] driver ready");
return 0;
}
/* ---- Phase 3: Port Scan + Device Enumeration ---- */
/*
* Wait 100ms after controller start for QEMU to complete USB device
* attachment and update port status. Without this delay, PORTSC.CCS
* may read 0 even though a device is physically connected.
*/
g_log->info("[xhci] waiting 100ms for port settle...");
dkm_delay_ms(100);
g_msc.ready = 0;
for (u32 port = 0; port < g_max_ports; port++) {
u32 port_off = g_port_base + port * XHCI_PORT_STRIDE + XHCI_PORT_SC;
u32 portsc = mmio_read32(port_off);
/* Always log PORTSC for debugging, even if no device is connected */
log_hex("[xhci] port=", port);
log_hex("[xhci] PORTSC=", portsc);
if (!(portsc & PORTSC_CCS)) {
/*
* If PPC (Per-Port Power Control) is supported, the port may
* need to be powered on before CCS reflects device connection.
* Set PP (Port Power) bit in PORTSC to enable port power.
* If PPC=0, ports are always powered and this write is a no-op.
*/
if (g_ppc && !(portsc & (1u << 9))) {
g_log->info("[xhci] enabling port power");
mmio_write32(port_off, portsc | (1u << 9));
/* Wait briefly for power to stabilize */
dkm_delay_ms(20);
portsc = mmio_read32(port_off);
log_hex("[xhci] PORTSC after PP=", portsc);
}
if (!(portsc & PORTSC_CCS)) continue; /* Still no device */
}
g_log->info("[xhci] device connected");
/* Port Reset */
if (xhci_reset_port(port) != 0) {
g_log->warn("[xhci] port reset failed; skipping");
continue;
}
g_log->info("[xhci] port reset OK");
/* Try to enumerate as MSC device */
if (xhci_enum_msc_device(port) == 0) {
g_log->info("[xhci] MSC enumeration successful");
break; /* First MSC device is enough for now */
}
g_log->warn("[xhci] MSC enumeration failed; trying next port");
}
/* ---- Phase 5: Register Block Device ---- */
if (g_msc.ready) {
if (api->block && api->block->register_device) {
struct dkm_block_device_desc desc;
desc.name = "usb0";
desc.sector_size = g_msc.sector_size;
desc.sector_count = g_msc.sector_count;
desc.ctx = 0;
desc.read = xhci_block_read;
desc.write = xhci_block_write;
int index = api->block->register_device(&desc);
log_hex("[xhci] block provider index=", (u64)(i64)index);
} else {
g_log->warn("[xhci] block API unavailable; provider not registered");
}
} else {
g_log->info("[xhci] no MSC device found; block provider not registered");
}
g_log->info("[xhci] driver ready");
return 0;
}
__attribute__((visibility("default")))
int driver_exit(struct dkm_driver_handle *handle) {
(void)handle;
/* Halt controller if it was started */
if (g_mmio) {
u32 usbcmd = mmio_read32(g_cap_length + XHCI_OP_USBCMD);
mmio_write32(g_cap_length + XHCI_OP_USBCMD, usbcmd & ~USBCMD_RS);
}
return 0;
}
CODE/Deaicup Software/pe/.cargo/config.toml
+16
View File
@@ -0,0 +1,16 @@
# Build for Windows PE64 without any MSVC toolchain:
# - lld-link (LLVM) links directly in MSVC flavor
# - all Win32 imports use raw-dylib (no import .lib files needed)
# - no CRT: we provide mainCRTStartup ourselves and link /NODEFAULTLIB
[build]
target = "x86_64-pc-windows-msvc"
[target.x86_64-pc-windows-msvc]
linker = "C:/Program Files/LLVM/bin/lld-link.exe"
rustflags = [
"-C", "link-arg=/NODEFAULTLIB",
"-C", "link-arg=/SUBSYSTEM:CONSOLE",
"-C", "link-arg=/ENTRY:mainCRTStartup",
"-C", "link-arg=/STACK:4194304",
"-C", "link-arg=/DEBUG:NONE",
]
CODE/Deaicup Software/pe/Cargo.lock
Generated
+240
View File
@@ -0,0 +1,240 @@
# This file is automatically @generated by Cargo.
# It is not intended for manual editing.
version = 4
[[package]]
name = "ab_glyph"
version = "0.2.32"
source = "registry+https://github.com/rust-lang/crates.io-index"
checksum = "01c0457472c38ea5bd1c3b5ada5e368271cb550be7a4ca4a0b4634e9913f6cc2"
dependencies = [
"ab_glyph_rasterizer",
"owned_ttf_parser",
]
[[package]]
name = "ab_glyph_rasterizer"
version = "0.1.10"
source = "registry+https://github.com/rust-lang/crates.io-index"
checksum = "366ffbaa4442f4684d91e2cd7c5ea7c4ed8add41959a31447066e279e432b618"
[[package]]
name = "ahash"
version = "0.8.12"
source = "registry+https://github.com/rust-lang/crates.io-index"
checksum = "5a15f179cd60c4584b8a8c596927aadc462e27f2ca70c04e0071964a73ba7a75"
dependencies = [
"cfg-if",
"once_cell",
"version_check",
"zerocopy",
]
[[package]]
name = "bitflags"
version = "2.13.1"
source = "registry+https://github.com/rust-lang/crates.io-index"
checksum = "b588b76d00fde79687d7646a9b5bdf3cc0f655e0bbd080335a95d7e96f3587da"
[[package]]
name = "cfg-if"
version = "1.0.4"
source = "registry+https://github.com/rust-lang/crates.io-index"
checksum = "9330f8b2ff13f34540b44e946ef35111825727b38d33286ef986142615121801"
[[package]]
name = "deaicup-pe"
version = "0.1.0"
dependencies = [
"egui",
]
[[package]]
name = "ecolor"
version = "0.27.2"
source = "registry+https://github.com/rust-lang/crates.io-index"
checksum = "20930a432bbd57a6d55e07976089708d4893f3d556cf42a0d79e9e321fa73b10"
[[package]]
name = "egui"
version = "0.27.2"
source = "registry+https://github.com/rust-lang/crates.io-index"
checksum = "584c5d1bf9a67b25778a3323af222dbe1a1feb532190e103901187f92c7fe29a"
dependencies = [
"ahash",
"epaint",
"nohash-hasher",
]
[[package]]
name = "emath"
version = "0.27.2"
source = "registry+https://github.com/rust-lang/crates.io-index"
checksum = "e4c3a552cfca14630702449d35f41c84a0d15963273771c6059175a803620f3f"
[[package]]
name = "epaint"
version = "0.27.2"
source = "registry+https://github.com/rust-lang/crates.io-index"
checksum = "b381f8b149657a4acf837095351839f32cd5c4aec1817fc4df84e18d76334176"
dependencies = [
"ab_glyph",
"ahash",
"ecolor",
"emath",
"nohash-hasher",
"parking_lot",
]
[[package]]
name = "libc"
version = "0.2.189"
source = "registry+https://github.com/rust-lang/crates.io-index"
checksum = "3eaf3ede3fee6db1a4c2ee091bf8a8b4dccdc6d17f656fb07896ee72867612f2"
[[package]]
name = "lock_api"
version = "0.4.14"
source = "registry+https://github.com/rust-lang/crates.io-index"
checksum = "224399e74b87b5f3557511d98dff8b14089b3dadafcab6bb93eab67d3aace965"
dependencies = [
"scopeguard",
]
[[package]]
name = "nohash-hasher"
version = "0.2.0"
source = "registry+https://github.com/rust-lang/crates.io-index"
checksum = "2bf50223579dc7cdcfb3bfcacf7069ff68243f8c363f62ffa99cf000a6b9c451"
[[package]]
name = "once_cell"
version = "1.21.4"
source = "registry+https://github.com/rust-lang/crates.io-index"
checksum = "9f7c3e4beb33f85d45ae3e3a1792185706c8e16d043238c593331cc7cd313b50"
[[package]]
name = "owned_ttf_parser"
version = "0.25.1"
source = "registry+https://github.com/rust-lang/crates.io-index"
checksum = "36820e9051aca1014ddc75770aab4d68bc1e9e632f0f5627c4086bc216fb583b"
dependencies = [
"ttf-parser",
]
[[package]]
name = "parking_lot"
version = "0.12.5"
source = "registry+https://github.com/rust-lang/crates.io-index"
checksum = "93857453250e3077bd71ff98b6a65ea6621a19bb0f559a85248955ac12c45a1a"
dependencies = [
"lock_api",
"parking_lot_core",
]
[[package]]
name = "parking_lot_core"
version = "0.9.12"
source = "registry+https://github.com/rust-lang/crates.io-index"
checksum = "2621685985a2ebf1c516881c026032ac7deafcda1a2c9b7850dc81e3dfcb64c1"
dependencies = [
"cfg-if",
"libc",
"redox_syscall",
"smallvec",
"windows-link",
]
[[package]]
name = "proc-macro2"
version = "1.0.107"
source = "registry+https://github.com/rust-lang/crates.io-index"
checksum = "985e7ec9bb745e6ce6535b544d84d6cd6f7ad8bd711c398938ae983b91a766d9"
dependencies = [
"unicode-ident",
]
[[package]]
name = "quote"
version = "1.0.47"
source = "registry+https://github.com/rust-lang/crates.io-index"
checksum = "1fbf4db142a473a8d80c26bbf18454ed458bf8d26c8219c331daecfdbd079001"
dependencies = [
"proc-macro2",
]
[[package]]
name = "redox_syscall"
version = "0.5.18"
source = "registry+https://github.com/rust-lang/crates.io-index"
checksum = "ed2bf2547551a7053d6fdfafda3f938979645c44812fbfcda098faae3f1a362d"
dependencies = [
"bitflags",
]
[[package]]
name = "scopeguard"
version = "1.2.0"
source = "registry+https://github.com/rust-lang/crates.io-index"
checksum = "94143f37725109f92c262ed2cf5e59bce7498c01bcc1502d7b9afe439a4e9f49"
[[package]]
name = "smallvec"
version = "1.15.2"
source = "registry+https://github.com/rust-lang/crates.io-index"
checksum = "8ed6a63f02c8539c91a8685a86f4099661ba3da017932f6ebbea6de3f0fa7c90"
[[package]]
name = "syn"
version = "2.0.119"
source = "registry+https://github.com/rust-lang/crates.io-index"
checksum = "872831b642d1a07999a962a351ed35b955ea2cfc8f3862091e2a240a84f17297"
dependencies = [
"proc-macro2",
"quote",
"unicode-ident",
]
[[package]]
name = "ttf-parser"
version = "0.25.1"
source = "registry+https://github.com/rust-lang/crates.io-index"
checksum = "d2df906b07856748fa3f6e0ad0cbaa047052d4a7dd609e231c4f72cee8c36f31"
[[package]]
name = "unicode-ident"
version = "1.0.24"
source = "registry+https://github.com/rust-lang/crates.io-index"
checksum = "e6e4313cd5fcd3dad5cafa179702e2b244f760991f45397d14d4ebf38247da75"
[[package]]
name = "version_check"
version = "0.9.5"
source = "registry+https://github.com/rust-lang/crates.io-index"
checksum = "0b928f33d975fc6ad9f86c8f283853ad26bdd5b10b7f1542aa2fa15e2289105a"
[[package]]
name = "windows-link"
version = "0.2.1"
source = "registry+https://github.com/rust-lang/crates.io-index"
checksum = "f0805222e57f7521d6a62e36fa9163bc891acd422f971defe97d64e70d0a4fe5"
[[package]]
name = "zerocopy"
version = "0.8.55"
source = "registry+https://github.com/rust-lang/crates.io-index"
checksum = "b5a105cd7b140f6eeec8acff2ea38135d3cab283ada58540f629fe51e46696eb"
dependencies = [
"zerocopy-derive",
]
[[package]]
name = "zerocopy-derive"
version = "0.8.55"
source = "registry+https://github.com/rust-lang/crates.io-index"
checksum = "0fe976fb70c78cd64cccfe3a6fc142244e8a77b70959b30faf9d0ac37ee228eb"
dependencies = [
"proc-macro2",
"quote",
"syn",
]
CODE/Deaicup Software/pe/Cargo.toml
+24
View File
@@ -0,0 +1,24 @@
[package]
name = "deaicup-pe"
version = "0.1.0"
edition = "2021"
# Deaicup Software — Windows PE64 target for Deshab UTSM PE compat layer.
# egui UI logic is kept; the eframe runtime is replaced by a hand-written
# Win32 backend (user32 window + GDI DIB blit) plus a pure-Rust software
# rasterizer for egui tessellated primitives.
[[bin]]
name = "deaicup"
path = "src/main.rs"
[dependencies]
egui = { version = "=0.27.2", default-features = false, features = ["default_fonts"] }
[profile.release]
opt-level = 2
debug = false
debug-assertions = false
lto = "thin"
codegen-units = 1
panic = "abort"
CODE/Deaicup Software/pe/src/main.rs
+438
View File
@@ -0,0 +1,438 @@
//! Deaicup Software — Windows PE64 entry point.
//!
//! The original application runs on eframe/egui. For the Deshab UTSM PE
//! compatibility layer we keep the egui UI logic but replace the eframe
//! runtime with a minimal hand-written Win32 backend:
//! user32 window + message pump -> egui RawInput events
//! egui tessellation -> SoftRaster (pure Rust, raster.rs)
//! 32bpp DIB backbuffer -> GDI BitBlt onto the window DC
//!
//! No CRT: the PE entry is `mainCRTStartup` (see .cargo/config.toml) and the
//! process ends via ExitProcess.
#![no_main]
#![allow(static_mut_refs)]
mod raster;
#[allow(dead_code)]
mod rt;
mod win32;
use egui::{self, Color32, Context, Event, Key, Modifiers, PointerButton, Pos2, Rect};
use raster::SoftRaster;
use win32::*;
/* ============================================================
* UI 逻辑（移植自原 eframe 应用 CODE/Deaicup Software/src）
* ========================================================== */
#[derive(Debug, PartialEq, Clone, Copy, Default)]
enum Page {
#[default]
Home,
Tool,
Game,
LinuxWare,
WindowsWare,
Set,
About,
}
#[derive(Default)]
struct DeaicupSoftware {
current_page: Page,
}
impl DeaicupSoftware {
fn ui(&mut self, ctx: &Context) {
// 原应用顶部是远程图片 https://deaicup.com/.../top.png。
// PE 环境无网络，用标题栏替代，保留 75px 高度布局。
egui::TopBottomPanel::top("top_image_panel").show(ctx, |ui| {
ui.set_min_height(75.0);
ui.vertical_centered(|ui| {
ui.add_space(15.0);
ui.label(egui::RichText::new("Deaicup Software").size(30.0).strong());
});
});
// main
egui::SidePanel::left("navigation_panel")
.default_width(200.0)
.resizable(true)
.show(ctx, |ui| {
ui.heading("Menu");
ui.separator();
ui.vertical(|ui| {
if ui.selectable_label(self.current_page == Page::Home, "HOME").clicked() {
self.current_page = Page::Home;
}
if ui.selectable_label(self.current_page == Page::Tool, "TOOL").clicked() {
self.current_page = Page::Tool;
}
if ui.selectable_label(self.current_page == Page::Game, "GAME").clicked() {
self.current_page = Page::Game;
}
if ui
.selectable_label(self.current_page == Page::LinuxWare, "LINUXWARE")
.clicked()
{
self.current_page = Page::LinuxWare;
}
if ui
.selectable_label(self.current_page == Page::WindowsWare, "WINDOWSWARE")
.clicked()
{
self.current_page = Page::WindowsWare;
}
if ui.selectable_label(self.current_page == Page::Set, "SET").clicked() {
self.current_page = Page::Set;
}
if ui
.selectable_label(self.current_page == Page::About, "ABOUT")
.clicked()
{
self.current_page = Page::About;
}
})
});
egui::CentralPanel::default().show(ctx, |ui| {
ui.separator();
match self.current_page {
Page::Home => ui.label("Home"),
Page::Tool => ui.label("Tool"),
Page::Game => ui.label("Game"),
Page::LinuxWare => ui.label("LinuxWare"),
Page::WindowsWare => ui.label("WindowsWare"),
Page::Set => ui.label("Set"),
Page::About => ui.label("About"),
}
});
}
}
/* ============================================================
* 全局输入状态（单线程：wnd_proc 只被 DispatchMessageW 同步调用）
* ========================================================== */
static mut EVENTS: Vec<Event> = Vec::new();
static mut POINTER: Pos2 = Pos2::ZERO;
static mut MOD_ALT: bool = false;
static mut MOD_CTRL: bool = false;
static mut MOD_SHIFT: bool = false;
static mut QUIT: bool = false;
fn current_modifiers() -> Modifiers {
unsafe {
Modifiers {
alt: MOD_ALT,
ctrl: MOD_CTRL,
shift: MOD_SHIFT,
mac_cmd: false,
command: MOD_CTRL,
}
}
}
#[inline]
fn lparam_x(l: LPARAM) -> i32 {
(l as i32 & 0xFFFF) as i16 as i32
}
#[inline]
fn lparam_y(l: LPARAM) -> i32 {
((l as i32 >> 16) & 0xFFFF) as i16 as i32
}
fn push_pointer_button(button: PointerButton, pressed: bool, l: LPARAM) -> LRESULT {
unsafe {
POINTER = Pos2::new(lparam_x(l) as f32, lparam_y(l) as f32);
EVENTS.push(Event::PointerButton {
pos: POINTER,
button,
pressed,
modifiers: current_modifiers(),
});
}
0
}
fn vk_to_egui_key(vk: usize) -> Option<Key> {
// 字符键不需要映射为 egui::Key —— 文本输入走 WM_CHAR -> Event::Text。
Some(match vk {
VK_LEFT => Key::ArrowLeft,
VK_UP => Key::ArrowUp,
VK_RIGHT => Key::ArrowRight,
VK_DOWN => Key::ArrowDown,
VK_BACK => Key::Backspace,
VK_DELETE => Key::Delete,
VK_RETURN => Key::Enter,
VK_TAB => Key::Tab,
VK_ESCAPE => Key::Escape,
VK_SPACE => Key::Space,
_ => return None,
})
}
fn on_key(vk: usize, pressed: bool) -> LRESULT {
unsafe {
match vk {
VK_SHIFT => MOD_SHIFT = pressed,
VK_CONTROL => MOD_CTRL = pressed,
VK_MENU => MOD_ALT = pressed,
_ => {}
}
if let Some(key) = vk_to_egui_key(vk) {
EVENTS.push(Event::Key {
key,
physical_key: None,
pressed,
repeat: false,
modifiers: current_modifiers(),
});
}
}
0
}
extern "system" fn wnd_proc(hwnd: HWND, msg: u32, w: WPARAM, l: LPARAM) -> LRESULT {
unsafe {
match msg {
WM_CLOSE | WM_DESTROY => {
QUIT = true;
PostQuitMessage(0);
0
}
WM_MOUSEMOVE => {
POINTER = Pos2::new(lparam_x(l) as f32, lparam_y(l) as f32);
EVENTS.push(Event::PointerMoved(POINTER));
0
}
WM_LBUTTONDOWN => push_pointer_button(PointerButton::Primary, true, l),
WM_LBUTTONUP => push_pointer_button(PointerButton::Primary, false, l),
WM_RBUTTONDOWN => push_pointer_button(PointerButton::Secondary, true, l),
WM_RBUTTONUP => push_pointer_button(PointerButton::Secondary, false, l),
WM_MBUTTONDOWN => push_pointer_button(PointerButton::Middle, true, l),
WM_MBUTTONUP => push_pointer_button(PointerButton::Middle, false, l),
WM_KEYDOWN => on_key(w, true),
WM_KEYUP => on_key(w, false),
WM_CHAR => {
if let Some(c) = char::from_u32(w as u32) {
if c >= ' ' && c != '\x7f' {
EVENTS.push(Event::Text(c.to_string()));
}
}
0
}
WM_ERASEBKGND => 1, // 背景由 egui 全量绘制
_ => DefWindowProcW(hwnd, msg, w, l),
}
}
}
/* ============================================================
* 计时
* ========================================================== */
fn now_secs() -> f64 {
unsafe {
static mut FREQ: i64 = 0;
if FREQ == 0 {
QueryPerformanceFrequency(&mut FREQ);
if FREQ == 0 {
FREQ = 1000;
}
}
let mut c: i64 = 0;
QueryPerformanceCounter(&mut c);
c as f64 / FREQ as f64
}
}
/* ============================================================
* PE 入口
* ========================================================== */
/// ExitProcess wrapper: restore the kernel GS base before leaving.
fn exit_process(code: u32) -> ! {
unsafe {
rt::restore_tls();
ExitProcess(code);
}
}
#[no_mangle]
pub extern "C" fn mainCRTStartup() {
unsafe {
// Fake TEB/TLS must precede any std facility that might touch
// thread locals (parking_lot, std::io, etc.).
rt::install_fake_tls();
}
log("[deaicup] mainCRTStartup\n");
unsafe {
let hinst = GetModuleHandleW(core::ptr::null());
let class_name = wide("DeaicupWindow");
let wc = WNDCLASSEXW {
cbSize: core::mem::size_of::<WNDCLASSEXW>() as u32,
style: 0,
lpfnWndProc: wnd_proc,
cbClsExtra: 0,
cbWndExtra: 0,
hInstance: hinst,
hIcon: 0,
hCursor: LoadCursorW(0, IDC_ARROW),
hbrBackground: 0,
lpszMenuName: core::ptr::null(),
lpszClassName: class_name.as_ptr(),
hIconSm: 0,
};
RegisterClassExW(&wc);
// 屏幕尺寸（shim 报 framebuffer 尺寸），窗口 800x600，超出则收缩
let sw = GetSystemMetrics(SM_CXSCREEN);
let sh = GetSystemMetrics(SM_CYSCREEN);
let mut ww = 800;
let mut wh = 600;
if sw > 0 && ww > sw {
ww = sw;
}
if sh > 0 && wh > sh {
wh = sh;
}
let title = wide("Deaicup Software");
let hwnd = CreateWindowExW(
0,
class_name.as_ptr(),
title.as_ptr(),
WS_OVERLAPPEDWINDOW | WS_VISIBLE,
CW_USEDEFAULT,
CW_USEDEFAULT,
ww,
wh,
0,
0,
hinst,
core::ptr::null_mut(),
);
if hwnd == 0 {
log("[deaicup] CreateWindowExW failed\n");
exit_process(1);
}
ShowWindow(hwnd, SW_SHOW);
UpdateWindow(hwnd);
// 32bpp top-down DIB 后台缓冲
let hdc = GetDC(hwnd);
let memdc = CreateCompatibleDC(hdc);
let mut bmi = BITMAPINFO::default();
bmi.bmiHeader.biSize = core::mem::size_of::<BITMAPINFOHEADER>() as u32;
bmi.bmiHeader.biWidth = ww;
bmi.bmiHeader.biHeight = -wh; // top-down
bmi.bmiHeader.biPlanes = 1;
bmi.bmiHeader.biBitCount = 32;
bmi.bmiHeader.biCompression = BI_RGB;
let mut bits: *mut core::ffi::c_void = core::ptr::null_mut();
let hbmp = CreateDIBSection(memdc, &bmi, DIB_RGB_COLORS, &mut bits, 0, 0);
if hbmp == 0 || bits.is_null() {
log("[deaicup] CreateDIBSection failed\n");
exit_process(1);
}
SelectObject(memdc, hbmp);
log("[dc] SelectObject ok\n");
/* 二分探针：逐项验证 std 设施，定位 Context::default 崩溃点 */
{
let mut v: Vec<u8> = Vec::with_capacity(16);
for i in 0..64u8 { v.push(i); }
log("[dc] vec ok\n");
let s = String::from("hello");
let _ = s.len();
log("[dc] string ok\n");
let mut h: std::collections::HashMap<u32, u32> = std::collections::HashMap::new();
h.insert(1, 2); h.insert(3, 4);
let _ = h.get(&1);
log("[dc] hashmap ok\n");
let a = std::sync::Arc::new(42u32);
let b = a.clone();
let _ = *b;
log("[dc] arc ok\n");
let m = std::sync::Mutex::new(7u32);
*m.lock().unwrap() = 8;
log("[dc] mutex ok\n");
}
let ctx = Context::default();
log("[dc] Context::default ok\n");
ctx.set_pixels_per_point(1.0);
let mut app = DeaicupSoftware::default();
let mut raster = SoftRaster::new();
let mut msg = MSG::default();
let mut frame: u64 = 0;
log("[dc] app+raster ok\n");
while !QUIT {
// 消息泵：把 Win32 消息转成 egui 事件（由 wnd_proc 推入 EVENTS）
while PeekMessageW(&mut msg, 0, 0, 0, PM_REMOVE) != 0 {
if msg.message == WM_QUIT {
QUIT = true;
break;
}
TranslateMessage(&msg);
DispatchMessageW(&msg);
}
if QUIT {
break;
}
if frame < 3 { log("[dc] msgpump ok\n"); }
let events = core::mem::take(&mut *core::ptr::addr_of_mut!(EVENTS));
let had_events = !events.is_empty();
let input = egui::RawInput {
screen_rect: Some(Rect::from_min_size(
Pos2::ZERO,
egui::vec2(ww as f32, wh as f32),
)),
time: Some(now_secs()),
modifiers: current_modifiers(),
events,
..Default::default()
};
if frame < 3 { log("[dc] rawinput ok\n"); }
let full = ctx.run(input, |ctx| app.ui(&ctx));
if frame < 3 { log("[dc] ctx.run ok\n"); }
let repaint_after = full
.viewport_output
.values()
.next()
.map(|v| v.repaint_delay)
.unwrap_or(std::time::Duration::from_millis(16));
raster.apply_delta(&full.textures_delta);
if frame < 3 { log("[dc] apply_delta ok\n"); }
let prims = ctx.tessellate(full.shapes, full.pixels_per_point);
if frame < 3 { log("[dc] tessellate ok\n"); }
let dst = core::slice::from_raw_parts_mut(bits as *mut u32, (ww * wh) as usize);
raster::clear(dst, Color32::from_rgb(0x30, 0x34, 0x3d));
raster.paint(dst, ww, wh, &prims);
if frame < 3 { log("[dc] paint ok\n"); }
BitBlt(hdc, 0, 0, ww, wh, memdc, 0, 0, SRCCOPY);
if frame < 3 { log("[dc] bitblt ok\n"); }
frame += 1;
if frame > 2 && !had_events && repaint_after > std::time::Duration::from_millis(5) {
let ms = repaint_after.as_millis().min(50) as u32;
Sleep(if ms == 0 { 5 } else { ms });
}
}
log("[deaicup] quit, ExitProcess(0)\n");
exit_process(0);
}
}
CODE/Deaicup Software/pe/src/raster.rs
+235
View File
@@ -0,0 +1,235 @@
//! Pure-Rust software rasterizer for egui tessellated primitives.
//! Renders `ClippedPrimitive` meshes (font atlas + color triangles) into a
//! 32bpp 0xAARRGGBB backbuffer that is later blitted via GDI BitBlt.
use egui::epaint::Primitive;
use egui::{ClippedPrimitive, Color32, Rect, TextureFilter, TextureId, TexturesDelta};
struct Texture {
w: usize,
h: usize,
/// RGBA8, row-major.
rgba: Vec<u8>,
linear: bool,
}
pub struct SoftRaster {
/// Small texture store (font atlas + user images). Vec-based to avoid
/// std HashMap RandomState (which would import an OS RNG API).
textures: Vec<(TextureId, Texture)>,
}
impl SoftRaster {
pub fn new() -> Self {
SoftRaster {
textures: Vec::new(),
}
}
fn get(&self, id: TextureId) -> Option<&Texture> {
self.textures.iter().find(|(tid, _)| *tid == id).map(|(_, t)| t)
}
/// Apply egui's texture updates (font atlas etc).
pub fn apply_delta(&mut self, delta: &TexturesDelta) {
for (id, img_delta) in &delta.set {
let size = img_delta.image.size();
let mut rgba = Vec::with_capacity(size[0] * size[1] * 4);
match &img_delta.image {
egui::ImageData::Color(color) => {
for p in &color.pixels {
rgba.extend_from_slice(&p.to_array());
}
}
egui::ImageData::Font(font) => {
// Coverage -> straight-alpha white texel (255,255,255,a).
for c in font.srgba_pixels(None) {
let a = c.a();
rgba.extend_from_slice(&[255, 255, 255, a]);
}
}
}
let linear = img_delta.options.magnification == TextureFilter::Linear;
let tex = Texture {
w: size[0],
h: size[1],
rgba,
linear,
};
if let Some(slot) = self.textures.iter_mut().find(|(tid, _)| tid == id) {
slot.1 = tex;
} else {
self.textures.push((*id, tex));
}
}
for id in &delta.free {
self.textures.retain(|(tid, _)| tid != id);
}
}
/// Paint all clipped primitives into `dst` (0xAARRGGBB pixels, dw*dh).
pub fn paint(&self, dst: &mut [u32], dw: i32, dh: i32, prims: &[ClippedPrimitive]) {
for cp in prims {
if let Primitive::Mesh(mesh) = &cp.primitive {
let Some(tex) = self.get(mesh.texture_id) else {
continue;
};
let clip = clip_rect_px(&cp.clip_rect, dw, dh);
if clip.2 <= clip.0 || clip.3 <= clip.1 {
continue;
}
for tri in mesh.indices.chunks_exact(3) {
let v0 = &mesh.vertices[tri[0] as usize];
let v1 = &mesh.vertices[tri[1] as usize];
let v2 = &mesh.vertices[tri[2] as usize];
raster_tri(dst, dw, dh, clip, v0, v1, v2, tex);
}
}
}
}
}
/// (x0, y0, x1, y1) integer clip bounds from an egui rect (points == pixels here).
fn clip_rect_px(r: &Rect, dw: i32, dh: i32) -> (i32, i32, i32, i32) {
let x0 = (r.min.x.floor() as i32).clamp(0, dw);
let y0 = (r.min.y.floor() as i32).clamp(0, dh);
let x1 = (r.max.x.ceil() as i32).clamp(0, dw);
let y1 = (r.max.y.ceil() as i32).clamp(0, dh);
(x0, y0, x1, y1)
}
#[inline]
fn edge(ax: f32, ay: f32, bx: f32, by: f32, px: f32, py: f32) -> f32 {
(px - ax) * (by - ay) - (py - ay) * (bx - ax)
}
fn raster_tri(
dst: &mut [u32],
dw: i32,
_dh: i32,
clip: (i32, i32, i32, i32),
v0: &egui::epaint::Vertex,
v1: &egui::epaint::Vertex,
v2: &egui::epaint::Vertex,
tex: &Texture,
) {
let x0 = v0.pos.x;
let y0 = v0.pos.y;
let x1 = v1.pos.x;
let y1 = v1.pos.y;
let x2 = v2.pos.x;
let y2 = v2.pos.y;
let area = edge(x0, y0, x1, y1, x2, y2);
if area.abs() < 1e-6 {
return;
}
let inv_area = 1.0 / area;
let min_x = ((x0.min(x1).min(x2)).floor() as i32).max(clip.0);
let min_y = ((y0.min(y1).min(y2)).floor() as i32).max(clip.1);
let max_x = ((x0.max(x1).max(x2)).ceil() as i32).min(clip.2);
let max_y = ((y0.max(y1).max(y2)).ceil() as i32).min(clip.3);
if min_x >= max_x || min_y >= max_y {
return;
}
for py in min_y..max_y {
let fy = py as f32 + 0.5;
let mut px = min_x;
// Row start barycentrics
let mut w0 = edge(x1, y1, x2, y2, px as f32 + 0.5, fy) * inv_area;
let mut w1 = edge(x2, y2, x0, y0, px as f32 + 0.5, fy) * inv_area;
let mut w2 = 1.0 - w0 - w1;
// Per-pixel increments (dx = +1)
let dw0 = (y1 - y2) * inv_area;
let dw1 = (y2 - y0) * inv_area;
while px < max_x {
if w0 >= 0.0 && w1 >= 0.0 && w2 >= 0.0 {
let u = w0 * v0.uv.x + w1 * v1.uv.x + w2 * v2.uv.x;
let v = w0 * v0.uv.y + w1 * v1.uv.y + w2 * v2.uv.y;
let t = sample(tex, u, v);
let c0 = v0.color;
let c1 = v1.color;
let c2 = v2.color;
let cr = (w0 * c0.r() as f32 + w1 * c1.r() as f32 + w2 * c2.r() as f32) as u32;
let cg = (w0 * c0.g() as f32 + w1 * c1.g() as f32 + w2 * c2.g() as f32) as u32;
let cb = (w0 * c0.b() as f32 + w1 * c1.b() as f32 + w2 * c2.b() as f32) as u32;
let ca = (w0 * c0.a() as f32 + w1 * c1.a() as f32 + w2 * c2.a() as f32) as u32;
// src color = vertex * texture (straight), alpha = va * ta
let sa = (ca * t[3] as u32 + 127) / 255;
if sa != 0 {
let sr = (cr * t[0] as u32 + 127) / 255;
let sg = (cg * t[1] as u32 + 127) / 255;
let sb = (cb * t[2] as u32 + 127) / 255;
let idx = (py * dw + px) as usize;
let d = dst[idx];
let dr = (d >> 16) & 0xFF;
let dg = (d >> 8) & 0xFF;
let db = d & 0xFF;
let inv = 255 - sa;
let or = (sr * sa + dr * inv + 127) / 255;
let og = (sg * sa + dg * inv + 127) / 255;
let ob = (sb * sa + db * inv + 127) / 255;
dst[idx] = 0xFF00_0000 | (or << 16) | (og << 8) | ob;
}
}
px += 1;
w0 += dw0;
w1 += dw1;
w2 = 1.0 - w0 - w1;
}
}
}
#[inline]
fn sample(tex: &Texture, u: f32, v: f32) -> [u8; 4] {
if tex.linear {
sample_linear(tex, u, v)
} else {
sample_nearest(tex, u, v)
}
}
#[inline]
fn sample_nearest(tex: &Texture, u: f32, v: f32) -> [u8; 4] {
let x = (u * tex.w as f32 - 0.5).round() as i32;
let y = (v * tex.h as f32 - 0.5).round() as i32;
texel(tex, x, y)
}
fn sample_linear(tex: &Texture, u: f32, v: f32) -> [u8; 4] {
let fx = u * tex.w as f32 - 0.5;
let fy = v * tex.h as f32 - 0.5;
let x0 = fx.floor() as i32;
let y0 = fy.floor() as i32;
let tx = ((fx - x0 as f32) * 256.0) as i32;
let ty = ((fy - y0 as f32) * 256.0) as i32;
let p00 = texel(tex, x0, y0);
let p10 = texel(tex, x0 + 1, y0);
let p01 = texel(tex, x0, y0 + 1);
let p11 = texel(tex, x0 + 1, y0 + 1);
let mut out = [0u8; 4];
for i in 0..4 {
let top = (p00[i] as i32 * (256 - tx) + p10[i] as i32 * tx) >> 8;
let bot = (p01[i] as i32 * (256 - tx) + p11[i] as i32 * tx) >> 8;
out[i] = ((top * (256 - ty) + bot * ty) >> 8) as u8;
}
out
}
#[inline]
fn texel(tex: &Texture, x: i32, y: i32) -> [u8; 4] {
let x = x.clamp(0, tex.w as i32 - 1) as usize;
let y = y.clamp(0, tex.h as i32 - 1) as usize;
let i = (y * tex.w + x) * 4;
[tex.rgba[i], tex.rgba[i + 1], tex.rgba[i + 2], tex.rgba[i + 3]]
}
/// Clear the whole backbuffer to an opaque color.
pub fn clear(dst: &mut [u32], c: Color32) {
let px = 0xFF00_0000 | ((c.r() as u32) << 16) | ((c.g() as u32) << 8) | c.b() as u32;
dst.fill(px);
}
CODE/Deaicup Software/pe/src/rt.rs
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@@ -0,0 +1,600 @@
//! Minimal CRT / libm runtime for the no-CRT PE64 build.
//!
//! The UTSM PE shim only resolves DLL imports (kernel32/user32/gdi32).
//! Symbols below are *link-time* references emitted by LLVM/std, so they must
//! live inside the PE image itself:
//! - string intrinsics: memcpy / memmove / memset / memcmp
//! - MSVC runtime: __chkstk, _fltused, _tls_index, _tls_used,
//! __CxxFrameHandler3 (never called, panic = abort)
//! - f32 libm: floorf/ceilf/roundf, sinf/cosf, atan2f, powf,
//! exp2f, acosf, cbrtf, _hypotf
//!
//! Math routines are ported from musl-libm (MIT) where accuracy matters
//! (sin/cos/atan) and use simple polynomial/series elsewhere. Visual use by
//! egui only needs ~1e-5 relative accuracy.
//!
//! TLS: Rust std on windows-msvc checks `_tls_used` and (if nonzero) accesses
//! thread locals through gs:[0x58] -> slots[_tls_index]. We are Ring0 with no
//! TEB, so mainCRTStartup installs a fake GS base pointing at a zeroed TLS
//! block (install_fake_tls) and restores it before ExitProcess.
#![allow(non_snake_case)]
use core::arch::asm;
/* ============================================================
* string intrinsics
* ========================================================== */
/// # Safety
/// Standard C contract.
#[no_mangle]
pub unsafe extern "C" fn memcpy(dst: *mut u8, src: *const u8, n: usize) -> *mut u8 {
let orig = dst;
asm!(
"rep movsb",
inout("rcx") n => _,
inout("rsi") src => _,
inout("rdi") dst => _,
options(nostack, preserves_flags)
);
orig
}
/// # Safety
/// Standard C contract.
#[no_mangle]
pub unsafe extern "C" fn memmove(dst: *mut u8, src: *const u8, n: usize) -> *mut u8 {
let d = dst as usize;
let s = src as usize;
if d < s || d >= s.wrapping_add(n) {
memcpy(dst, src, n)
} else {
// Backward copy without touching DF (ABI requires DF=0).
let mut i = n;
while i > 0 {
i -= 1;
core::ptr::write_volatile(dst.add(i), core::ptr::read_volatile(src.add(i)));
}
dst
}
}
/// # Safety
/// Standard C contract.
#[no_mangle]
pub unsafe extern "C" fn memset(dst: *mut u8, val: i32, n: usize) -> *mut u8 {
let orig = dst;
asm!(
"rep stosb",
inout("rcx") n => _,
inout("rdi") dst => _,
in("al") val as u8,
options(nostack, preserves_flags)
);
orig
}
/// # Safety
/// Standard C contract.
#[no_mangle]
pub unsafe extern "C" fn memcmp(a: *const u8, b: *const u8, n: usize) -> i32 {
// Volatile reads keep LLVM from idiom-recognizing this back into memcmp.
for i in 0..n {
let x = core::ptr::read_volatile(a.add(i));
let y = core::ptr::read_volatile(b.add(i));
if x != y {
return x as i32 - y as i32;
}
}
0
}
/* ============================================================
* MSVC runtime bits
* ========================================================== */
/// Stack probe. Our stack is one large committed region (see /STACK flag),
/// so probing pages is unnecessary. An empty body compiles to `ret`,
/// which trivially satisfies the preserve-everything contract.
#[no_mangle]
pub extern "C" fn __chkstk() {}
/// Referenced by std's unwind tables (.pdata personality). With
/// panic = "abort" it is never invoked; loop loudly if it ever is.
#[no_mangle]
pub extern "C" fn __CxxFrameHandler3() -> ! {
loop {
core::hint::spin_loop();
}
}
/// CRT float-usage marker (data symbol only).
#[no_mangle]
pub static _fltused: i32 = 0x9875;
/// TLS slot index of this module. We use slot 0 of the fake TLS array.
#[no_mangle]
pub static _tls_index: u32 = 0;
/// IMAGE_TLS_DIRECTORY64 stand-in (all zeros: no raw template, no callbacks).
/// std only checks that its address is nonzero to decide TLS is supported.
#[no_mangle]
pub static _tls_used: [u8; 0x30] = [0; 0x30];
/* ---- fake TEB / TLS so std thread_local access can't fault ---- */
const IA32_GS_BASE: u32 = 0xC000_0101;
static mut OLD_GS_BASE: u64 = 0;
static mut TLS_READY: bool = false;
fn rdmsr(msr: u32) -> u64 {
let lo: u32;
let hi: u32;
unsafe {
asm!("rdmsr", in("ecx") msr, out("eax") lo, out("edx") hi,
options(nomem, nostack, preserves_flags));
}
((hi as u64) << 32) | lo as u64
}
fn wrmsr(msr: u32, val: u64) {
unsafe {
asm!("wrmsr", in("ecx") msr, in("eax") val as u32,
in("edx") (val >> 32) as u32, options(nomem, nostack, preserves_flags));
}
}
/// Point GS at a minimal fake TEB whose ThreadLocalStoragePointer (0x58)
/// references a zeroed slots array; slot 0 covers `_tls_index == 0`.
/// All const-init thread locals in std are zero-valid (None/0).
///
/// # Safety
/// Ring0 only; call once at PE entry before touching std facilities.
pub unsafe fn install_fake_tls() {
static mut TEB: [u8; 0x100] = [0; 0x100];
static mut SLOTS: [usize; 64] = [0; 64];
static mut TLS_BLOCK: [u8; 8192] = [0; 8192];
if TLS_READY {
return;
}
let teb = core::ptr::addr_of_mut!(TEB);
let slots = core::ptr::addr_of_mut!(SLOTS);
let block = core::ptr::addr_of_mut!(TLS_BLOCK);
(*slots)[0] = block as usize;
*((*teb).as_mut_ptr().add(0x58) as *mut usize) = slots as usize;
OLD_GS_BASE = rdmsr(IA32_GS_BASE);
wrmsr(IA32_GS_BASE, teb as u64);
TLS_READY = true;
}
/// Restore the kernel's GS base (call before ExitProcess).
///
/// # Safety
/// Ring0 only; pair with install_fake_tls.
pub unsafe fn restore_tls() {
if TLS_READY {
wrmsr(IA32_GS_BASE, OLD_GS_BASE);
TLS_READY = false;
}
}
/* ============================================================
* f32 libm
* ========================================================== */
#[inline(always)]
fn asu32(x: f32) -> u32 {
x.to_bits()
}
#[inline(always)]
fn asf32(x: u32) -> f32 {
f32::from_bits(x)
}
#[no_mangle]
pub extern "C" fn floorf(x: f32) -> f32 {
// |x| >= 2^23 is already integral; NaN passes the compare false and
// degrades to 0.0, which egui never feeds us anyway.
if x.abs() >= 8388608.0 {
return x;
}
let i = x as i32; // truncate toward zero
let f = i as f32;
if f > x {
f - 1.0
} else {
f
}
}
#[no_mangle]
pub extern "C" fn ceilf(x: f32) -> f32 {
if x.abs() >= 8388608.0 {
return x;
}
let i = x as i32;
let f = i as f32;
if f < x {
f + 1.0
} else {
f
}
}
/// C semantics: round half away from zero.
#[no_mangle]
pub extern "C" fn roundf(x: f32) -> f32 {
if x >= 0.0 {
floorf(x + 0.5)
} else {
ceilf(x - 0.5)
}
}
#[no_mangle]
pub extern "C" fn truncf(x: f32) -> f32 {
if x.abs() >= 8388608.0 {
return x;
}
x as i32 as f32
}
/// f64 truncation toward zero (LLVM libcall on SSE2-only targets).
#[no_mangle]
pub extern "C" fn trunc(x: f64) -> f64 {
// 2^52: every f64 with |x| >= 2^52 is already integral.
if x.abs() >= 4503599627370496.0 {
return x;
}
x as i64 as f64
}
/* ---- sin/cos: musl __sindf/__cosdf + medium Cody-Waite reduction ---- */
// |sin(x)/x - s(x)| < 2**-27.5 on the reduced range.
const S1: f64 = -0.166666666416265235595;
const S2: f64 = 0.0083333293858894631756;
const S3: f64 = -0.000198393348360966317347;
const S4: f64 = 0.0000027183114939898219064;
const C0: f64 = -0.499999997251031003120;
const C1: f64 = 0.0416666233237390631894;
const C2: f64 = -0.00138867637746099294692;
const C3: f64 = 0.0000243904487962774090654;
const PIO2_HI: f64 = 1.57079625129699707031e+00;
const PIO2_LO: f64 = 7.54978941586159635335e-08;
const INV_PIO2: f64 = 6.36619772367581382433e-01; // 2/pi
const TOINT: f64 = 1.5 / f64::EPSILON;
const TWO_PI: f64 = 6.28318530717958647693;
#[inline]
fn sindf(x: f64) -> f64 {
let z = x * x;
let w = z * z;
let r = S3 + z * S4;
let s = z * x;
(x + s * (S1 + z * S2)) + s * w * r
}
#[inline]
fn cosdf(x: f64) -> f64 {
let z = x * x;
let w = z * z;
let r = C2 + z * C3;
((1.0 + z * C0) + w * C1) + (w * z) * r
}
/// Reduce x modulo pi/2 (Cody-Waite, double precision). Returns (n, y)
/// with y = x - n*pi/2 accurate for moderate |x|.
#[inline]
fn rem_pio2_medium(x: f64) -> (i32, f64) {
// Coarse pre-reduction keeps the accurate path valid for any angle egui
// can produce (ellipse/bezier angles are already tiny).
let x = if x.abs() > 105.0 {
x - (x / TWO_PI).trunc() * TWO_PI
} else {
x
};
let fn_ = x * INV_PIO2 + TOINT - TOINT;
let n = fn_ as i32;
(n, x - fn_ * PIO2_HI - fn_ * PIO2_LO)
}
#[no_mangle]
pub extern "C" fn sinf(x: f32) -> f32 {
if x.abs() < 1.0e-30 {
return x;
}
let (n, y) = rem_pio2_medium(x as f64);
(match n & 3 {
0 => sindf(y),
1 => cosdf(y),
2 => sindf(-y),
_ => -cosdf(y),
}) as f32
}
#[no_mangle]
pub extern "C" fn cosf(x: f32) -> f32 {
let (n, y) = rem_pio2_medium(x as f64);
(match n & 3 {
0 => cosdf(y),
1 => sindf(-y),
2 => -cosdf(y),
_ => sindf(y),
}) as f32
}
/* ---- atan2f: musl atanf + quadrant fix ---- */
const ATAN_HI: [f32; 4] = [
4.6364760399e-01,
7.8539812565e-01,
9.8279371262e-01,
1.5707962513e+00,
];
const ATAN_LO: [f32; 4] = [
8.8023035407e-08,
1.2093354704e-08,
1.2587686365e-08,
7.5497894159e-08,
];
const AT: [f32; 5] = [
3.3333328366e-01,
-1.9999158382e-01,
1.4253635705e-01,
-1.0648017377e-01,
6.1687607318e-02,
];
const PI_F: f32 = 3.1415927410e+00;
fn atanf(x: f32) -> f32 {
let mut x = x;
let ix = asu32(x);
let sign = ix >> 31;
let aix = ix & 0x7fffffff;
if aix >= 0x4c800000 {
// |x| >= 2^26
if x.is_nan() {
return x;
}
let z = ATAN_HI[3] + 7.5231638e-37;
return if sign != 0 { -z } else { z };
}
let id: i32;
if aix < 0x3ee00000 {
// |x| < 0.4375
if aix < 0x39800000 {
return x; // |x| < 2^-12: atan(x) ~ x
}
id = -1;
} else {
x = x.abs();
if aix < 0x3f980000 {
if aix < 0x3f300000 {
id = 0;
x = (2.0 * x - 1.0) / (2.0 + x);
} else {
id = 1;
x = (x - 1.0) / (x + 1.0);
}
} else if aix < 0x401c0000 {
id = 2;
x = (x - 1.5) / (1.0 + 1.5 * x);
} else {
id = 3;
x = -1.0 / x;
}
}
let z = x * x;
let w = z * z;
let s1 = z * (AT[0] + w * (AT[2] + w * AT[4]));
let s2 = w * (AT[1] + w * AT[3]);
if id < 0 {
return x - x * (s1 + s2);
}
let i = id as usize;
let z2 = ATAN_HI[i] - ((x * (s1 + s2) - ATAN_LO[i]) - x);
if sign != 0 {
-z2
} else {
z2
}
}
#[no_mangle]
pub extern "C" fn atan2f(y: f32, x: f32) -> f32 {
if y == 0.0 {
return if x < 0.0 { PI_F } else { y }; // crude, matches C for our uses
}
if x == 0.0 {
return if y < 0.0 { -PI_F / 2.0 } else { PI_F / 2.0 };
}
let ax = x.abs();
let ay = y.abs();
let z = if ax > ay {
atanf(ay / ax)
} else {
PI_F / 2.0 - atanf(ax / ay)
};
if x < 0.0 {
if y < 0.0 {
z - PI_F
} else {
PI_F - z
}
} else if y < 0.0 {
-z
} else {
z
}
}
/* ---- exp2f / log2f / powf ---- */
/// ldexp-style scaling by 2^n (n clamped to f32 range by callers).
fn scalbnf(mut r: f32, mut n: i32) -> f32 {
while n > 127 {
r *= asf32(0x7F00_0000); // 2^127
n -= 127;
}
while n < -126 {
r *= asf32(0x0080_0000); // 2^-126
n += 126;
}
r * asf32(((127 + n) as u32) << 23)
}
#[no_mangle]
pub extern "C" fn exp2f(x: f32) -> f32 {
if x > 128.0 {
return f32::INFINITY;
}
if x < -150.0 {
return 0.0;
}
// n = round-to-nearest-even(x) via the magic-number trick.
let t = x + 12582912.0; // 1.5 * 2^23
let nf = t - 12582912.0;
let n = nf as i32;
let f = x - nf; // in [-0.5, 0.5]
// 2^f: Taylor in ln2, degree 6 -> ~1e-10 rel error on [-0.5, 0.5].
let p = 1.0
+ f * (0.6931471805599453
+ f * (0.24022650695910070
+ f * (0.05550410866482158
+ f * (0.009618129107628477
+ f * (0.0013333558146428443 + f * 0.00015403530393381609)))));
scalbnf(p, n)
}
/// log2(x) for x > 0; accuracy ~1e-7 via atanh series in double.
fn log2f(x: f32) -> f32 {
let ix = asu32(x);
let e = ((ix >> 23) as i32) - 127;
let m = asf32((ix & 0x007F_FFFF) | 0x3F80_0000); // [1, 2)
let t = ((m - 1.0) / (m + 1.0)) as f64;
let t2 = t * t;
let mut sum = 0.0f64;
let mut term = t;
for k in 0..8 {
sum += term / (2 * k + 1) as f64;
term *= t2;
}
let ln_m = 2.0 * sum;
(e as f64 + ln_m * 1.4426950408889634) as f32
}
#[no_mangle]
pub extern "C" fn powf(x: f32, y: f32) -> f32 {
if y == 0.0 {
return 1.0;
}
if x == 1.0 {
return 1.0;
}
if x == 0.0 {
return 0.0;
}
if x == 2.0 {
return exp2f(y);
}
if x < 0.0 {
let yi = y as i32;
if yi as f32 == y {
let r = exp2f(y * log2f(-x));
return if yi & 1 != 0 { -r } else { r };
}
return f32::NAN;
}
exp2f(y * log2f(x))
}
/* ---- acosf: musl ---- */
const PIO2_HI_F: f32 = 1.5707962513e+00;
const PIO2_LO_F: f32 = 7.5497894159e-08;
const PS0: f32 = 1.6666586697e-01;
const PS1: f32 = -4.2743422091e-02;
const PS2: f32 = -8.6563630030e-03;
const QS1: f32 = -7.0662963390e-01;
#[inline]
fn acos_r(z: f32) -> f32 {
z * (PS0 + z * (PS1 + z * PS2)) / (1.0 + z * QS1)
}
#[no_mangle]
pub extern "C" fn acosf(x: f32) -> f32 {
let hx = asu32(x);
let ix = hx & 0x7fffffff;
if ix >= 0x3f800000 {
// |x| >= 1
if ix == 0x3f800000 {
if hx >> 31 != 0 {
return 2.0 * PIO2_HI_F; // acos(-1) = pi
}
return 0.0; // acos(1) = 0
}
return f32::NAN;
}
if ix < 0x3f000000 {
// |x| < 0.5
if ix <= 0x32800000 {
return PIO2_HI_F; // |x| < 2^-26
}
return PIO2_HI_F - (x - (PIO2_LO_F - x * acos_r(x * x)));
}
if hx >> 31 != 0 {
// x < -0.5
let z = (1.0 + x) * 0.5;
let s = z.sqrt();
let w = acos_r(z) * s - PIO2_LO_F;
return 2.0 * PIO2_HI_F - 2.0 * (s + w);
}
// x > 0.5
let z = (1.0 - x) * 0.5;
let s = z.sqrt();
let df = asf32(asu32(s) & 0xFFFFF000); // keep df*df rounding-exact
let c = (z - df * df) / (s + df);
let w = acos_r(z) * s + c;
2.0 * (df + w)
}
/* ---- cbrtf / hypotf ---- */
#[no_mangle]
pub extern "C" fn cbrtf(x: f32) -> f32 {
if x == 0.0 {
return x;
}
let r = exp2f(log2f(x.abs()) / 3.0);
if x < 0.0 {
-r
} else {
r
}
}
#[no_mangle]
pub extern "C" fn _hypotf(x: f32, y: f32) -> f32 {
let ax = x.abs();
let ay = y.abs();
let (a, b) = if ax > ay { (ax, ay) } else { (ay, ax) };
if a == 0.0 {
return 0.0;
}
let r = b / a;
a * (1.0 + r * r).sqrt()
}
/// Plain alias in case LLVM references the C99 spelling.
#[no_mangle]
pub extern "C" fn hypotf(x: f32, y: f32) -> f32 {
_hypotf(x, y)
}
CODE/Deaicup Software/pe/src/win32.rs
+315
View File
@@ -0,0 +1,315 @@
//! Minimal Win32 bindings used by the Deaicup PE backend.
//! Only the API subset that the Deshab UTSM PE shim implements is declared here.
//! All imports use raw-dylib so rust-lld can emit the import table without
//! any MSVC import libraries.
#![allow(non_snake_case, non_camel_case_types, dead_code)]
pub type HWND = isize;
pub type HDC = isize;
pub type HINSTANCE = isize;
pub type HICON = isize;
pub type HCURSOR = isize;
pub type HBRUSH = isize;
pub type HMENU = isize;
pub type HGDIOBJ = isize;
pub type HBITMAP = isize;
pub type HANDLE = isize;
pub type ATOM = u16;
pub type WPARAM = usize;
pub type LPARAM = isize;
pub type LRESULT = isize;
pub type BOOL = i32;
pub type UINT = u32;
pub type DWORD = u32;
pub type WORD = u16;
pub type LPCWSTR = *const u16;
pub const CW_USEDEFAULT: i32 = 0x80000000u32 as i32;
pub const WS_OVERLAPPED: u32 = 0x00000000;
pub const WS_CAPTION: u32 = 0x00C00000;
pub const WS_SYSMENU: u32 = 0x00080000;
pub const WS_THICKFRAME: u32 = 0x00040000;
pub const WS_MINIMIZEBOX: u32 = 0x00020000;
pub const WS_MAXIMIZEBOX: u32 = 0x00010000;
pub const WS_VISIBLE: u32 = 0x10000000;
pub const WS_OVERLAPPEDWINDOW: u32 = WS_OVERLAPPED
| WS_CAPTION
| WS_SYSMENU
| WS_THICKFRAME
| WS_MINIMIZEBOX
| WS_MAXIMIZEBOX;
pub const SW_SHOW: i32 = 5;
pub const WM_CREATE: u32 = 0x0001;
pub const WM_DESTROY: u32 = 0x0002;
pub const WM_SIZE: u32 = 0x0005;
pub const WM_PAINT: u32 = 0x000F;
pub const WM_CLOSE: u32 = 0x0010;
pub const WM_QUIT: u32 = 0x0012;
pub const WM_ERASEBKGND: u32 = 0x0014;
pub const WM_KEYDOWN: u32 = 0x0100;
pub const WM_KEYUP: u32 = 0x0101;
pub const WM_CHAR: u32 = 0x0102;
pub const WM_TIMER: u32 = 0x0113;
pub const WM_MOUSEMOVE: u32 = 0x0200;
pub const WM_LBUTTONDOWN: u32 = 0x0201;
pub const WM_LBUTTONUP: u32 = 0x0202;
pub const WM_RBUTTONDOWN: u32 = 0x0204;
pub const WM_RBUTTONUP: u32 = 0x0205;
pub const WM_MBUTTONDOWN: u32 = 0x0207;
pub const WM_MBUTTONUP: u32 = 0x0208;
pub const PM_NOREMOVE: u32 = 0x0000;
pub const PM_REMOVE: u32 = 0x0001;
pub const VK_BACK: usize = 0x08;
pub const VK_TAB: usize = 0x09;
pub const VK_RETURN: usize = 0x0D;
pub const VK_SHIFT: usize = 0x10;
pub const VK_CONTROL: usize = 0x11;
pub const VK_MENU: usize = 0x12;
pub const VK_ESCAPE: usize = 0x1B;
pub const VK_SPACE: usize = 0x20;
pub const VK_LEFT: usize = 0x25;
pub const VK_UP: usize = 0x26;
pub const VK_RIGHT: usize = 0x27;
pub const VK_DOWN: usize = 0x28;
pub const VK_DELETE: usize = 0x2E;
pub const IDC_ARROW: usize = 32512;
pub const COLOR_WINDOW: u32 = 5;
pub const GWLP_USERDATA: i32 = -21;
pub const GWLP_WNDPROC: i32 = -4;
pub const SM_CXSCREEN: i32 = 0;
pub const SM_CYSCREEN: i32 = 1;
pub const SRCCOPY: u32 = 0x00CC0020;
pub const DIB_RGB_COLORS: u32 = 0;
pub const BI_RGB: u32 = 0;
pub const WHITE_BRUSH: i32 = 0;
pub const STD_OUTPUT_HANDLE: u32 = 0xFFFFFFF5;
pub const STD_ERROR_HANDLE: u32 = 0xFFFFFFF4;
#[repr(C)]
#[derive(Default, Clone, Copy)]
pub struct POINT {
pub x: i32,
pub y: i32,
}
#[repr(C)]
#[derive(Default, Clone, Copy)]
pub struct RECT {
pub left: i32,
pub top: i32,
pub right: i32,
pub bottom: i32,
}
#[repr(C)]
#[derive(Default, Clone, Copy)]
pub struct MSG {
pub hwnd: HWND,
pub message: u32,
pub wParam: WPARAM,
pub lParam: LPARAM,
pub time: u32,
pub pt: POINT,
}
#[repr(C)]
pub struct WNDCLASSEXW {
pub cbSize: UINT,
pub style: UINT,
pub lpfnWndProc: WNDPROC,
pub cbClsExtra: i32,
pub cbWndExtra: i32,
pub hInstance: HINSTANCE,
pub hIcon: HICON,
pub hCursor: HCURSOR,
pub hbrBackground: HBRUSH,
pub lpszMenuName: LPCWSTR,
pub lpszClassName: LPCWSTR,
pub hIconSm: HICON,
}
pub type WNDPROC = extern "system" fn(HWND, u32, WPARAM, LPARAM) -> LRESULT;
#[repr(C)]
pub struct PAINTSTRUCT {
pub hdc: HDC,
pub fErase: BOOL,
pub rcPaint: RECT,
pub fRestore: BOOL,
pub fIncUpdate: BOOL,
pub rgbReserved: [u8; 32],
}
impl Default for PAINTSTRUCT {
fn default() -> Self {
unsafe { core::mem::zeroed() }
}
}
#[repr(C)]
#[derive(Default, Clone, Copy)]
pub struct BITMAPINFOHEADER {
pub biSize: u32,
pub biWidth: i32,
pub biHeight: i32,
pub biPlanes: u16,
pub biBitCount: u16,
pub biCompression: u32,
pub biSizeImage: u32,
pub biXPelsPerMeter: i32,
pub biYPelsPerMeter: i32,
pub biClrUsed: u32,
pub biClrImportant: u32,
}
#[repr(C)]
#[derive(Default, Clone, Copy)]
pub struct RGBQUAD {
pub rgbBlue: u8,
pub rgbGreen: u8,
pub rgbRed: u8,
pub rgbReserved: u8,
}
#[repr(C)]
#[derive(Default, Clone, Copy)]
pub struct BITMAPINFO {
pub bmiHeader: BITMAPINFOHEADER,
pub bmiColors: [RGBQUAD; 1],
}
#[link(name = "user32", kind = "raw-dylib")]
extern "system" {
pub fn RegisterClassExW(lpwcx: *const WNDCLASSEXW) -> ATOM;
pub fn CreateWindowExW(
dwExStyle: DWORD,
lpClassName: LPCWSTR,
lpWindowName: LPCWSTR,
dwStyle: DWORD,
x: i32,
y: i32,
nWidth: i32,
nHeight: i32,
hWndParent: HWND,
hMenu: HMENU,
hInstance: HINSTANCE,
lpParam: *mut core::ffi::c_void,
) -> HWND;
pub fn DestroyWindow(hWnd: HWND) -> BOOL;
pub fn ShowWindow(hWnd: HWND, nCmdShow: i32) -> BOOL;
pub fn UpdateWindow(hWnd: HWND) -> BOOL;
pub fn GetMessageW(lpMsg: *mut MSG, hWnd: HWND, wMsgFilterMin: u32, wMsgFilterMax: u32) -> BOOL;
pub fn PeekMessageW(
lpMsg: *mut MSG,
hWnd: HWND,
wMsgFilterMin: u32,
wMsgFilterMax: u32,
wRemoveMsg: UINT,
) -> BOOL;
pub fn TranslateMessage(lpMsg: *const MSG) -> BOOL;
pub fn DispatchMessageW(lpMsg: *const MSG) -> LRESULT;
pub fn PostQuitMessage(nExitCode: i32);
pub fn DefWindowProcW(hWnd: HWND, msg: u32, wParam: WPARAM, lParam: LPARAM) -> LRESULT;
pub fn GetClientRect(hWnd: HWND, lpRect: *mut RECT) -> BOOL;
pub fn InvalidateRect(hWnd: HWND, lpRect: *const RECT, bErase: BOOL) -> BOOL;
pub fn BeginPaint(hWnd: HWND, lpPaint: *mut PAINTSTRUCT) -> HDC;
pub fn EndPaint(hWnd: HWND, lpPaint: *const PAINTSTRUCT) -> BOOL;
pub fn GetDC(hWnd: HWND) -> HDC;
pub fn ReleaseDC(hWnd: HWND, hDC: HDC) -> i32;
pub fn LoadCursorW(hInstance: HINSTANCE, lpCursorName: usize) -> HCURSOR;
pub fn SetCursor(hCursor: HCURSOR) -> HCURSOR;
pub fn GetCursorPos(lpPoint: *mut POINT) -> BOOL;
pub fn ScreenToClient(hWnd: HWND, lpPoint: *mut POINT) -> BOOL;
pub fn GetAsyncKeyState(vKey: i32) -> i16;
pub fn SetTimer(hWnd: HWND, nIDEvent: usize, uElapse: UINT, lpTimerFunc: usize) -> usize;
pub fn KillTimer(hWnd: HWND, uIDEvent: usize) -> BOOL;
pub fn MessageBeep(uType: UINT) -> BOOL;
pub fn GetSystemMetrics(nIndex: i32) -> i32;
}
#[link(name = "gdi32", kind = "raw-dylib")]
extern "system" {
pub fn CreateCompatibleDC(hdc: HDC) -> HDC;
pub fn CreateDIBSection(
hdc: HDC,
pbmi: *const BITMAPINFO,
usage: UINT,
ppvBits: *mut *mut core::ffi::c_void,
hSection: HANDLE,
offset: DWORD,
) -> HBITMAP;
pub fn SelectObject(hdc: HDC, h: HGDIOBJ) -> HGDIOBJ;
pub fn DeleteObject(ho: HGDIOBJ) -> BOOL;
pub fn DeleteDC(hdc: HDC) -> BOOL;
pub fn BitBlt(
hdc: HDC,
x: i32,
y: i32,
cx: i32,
cy: i32,
hdcSrc: HDC,
x1: i32,
y1: i32,
rop: DWORD,
) -> BOOL;
pub fn GetStockObject(i: i32) -> HGDIOBJ;
pub fn SetDIBitsToDevice(
hdc: HDC,
xDest: i32,
yDest: i32,
w: DWORD,
h: DWORD,
xSrc: i32,
ySrc: i32,
startScan: UINT,
numLines: UINT,
lpvBits: *const core::ffi::c_void,
lpbmi: *const BITMAPINFO,
colorUse: UINT,
) -> i32;
pub fn GdiFlush() -> BOOL;
}
#[link(name = "kernel32", kind = "raw-dylib")]
extern "system" {
pub fn GetModuleHandleW(lpModuleName: LPCWSTR) -> HINSTANCE;
pub fn GetStdHandle(nStdHandle: DWORD) -> HANDLE;
pub fn WriteFile(
hFile: HANDLE,
lpBuffer: *const u8,
nNumberOfBytesToWrite: DWORD,
lpNumberOfBytesWritten: *mut DWORD,
lpOverlapped: *mut core::ffi::c_void,
) -> BOOL;
pub fn ExitProcess(uExitCode: UINT) -> !;
pub fn GetCommandLineA() -> *const u8;
pub fn GetTickCount() -> DWORD;
pub fn QueryPerformanceCounter(lpPerformanceCount: *mut i64) -> BOOL;
pub fn QueryPerformanceFrequency(lpFrequency: *mut i64) -> BOOL;
pub fn Sleep(dwMilliseconds: DWORD);
}
/// UTF-16 helper: build a null-terminated wide string.
pub fn wide(s: &str) -> Vec<u16> {
s.encode_utf16().chain(core::iter::once(0)).collect()
}
/// Debug log through the shim's stdout (serial).
pub fn log(s: &str) {
unsafe {
let h = GetStdHandle(STD_OUTPUT_HANDLE);
let mut written: DWORD = 0;
WriteFile(h, s.as_ptr(), s.len() as DWORD, &mut written, core::ptr::null_mut());
}
}
CODE/Deaicup Software/src/Cargo.lock
Generated
+4639
View File
@@ -0,0 +1,4639 @@
# This file is automatically @generated by Cargo.
# It is not intended for manual editing.
version = 4
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"sha1",
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"tracing",
"uds_windows",
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"xdg-home",
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CODE/Deaicup Software/src/Cargo.toml
+13
View File
@@ -0,0 +1,13 @@
[package]
name = "Deaicup-Software"
version = "0.1.0"
edition = "2024"
[[bin]]
name = "Deaicup-Software"
path = "src/main.rs"
[dependencies]
egui = "0.27"
eframe = "0.27"
egui_extras = { version = "0.27" , features = ["all_loaders"] }
CODE/Deaicup Software/src/src/main.rs
+104
View File
@@ -0,0 +1,104 @@
#![cfg_attr(target_os = "windows", windows_subsystem = "windows")]
use eframe::egui;
fn main() -> Result<(), eframe::Error>{
let options = eframe::NativeOptions {
viewport: egui::ViewportBuilder::default().with_inner_size([800.0, 600.0]),
..Default::default()
};
eframe::run_native(
"Deaicup Software",
options,
Box::new(|cc| {
egui_extras::install_image_loaders(&cc.egui_ctx);
Box::new(DeaicupSoftware::default())
},)
)
}
#[derive(Default)]
struct DeaicupSoftware {
current_page: Page,
}
#[derive(Debug, PartialEq, Clone, Copy, Default)]
enum Page {
#[default]
Home,
Tool,
Game,
LinuxWare,
WindowsWare,
Set,
About
}
impl eframe::App for DeaicupSoftware{
fn update(&mut self, ctx: &egui::Context, frame: &mut eframe::Frame){
egui::TopBottomPanel::top("top_image_panel").show(ctx, |ui|{
let image_url = "https://deaicup.com/DeaicupSoftware/top.png";
ui.set_min_height(75.0);
let size = ui.available_size();
ui.image(egui::Image::new(image_url).fit_to_exact_size(egui::Vec2::new(size.x, 75.0)));
});
//main
egui::SidePanel::left("navigation_panel")
.default_width(200.0)
.resizable(true)
.show(ctx, |ui| {
ui.heading("Menu");
ui.separator();
ui.vertical(|ui| {
if ui.selectable_label(self.current_page == Page::Home, "HOME").clicked(){
self.current_page = Page::Home;
}
if ui.selectable_label(self.current_page == Page::Tool, "TOOL").clicked(){
self.current_page = Page::Tool;
}
if ui.selectable_label(self.current_page == Page::Game, "GAME").clicked(){
self.current_page = Page::Game;
}
if ui.selectable_label(self.current_page == Page::LinuxWare, "LINUXWARE").clicked(){
self.current_page = Page::LinuxWare;
}
if ui.selectable_label(self.current_page == Page::WindowsWare, "WINDOWSWARE").clicked(){
self.current_page = Page::WindowsWare;
}
if ui.selectable_label(self.current_page == Page::Set, "SET").clicked(){
self.current_page = Page::Set;
}
if ui.selectable_label(self.current_page == Page::About, "ABOUT").clicked(){
self.current_page = Page::About;
}
})
});
egui::CentralPanel::default().show(ctx, |ui| {
ui.separator();
match self.current_page {
Page::Home => {
ui.label("Home")
}
Page::Tool => {
ui.label("Tool")
}
Page::Game => {
ui.label("Game")
}
Page::LinuxWare => {
ui.label("LinuxWare")
}
Page::WindowsWare => {
ui.label("WindowsWare")
}
Page::Set => {
ui.label("Set")
}
Page::About => {
ui.label("About")
}
}
});
}
}
CODE/UTSM/MAKEFILE
+10 -2
View File
@@ -12,20 +12,28 @@ LDFLAGS := -nostdlib -static -z max-page-size=0x1000 -T linker.ld
C_SOURCES := $(wildcard arch/x86_64/*.c kernel/*.c runtime/*.c mm/*.c core/*.c crypto/*.c pckc/*.c utrw/*.c drr/*.c dkm/*.c test/*.c vmm/*.c pe/*.c)
S_SOURCES := $(wildcard arch/x86_64/*.S vmm/*.S)
OBJECTS := $(C_SOURCES:.c=.o) $(S_SOURCES:.S=.o)
DEPS := $(C_SOURCES:.c=.d)
.PHONY: all clean
# 显式指定默认目标：防止 -include 的 .d 文件(halt.d 等)抢占默认目标
.DEFAULT_GOAL := all
all: $(OUT)
# 头文件依赖追踪：clang -MMD 生成 .d，避免 config.h 等头修改后对象文件不重建
# 注意：-include 必须放在 all: 之后，否则第一个 .d 中的目标会成为 make 默认目标
-include $(DEPS)
$(OUT): $(OBJECTS) linker.ld
@if not exist "$(ROOT)\SYSTEM\boot" mkdir "$(ROOT)\SYSTEM\boot"
$(LD) $(LDFLAGS) -o $@ $(OBJECTS)
%.o: %.c
$(CC) $(CFLAGS) -c $< -o $@
$(CC) $(CFLAGS) -MMD -MP -c $< -o $@
%.o: %.S
$(CC) $(ASFLAGS) -c $< -o $@
clean:
powershell -NoProfile -Command "Get-ChildItem -Path . -Recurse -Filter *.o | Remove-Item -Force; if (Test-Path '$(OUT)') { Remove-Item '$(OUT)' -Force }"
powershell -NoProfile -Command "Get-ChildItem -Path . -Recurse -Include *.o,*.d | Remove-Item -Force; if (Test-Path '$(OUT)') { Remove-Item '$(OUT)' -Force }"
CODE/UTSM/arch/x86_64/halt.d
+1
View File
@@ -0,0 +1 @@
arch/x86_64/halt.o: arch\x86_64\halt.c
CODE/UTSM/arch/x86_64/idt.c
+335 -28
View File
@@ -1,6 +1,7 @@
#include <utsm/idt.h>
#include <utsm/log.h>
#include <utsm/types.h>
#include <utsm/instr.h>
/* IDT gate descriptor (64-bit) */
typedef struct __attribute__((packed)) {
@@ -29,7 +30,7 @@ static idt_entry g_idt[IDT_ENTRIES] __attribute__((aligned(16)));
#define ICW1_ICW4 0x01
#define ICW1_INIT 0x10
/* assembly stub declarations */
/* assembly stub declarations — vectors 0-255 全覆盖 */
extern void isr_stub_0(void);
extern void isr_stub_1(void);
extern void isr_stub_2(void);
@@ -78,20 +79,280 @@ extern void isr_stub_44(void);
extern void isr_stub_45(void);
extern void isr_stub_46(void);
extern void isr_stub_47(void);
extern void isr_stub_48(void);
extern void isr_stub_49(void);
extern void isr_stub_50(void);
extern void isr_stub_51(void);
extern void isr_stub_52(void);
extern void isr_stub_53(void);
extern void isr_stub_54(void);
extern void isr_stub_55(void);
extern void isr_stub_56(void);
extern void isr_stub_57(void);
extern void isr_stub_58(void);
extern void isr_stub_59(void);
extern void isr_stub_60(void);
extern void isr_stub_61(void);
extern void isr_stub_62(void);
extern void isr_stub_63(void);
extern void isr_stub_64(void);
extern void isr_stub_65(void);
extern void isr_stub_66(void);
extern void isr_stub_67(void);
extern void isr_stub_68(void);
extern void isr_stub_69(void);
extern void isr_stub_70(void);
extern void isr_stub_71(void);
extern void isr_stub_72(void);
extern void isr_stub_73(void);
extern void isr_stub_74(void);
extern void isr_stub_75(void);
extern void isr_stub_76(void);
extern void isr_stub_77(void);
extern void isr_stub_78(void);
extern void isr_stub_79(void);
extern void isr_stub_80(void);
extern void isr_stub_81(void);
extern void isr_stub_82(void);
extern void isr_stub_83(void);
extern void isr_stub_84(void);
extern void isr_stub_85(void);
extern void isr_stub_86(void);
extern void isr_stub_87(void);
extern void isr_stub_88(void);
extern void isr_stub_89(void);
extern void isr_stub_90(void);
extern void isr_stub_91(void);
extern void isr_stub_92(void);
extern void isr_stub_93(void);
extern void isr_stub_94(void);
extern void isr_stub_95(void);
extern void isr_stub_96(void);
extern void isr_stub_97(void);
extern void isr_stub_98(void);
extern void isr_stub_99(void);
extern void isr_stub_100(void);
extern void isr_stub_101(void);
extern void isr_stub_102(void);
extern void isr_stub_103(void);
extern void isr_stub_104(void);
extern void isr_stub_105(void);
extern void isr_stub_106(void);
extern void isr_stub_107(void);
extern void isr_stub_108(void);
extern void isr_stub_109(void);
extern void isr_stub_110(void);
extern void isr_stub_111(void);
extern void isr_stub_112(void);
extern void isr_stub_113(void);
extern void isr_stub_114(void);
extern void isr_stub_115(void);
extern void isr_stub_116(void);
extern void isr_stub_117(void);
extern void isr_stub_118(void);
extern void isr_stub_119(void);
extern void isr_stub_120(void);
extern void isr_stub_121(void);
extern void isr_stub_122(void);
extern void isr_stub_123(void);
extern void isr_stub_124(void);
extern void isr_stub_125(void);
extern void isr_stub_126(void);
extern void isr_stub_127(void);
extern void isr_stub_128(void);
extern void isr_stub_129(void);
extern void isr_stub_130(void);
extern void isr_stub_131(void);
extern void isr_stub_132(void);
extern void isr_stub_133(void);
extern void isr_stub_134(void);
extern void isr_stub_135(void);
extern void isr_stub_136(void);
extern void isr_stub_137(void);
extern void isr_stub_138(void);
extern void isr_stub_139(void);
extern void isr_stub_140(void);
extern void isr_stub_141(void);
extern void isr_stub_142(void);
extern void isr_stub_143(void);
extern void isr_stub_144(void);
extern void isr_stub_145(void);
extern void isr_stub_146(void);
extern void isr_stub_147(void);
extern void isr_stub_148(void);
extern void isr_stub_149(void);
extern void isr_stub_150(void);
extern void isr_stub_151(void);
extern void isr_stub_152(void);
extern void isr_stub_153(void);
extern void isr_stub_154(void);
extern void isr_stub_155(void);
extern void isr_stub_156(void);
extern void isr_stub_157(void);
extern void isr_stub_158(void);
extern void isr_stub_159(void);
extern void isr_stub_160(void);
extern void isr_stub_161(void);
extern void isr_stub_162(void);
extern void isr_stub_163(void);
extern void isr_stub_164(void);
extern void isr_stub_165(void);
extern void isr_stub_166(void);
extern void isr_stub_167(void);
extern void isr_stub_168(void);
extern void isr_stub_169(void);
extern void isr_stub_170(void);
extern void isr_stub_171(void);
extern void isr_stub_172(void);
extern void isr_stub_173(void);
extern void isr_stub_174(void);
extern void isr_stub_175(void);
extern void isr_stub_176(void);
extern void isr_stub_177(void);
extern void isr_stub_178(void);
extern void isr_stub_179(void);
extern void isr_stub_180(void);
extern void isr_stub_181(void);
extern void isr_stub_182(void);
extern void isr_stub_183(void);
extern void isr_stub_184(void);
extern void isr_stub_185(void);
extern void isr_stub_186(void);
extern void isr_stub_187(void);
extern void isr_stub_188(void);
extern void isr_stub_189(void);
extern void isr_stub_190(void);
extern void isr_stub_191(void);
extern void isr_stub_192(void);
extern void isr_stub_193(void);
extern void isr_stub_194(void);
extern void isr_stub_195(void);
extern void isr_stub_196(void);
extern void isr_stub_197(void);
extern void isr_stub_198(void);
extern void isr_stub_199(void);
extern void isr_stub_200(void);
extern void isr_stub_201(void);
extern void isr_stub_202(void);
extern void isr_stub_203(void);
extern void isr_stub_204(void);
extern void isr_stub_205(void);
extern void isr_stub_206(void);
extern void isr_stub_207(void);
extern void isr_stub_208(void);
extern void isr_stub_209(void);
extern void isr_stub_210(void);
extern void isr_stub_211(void);
extern void isr_stub_212(void);
extern void isr_stub_213(void);
extern void isr_stub_214(void);
extern void isr_stub_215(void);
extern void isr_stub_216(void);
extern void isr_stub_217(void);
extern void isr_stub_218(void);
extern void isr_stub_219(void);
extern void isr_stub_220(void);
extern void isr_stub_221(void);
extern void isr_stub_222(void);
extern void isr_stub_223(void);
extern void isr_stub_224(void);
extern void isr_stub_225(void);
extern void isr_stub_226(void);
extern void isr_stub_227(void);
extern void isr_stub_228(void);
extern void isr_stub_229(void);
extern void isr_stub_230(void);
extern void isr_stub_231(void);
extern void isr_stub_232(void);
extern void isr_stub_233(void);
extern void isr_stub_234(void);
extern void isr_stub_235(void);
extern void isr_stub_236(void);
extern void isr_stub_237(void);
extern void isr_stub_238(void);
extern void isr_stub_239(void);
extern void isr_stub_240(void);
extern void isr_stub_241(void);
extern void isr_stub_242(void);
extern void isr_stub_243(void);
extern void isr_stub_244(void);
extern void isr_stub_245(void);
extern void isr_stub_246(void);
extern void isr_stub_247(void);
extern void isr_stub_248(void);
extern void isr_stub_249(void);
extern void isr_stub_250(void);
extern void isr_stub_251(void);
extern void isr_stub_252(void);
extern void isr_stub_253(void);
extern void isr_stub_254(void);
extern void isr_stub_255(void);
static void *g_isr_table[] = {
isr_stub_0, isr_stub_1, isr_stub_2, isr_stub_3,
isr_stub_4, isr_stub_5, isr_stub_6, isr_stub_7,
isr_stub_8, isr_stub_9, isr_stub_10, isr_stub_11,
isr_stub_12, isr_stub_13, isr_stub_14, isr_stub_15,
isr_stub_16, isr_stub_17, isr_stub_18, isr_stub_19,
isr_stub_20, isr_stub_21, isr_stub_22, isr_stub_23,
isr_stub_24, isr_stub_25, isr_stub_26, isr_stub_27,
isr_stub_28, isr_stub_29, isr_stub_30, isr_stub_31,
isr_stub_32, isr_stub_33, isr_stub_34, isr_stub_35,
isr_stub_36, isr_stub_37, isr_stub_38, isr_stub_39,
isr_stub_40, isr_stub_41, isr_stub_42, isr_stub_43,
isr_stub_44, isr_stub_45, isr_stub_46, isr_stub_47,
static void *g_isr_table[256] = {
isr_stub_0, isr_stub_1, isr_stub_2, isr_stub_3,
isr_stub_4, isr_stub_5, isr_stub_6, isr_stub_7,
isr_stub_8, isr_stub_9, isr_stub_10, isr_stub_11,
isr_stub_12, isr_stub_13, isr_stub_14, isr_stub_15,
isr_stub_16, isr_stub_17, isr_stub_18, isr_stub_19,
isr_stub_20, isr_stub_21, isr_stub_22, isr_stub_23,
isr_stub_24, isr_stub_25, isr_stub_26, isr_stub_27,
isr_stub_28, isr_stub_29, isr_stub_30, isr_stub_31,
isr_stub_32, isr_stub_33, isr_stub_34, isr_stub_35,
isr_stub_36, isr_stub_37, isr_stub_38, isr_stub_39,
isr_stub_40, isr_stub_41, isr_stub_42, isr_stub_43,
isr_stub_44, isr_stub_45, isr_stub_46, isr_stub_47,
isr_stub_48, isr_stub_49, isr_stub_50, isr_stub_51,
isr_stub_52, isr_stub_53, isr_stub_54, isr_stub_55,
isr_stub_56, isr_stub_57, isr_stub_58, isr_stub_59,
isr_stub_60, isr_stub_61, isr_stub_62, isr_stub_63,
isr_stub_64, isr_stub_65, isr_stub_66, isr_stub_67,
isr_stub_68, isr_stub_69, isr_stub_70, isr_stub_71,
isr_stub_72, isr_stub_73, isr_stub_74, isr_stub_75,
isr_stub_76, isr_stub_77, isr_stub_78, isr_stub_79,
isr_stub_80, isr_stub_81, isr_stub_82, isr_stub_83,
isr_stub_84, isr_stub_85, isr_stub_86, isr_stub_87,
isr_stub_88, isr_stub_89, isr_stub_90, isr_stub_91,
isr_stub_92, isr_stub_93, isr_stub_94, isr_stub_95,
isr_stub_96, isr_stub_97, isr_stub_98, isr_stub_99,
isr_stub_100, isr_stub_101, isr_stub_102, isr_stub_103,
isr_stub_104, isr_stub_105, isr_stub_106, isr_stub_107,
isr_stub_108, isr_stub_109, isr_stub_110, isr_stub_111,
isr_stub_112, isr_stub_113, isr_stub_114, isr_stub_115,
isr_stub_116, isr_stub_117, isr_stub_118, isr_stub_119,
isr_stub_120, isr_stub_121, isr_stub_122, isr_stub_123,
isr_stub_124, isr_stub_125, isr_stub_126, isr_stub_127,
isr_stub_128, isr_stub_129, isr_stub_130, isr_stub_131,
isr_stub_132, isr_stub_133, isr_stub_134, isr_stub_135,
isr_stub_136, isr_stub_137, isr_stub_138, isr_stub_139,
isr_stub_140, isr_stub_141, isr_stub_142, isr_stub_143,
isr_stub_144, isr_stub_145, isr_stub_146, isr_stub_147,
isr_stub_148, isr_stub_149, isr_stub_150, isr_stub_151,
isr_stub_152, isr_stub_153, isr_stub_154, isr_stub_155,
isr_stub_156, isr_stub_157, isr_stub_158, isr_stub_159,
isr_stub_160, isr_stub_161, isr_stub_162, isr_stub_163,
isr_stub_164, isr_stub_165, isr_stub_166, isr_stub_167,
isr_stub_168, isr_stub_169, isr_stub_170, isr_stub_171,
isr_stub_172, isr_stub_173, isr_stub_174, isr_stub_175,
isr_stub_176, isr_stub_177, isr_stub_178, isr_stub_179,
isr_stub_180, isr_stub_181, isr_stub_182, isr_stub_183,
isr_stub_184, isr_stub_185, isr_stub_186, isr_stub_187,
isr_stub_188, isr_stub_189, isr_stub_190, isr_stub_191,
isr_stub_192, isr_stub_193, isr_stub_194, isr_stub_195,
isr_stub_196, isr_stub_197, isr_stub_198, isr_stub_199,
isr_stub_200, isr_stub_201, isr_stub_202, isr_stub_203,
isr_stub_204, isr_stub_205, isr_stub_206, isr_stub_207,
isr_stub_208, isr_stub_209, isr_stub_210, isr_stub_211,
isr_stub_212, isr_stub_213, isr_stub_214, isr_stub_215,
isr_stub_216, isr_stub_217, isr_stub_218, isr_stub_219,
isr_stub_220, isr_stub_221, isr_stub_222, isr_stub_223,
isr_stub_224, isr_stub_225, isr_stub_226, isr_stub_227,
isr_stub_228, isr_stub_229, isr_stub_230, isr_stub_231,
isr_stub_232, isr_stub_233, isr_stub_234, isr_stub_235,
isr_stub_236, isr_stub_237, isr_stub_238, isr_stub_239,
isr_stub_240, isr_stub_241, isr_stub_242, isr_stub_243,
isr_stub_244, isr_stub_245, isr_stub_246, isr_stub_247,
isr_stub_248, isr_stub_249, isr_stub_250, isr_stub_251,
isr_stub_252, isr_stub_253, isr_stub_254, isr_stub_255,
};
static void outb(u16 port, u8 value) {
@@ -109,9 +370,11 @@ static void io_wait(void) {
}
static void pic_remap(void) {
/* save masks */
/* save masks (kept for reference; fixed masks are applied below) */
u8 m1 = inb(PIC1_DATA);
u8 m2 = inb(PIC2_DATA);
(void)m1;
(void)m2;
/* ICW1: start init + ICW4 */
outb(PIC1_CMD, ICW1_INIT | ICW1_ICW4);
@@ -156,13 +419,9 @@ static void idt_set_entry(u8 vector, void *handler, u8 ist, u8 type) {
void idt_init(void) {
log_info("[IDT] init begin");
for (u16 i = 0; i < 48; i++) {
for (u16 i = 0; i < IDT_ENTRIES; i++) {
idt_set_entry((u8)i, g_isr_table[i], 0, 0x8E); /* present, ring0, 64-bit interrupt gate */
}
/* fill unused entries with null */
for (u16 i = 48; i < IDT_ENTRIES; i++) {
idt_set_entry((u8)i, 0, 0, 0);
}
idt_ptr idtr;
idtr.limit = (u16)(sizeof(g_idt) - 1);
@@ -178,12 +437,39 @@ void idt_init(void) {
log_info("[IDT] init ok");
}
/* IRQ handler table */
static irq_handler_t g_irq_handlers[16];
/* 安全 halt stub: cli; hlt 循环。用于 idt_halt_all()。
* 任何异常/IRQ 触发此 stub 将安全停机，不会三重故障。 */
static void isr_halt_stub(void) {
for (;;) { __asm__ volatile("cli; hlt"); }
}
int irq_register(u8 irq, irq_handler_t handler) {
if (irq >= 16) return -1;
g_irq_handlers[irq] = handler;
void idt_halt_all(void) {
/* 将 IDT 所有 256 个条目替换为安全 halt stub。
* 调用前应已 cli + mask PIC，此函数是额外防御层:
* - 实机 spurious IRQ7/15 即使 PIC 已 mask 也可能触发
* - NMI / SMI 可能导致异常
* - DSK 运行期间 CPU 异常 (PF/GP) 应安全停机而非执行过期 handler */
for (u16 i = 0; i < IDT_ENTRIES; i++) {
idt_set_entry((u8)i, (void *)isr_halt_stub, 0, 0x8E);
}
/* 重新加载 IDTR 以确保更改生效 */
idt_ptr idtr;
idtr.limit = (u16)(sizeof(g_idt) - 1);
idtr.base = (u64)&g_idt;
__asm__ volatile("lidt %0" :: "m"(idtr));
}
/* IRQ handler table — 扩展到 256 个 vector (真机 APIC/IOAPIC/MSI 需要) */
static irq_handler_t g_irq_handlers[256];
/* ---- 插桩: IRQ 统计计数器 ---- */
INSTR_STAT_DECL(pic_irq_total);
INSTR_STAT_DECL(apic_irq_total);
int irq_register(u8 vector, irq_handler_t handler) {
if ((unsigned)vector >= 256) return -1;
g_irq_handlers[vector] = handler;
INSTR_LOG(INSTR_LOG_DEBUG, INSTR_F_UTSM_TRACE, "[IDT] IRQ handler registered");
return 0;
}
@@ -197,6 +483,7 @@ typedef struct {
void idt_handler(isr_frame *frame) {
if (frame->vector < 32) {
INSTR_PROBE(EXCP, frame->vector, frame->error_code, frame->rip, 0);
log_error("[IDT] exception");
log_hex64("[IDT] vector=", frame->vector);
log_hex64("[IDT] err=", frame->error_code);
@@ -204,19 +491,39 @@ void idt_handler(isr_frame *frame) {
for (;;) { __asm__ volatile ("cli; hlt"); }
}
/* PIC IRQ: vectors 0x20-0x2F (32-47) */
if (frame->vector >= 32 && frame->vector <= 47) {
INSTR_STAT_INC(pic_irq_total);
u8 irq = (u8)(frame->vector - 0x20);
/* call registered handler */
if (irq < 16 && g_irq_handlers[irq]) {
int suppress_eoi = g_irq_handlers[irq](irq);
if (g_irq_handlers[frame->vector]) {
int suppress_eoi = g_irq_handlers[frame->vector](irq);
if (suppress_eoi) return;
}
/* send EOI */
/* send PIC EOI */
if (frame->vector >= 0x28) {
outb(PIC2_CMD, 0x20);
}
outb(PIC1_CMD, 0x20);
return;
}
/* APIC/IOAPIC/MSI IRQ: vectors 0x30-0xFF (48-255)
* **QEMU 无法测试但真机必需的代码路径**:
* - APIC EOI 写入 LAPIC EOI 寄存器 (0xFEE000B0)
* - 当前 PIC 仍激活, 不需要 APIC EOI
* - 迁移到 IOAPIC 后需要此处补 APIC EOI */
if (frame->vector >= 48 && frame->vector <= 255) {
INSTR_STAT_INC(apic_irq_total);
if (g_irq_handlers[frame->vector]) {
g_irq_handlers[frame->vector]((u8)frame->vector);
}
/* TODO: LAPIC EOI — 写 0 到 LAPIC EOI 寄存器 (mmio offset 0xB0)
* 当从 PIC 迁移到 APIC 中断路由时, 必须在此处添加:
* *(volatile u32 *)(hhdm_offset + lapic_phys + 0xB0) = 0;
*/
return;
}
}
CODE/UTSM/arch/x86_64/idt.d
+6
View File
@@ -0,0 +1,6 @@
arch/x86_64/idt.o: arch\x86_64\idt.c include\utsm\idt.h \
include\utsm\types.h include\utsm\log.h include\utsm\instr.h
include\utsm\idt.h:
include\utsm\types.h:
include\utsm\log.h:
include\utsm\instr.h:
CODE/UTSM/arch/x86_64/idt.o
BIN
View File
Binary file not shown.
CODE/UTSM/arch/x86_64/idt_stubs.S
+61 -1
View File
@@ -1,4 +1,8 @@
/* IDT assembly stubs — SAS-R0 interrupt vectors */
/* IDT assembly stubs — SAS-R0 interrupt vectors
* Vectors 0-31: CPU exceptions (some push error code)
* Vectors 32-47: PIC IRQ remap region
* Vectors 48-255: APIC/IOAPIC/MSI dynamic vectors
*/
.section .text
.macro isr_no_err n
@@ -34,6 +38,62 @@ isr_no_err 36; isr_no_err 37; isr_no_err 38; isr_no_err 39
isr_no_err 40; isr_no_err 41; isr_no_err 42; isr_no_err 43
isr_no_err 44; isr_no_err 45; isr_no_err 46; isr_no_err 47
/* Vectors 48-255: APIC/IOAPIC/MSI 真机动态向量
* 真机需要更多 vector: APIC timer (0x30+), IOAPIC GSI, MSI/MSI-X 等。
* 全部生成 stub 确保任何 vector 命中都有 handler, 不会 triple fault。 */
isr_no_err 48; isr_no_err 49; isr_no_err 50; isr_no_err 51
isr_no_err 52; isr_no_err 53; isr_no_err 54; isr_no_err 55
isr_no_err 56; isr_no_err 57; isr_no_err 58; isr_no_err 59
isr_no_err 60; isr_no_err 61; isr_no_err 62; isr_no_err 63
isr_no_err 64; isr_no_err 65; isr_no_err 66; isr_no_err 67
isr_no_err 68; isr_no_err 69; isr_no_err 70; isr_no_err 71
isr_no_err 72; isr_no_err 73; isr_no_err 74; isr_no_err 75
isr_no_err 76; isr_no_err 77; isr_no_err 78; isr_no_err 79
isr_no_err 80; isr_no_err 81; isr_no_err 82; isr_no_err 83
isr_no_err 84; isr_no_err 85; isr_no_err 86; isr_no_err 87
isr_no_err 88; isr_no_err 89; isr_no_err 90; isr_no_err 91
isr_no_err 92; isr_no_err 93; isr_no_err 94; isr_no_err 95
isr_no_err 96; isr_no_err 97; isr_no_err 98; isr_no_err 99
isr_no_err 100; isr_no_err 101; isr_no_err 102; isr_no_err 103
isr_no_err 104; isr_no_err 105; isr_no_err 106; isr_no_err 107
isr_no_err 108; isr_no_err 109; isr_no_err 110; isr_no_err 111
isr_no_err 112; isr_no_err 113; isr_no_err 114; isr_no_err 115
isr_no_err 116; isr_no_err 117; isr_no_err 118; isr_no_err 119
isr_no_err 120; isr_no_err 121; isr_no_err 122; isr_no_err 123
isr_no_err 124; isr_no_err 125; isr_no_err 126; isr_no_err 127
isr_no_err 128; isr_no_err 129; isr_no_err 130; isr_no_err 131
isr_no_err 132; isr_no_err 133; isr_no_err 134; isr_no_err 135
isr_no_err 136; isr_no_err 137; isr_no_err 138; isr_no_err 139
isr_no_err 140; isr_no_err 141; isr_no_err 142; isr_no_err 143
isr_no_err 144; isr_no_err 145; isr_no_err 146; isr_no_err 147
isr_no_err 148; isr_no_err 149; isr_no_err 150; isr_no_err 151
isr_no_err 152; isr_no_err 153; isr_no_err 154; isr_no_err 155
isr_no_err 156; isr_no_err 157; isr_no_err 158; isr_no_err 159
isr_no_err 160; isr_no_err 161; isr_no_err 162; isr_no_err 163
isr_no_err 164; isr_no_err 165; isr_no_err 166; isr_no_err 167
isr_no_err 168; isr_no_err 169; isr_no_err 170; isr_no_err 171
isr_no_err 172; isr_no_err 173; isr_no_err 174; isr_no_err 175
isr_no_err 176; isr_no_err 177; isr_no_err 178; isr_no_err 179
isr_no_err 180; isr_no_err 181; isr_no_err 182; isr_no_err 183
isr_no_err 184; isr_no_err 185; isr_no_err 186; isr_no_err 187
isr_no_err 188; isr_no_err 189; isr_no_err 190; isr_no_err 191
isr_no_err 192; isr_no_err 193; isr_no_err 194; isr_no_err 195
isr_no_err 196; isr_no_err 197; isr_no_err 198; isr_no_err 199
isr_no_err 200; isr_no_err 201; isr_no_err 202; isr_no_err 203
isr_no_err 204; isr_no_err 205; isr_no_err 206; isr_no_err 207
isr_no_err 208; isr_no_err 209; isr_no_err 210; isr_no_err 211
isr_no_err 212; isr_no_err 213; isr_no_err 214; isr_no_err 215
isr_no_err 216; isr_no_err 217; isr_no_err 218; isr_no_err 219
isr_no_err 220; isr_no_err 221; isr_no_err 222; isr_no_err 223
isr_no_err 224; isr_no_err 225; isr_no_err 226; isr_no_err 227
isr_no_err 228; isr_no_err 229; isr_no_err 230; isr_no_err 231
isr_no_err 232; isr_no_err 233; isr_no_err 234; isr_no_err 235
isr_no_err 236; isr_no_err 237; isr_no_err 238; isr_no_err 239
isr_no_err 240; isr_no_err 241; isr_no_err 242; isr_no_err 243
isr_no_err 244; isr_no_err 245; isr_no_err 246; isr_no_err 247
isr_no_err 248; isr_no_err 249; isr_no_err 250; isr_no_err 251
isr_no_err 252; isr_no_err 253; isr_no_err 254; isr_no_err 255
/* Common ISR */
isr_common:
pushq %rdi
CODE/UTSM/arch/x86_64/idt_stubs.o
BIN
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CODE/UTSM/arch/x86_64/io.d
+2
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@@ -0,0 +1,2 @@
arch/x86_64/io.o: arch\x86_64\io.c include\utsm\types.h
include\utsm\types.h:
CODE/UTSM/arch/x86_64/serial.d
+2
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@@ -0,0 +1,2 @@
arch/x86_64/serial.o: arch\x86_64\serial.c include\utsm\types.h
include\utsm\types.h:
CODE/UTSM/core/capability.d
+9
View File
@@ -0,0 +1,9 @@
core/capability.o: core\capability.c include\utsm\capability.h \
include\utsm\types.h include\utsm\status.h include\utsm\segment.h \
include\utsm\uuid.h include\utsm\dirty.h
include\utsm\capability.h:
include\utsm\types.h:
include\utsm\status.h:
include\utsm\segment.h:
include\utsm\uuid.h:
include\utsm\dirty.h:
CODE/UTSM/core/dirty.d
+11
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@@ -0,0 +1,11 @@
core/dirty.o: core\dirty.c include\utsm\dirty.h include\utsm\types.h \
include\utsm\segment.h include\utsm\uuid.h include\utsm\status.h \
include\utsm\capability.h include\utsm\arena.h include\utsm\config.h
include\utsm\dirty.h:
include\utsm\types.h:
include\utsm\segment.h:
include\utsm\uuid.h:
include\utsm\status.h:
include\utsm\capability.h:
include\utsm\arena.h:
include\utsm\config.h:
CODE/UTSM/core/dmp.d
+10
View File
@@ -0,0 +1,10 @@
core/dmp.o: core\dmp.c include\utsm\dmp.h include\utsm\types.h \
include\utsm\segment.h include\utsm\uuid.h include\utsm\status.h \
include\utsm\capability.h include\utsm\dirty.h
include\utsm\dmp.h:
include\utsm\types.h:
include\utsm\segment.h:
include\utsm\uuid.h:
include\utsm\status.h:
include\utsm\capability.h:
include\utsm\dirty.h:
CODE/UTSM/core/process.d
+13
View File
@@ -0,0 +1,13 @@
core/process.o: core\process.c include\utsm\process.h \
include\utsm\types.h include\utsm\uuid.h include\utsm\capability.h \
include\utsm\status.h include\utsm\config.h include\utsm\drr.h \
include\utsm\arena.h include\utsm\log.h
include\utsm\process.h:
include\utsm\types.h:
include\utsm\uuid.h:
include\utsm\capability.h:
include\utsm\status.h:
include\utsm\config.h:
include\utsm\drr.h:
include\utsm\arena.h:
include\utsm\log.h:
CODE/UTSM/core/segment.d
+14
View File
@@ -0,0 +1,14 @@
core/segment.o: core\segment.c include\utsm\segment.h \
include\utsm\types.h include\utsm\uuid.h include\utsm\status.h \
include\utsm\capability.h include\utsm\dirty.h include\utsm\process.h \
include\utsm\config.h include\utsm\arena.h include\utsm\dmp.h
include\utsm\segment.h:
include\utsm\types.h:
include\utsm\uuid.h:
include\utsm\status.h:
include\utsm\capability.h:
include\utsm\dirty.h:
include\utsm\process.h:
include\utsm\config.h:
include\utsm\arena.h:
include\utsm\dmp.h:
CODE/UTSM/core/utsm_init.c
+5 -2
View File
@@ -3,13 +3,16 @@
#include <utsm/pckc.h>
#include <utsm/process.h>
#include <utsm/log.h>
#include <utsm/config.h>
static utsm_segment_desc g_segments[UTSM_MAX_SEGMENTS];
static u64 g_generation = 1;
void utsm_init(void) {
log_info("[UTSM] segment table reset begin");
for (u32 i = 0; i < UTSM_MAX_SEGMENTS; i++) {
u32 max_seg = g_utsm_max_segments;
if (max_seg > UTSM_MAX_SEGMENTS) max_seg = UTSM_MAX_SEGMENTS;
for (u32 i = 0; i < max_seg; i++) {
g_segments[i].state = UTSM_SEG_FREE;
g_segments[i].generation = 1;
}
@@ -24,7 +27,7 @@ void utsm_init(void) {
}
utsm_segment_desc *utsm_get_segment(u32 slot) {
if (slot >= UTSM_MAX_SEGMENTS) {
if (slot >= g_utsm_max_segments || slot >= UTSM_MAX_SEGMENTS) {
return NULL;
}
return &g_segments[slot];
CODE/UTSM/core/utsm_init.d
+25
View File
@@ -0,0 +1,25 @@
core/utsm_init.o: core\utsm_init.c include\utsm\utsm.h \
include\utsm\types.h include\utsm\status.h include\utsm\config.h \
include\utsm\uuid.h include\utsm\process.h include\utsm\capability.h \
include\utsm\segment.h include\utsm\dirty.h include\utsm\utrw.h \
include\utsm\vmm.h include\utsm\linux_loader.h include\utsm\ipc_shm.h \
..\utsm-ipc\ipc_proto.h include\utsm\hypercall.h include\utsm\pckc.h \
include\utsm\crypto.h include\utsm\log.h
include\utsm\utsm.h:
include\utsm\types.h:
include\utsm\status.h:
include\utsm\config.h:
include\utsm\uuid.h:
include\utsm\process.h:
include\utsm\capability.h:
include\utsm\segment.h:
include\utsm\dirty.h:
include\utsm\utrw.h:
include\utsm\vmm.h:
include\utsm\linux_loader.h:
include\utsm\ipc_shm.h:
..\utsm-ipc\ipc_proto.h:
include\utsm\hypercall.h:
include\utsm\pckc.h:
include\utsm\crypto.h:
include\utsm\log.h:
CODE/UTSM/core/utsm_init.o
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CODE/UTSM/crypto/kdf.d
+7
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@@ -0,0 +1,7 @@
crypto/kdf.o: crypto\kdf.c include\utsm\crypto.h include\utsm\types.h \
include\utsm\uuid.h include\utsm\drr.h include\utsm\config.h
include\utsm\crypto.h:
include\utsm\types.h:
include\utsm\uuid.h:
include\utsm\drr.h:
include\utsm\config.h:
CODE/UTSM/crypto/stream.d
+6
View File
@@ -0,0 +1,6 @@
crypto/stream.o: crypto\stream.c include\utsm\crypto.h \
include\utsm\types.h include\utsm\uuid.h include\utsm\config.h
include\utsm\crypto.h:
include\utsm\types.h:
include\utsm\uuid.h:
include\utsm\config.h:
CODE/UTSM/crypto/tweak.d
+5
View File
@@ -0,0 +1,5 @@
crypto/tweak.o: crypto\tweak.c include\utsm\crypto.h include\utsm\types.h \
include\utsm\uuid.h
include\utsm\crypto.h:
include\utsm\types.h:
include\utsm\uuid.h:
CODE/UTSM/dkm/boot_modules.d
+13
View File
@@ -0,0 +1,13 @@
dkm/boot_modules.o: dkm\boot_modules.c include\utsm\dkm.h \
include\utsm\types.h include\utsm\dma.h include\utsm\block.h \
include\utsm\net.h include\utsm\paging.h include\utsm\log.h \
include\utsm\arena.h dkm\..\arch\x86_64\limine.h
include\utsm\dkm.h:
include\utsm\types.h:
include\utsm\dma.h:
include\utsm\block.h:
include\utsm\net.h:
include\utsm\paging.h:
include\utsm\log.h:
include\utsm\arena.h:
dkm\..\arch\x86_64\limine.h:
CODE/UTSM/dkm/console_early.d
+9
View File
@@ -0,0 +1,9 @@
dkm/console_early.o: dkm\console_early.c include\utsm\dkm.h \
include\utsm\types.h include\utsm\dma.h include\utsm\block.h \
include\utsm\net.h include\utsm\paging.h
include\utsm\dkm.h:
include\utsm\types.h:
include\utsm\dma.h:
include\utsm\block.h:
include\utsm\net.h:
include\utsm\paging.h:
CODE/UTSM/dkm/dkm_core.d
+10
View File
@@ -0,0 +1,10 @@
dkm/dkm_core.o: dkm\dkm_core.c include\utsm\dkm.h include\utsm\types.h \
include\utsm\dma.h include\utsm\block.h include\utsm\net.h \
include\utsm\paging.h include\utsm\log.h
include\utsm\dkm.h:
include\utsm\types.h:
include\utsm\dma.h:
include\utsm\block.h:
include\utsm\net.h:
include\utsm\paging.h:
include\utsm\log.h:
CODE/UTSM/dkm/kernel_api.c
+8 -1
View File
@@ -2,6 +2,7 @@
#include <utsm/log.h>
#include <utsm/idt.h>
#include <utsm/net.h>
#include <utsm/mm.h>
static void dkm_api_info(const char *msg) {
log_info(msg);
@@ -52,7 +53,10 @@ static dkm_kernel_api g_kernel_api = {
.boot_modules_response = 0,
.irq_register = 0,
.hhdm_offset = 0,
.block = 0
.block = 0,
.mmio = 0,
.mm_map_mmio = 0,
.mm_unmap_mmio = 0
};
const dkm_kernel_api *dkm_get_kernel_api(void) {
@@ -69,6 +73,7 @@ void dkm_fill_platform_info(void) {
g_kernel_api.dma = dma_get_api();
g_kernel_api.net = net_get_api();
g_kernel_api.block = block_get_api();
g_kernel_api.mmio = paging_get_api();
if (g_rsdp_request.response && g_rsdp_request.response->address) {
g_kernel_api.rsdp_address = g_rsdp_request.response->address;
}
@@ -87,4 +92,6 @@ void dkm_fill_platform_info(void) {
if (g_hhdm_request.response) {
g_kernel_api.hhdm_offset = g_hhdm_request.response->offset;
}
g_kernel_api.mm_map_mmio = mm_map_mmio;
g_kernel_api.mm_unmap_mmio = mm_unmap_mmio;
}
CODE/UTSM/dkm/kernel_api.d
+14
View File
@@ -0,0 +1,14 @@
dkm/kernel_api.o: dkm\kernel_api.c include\utsm\dkm.h \
include\utsm\types.h include\utsm\dma.h include\utsm\block.h \
include\utsm\net.h include\utsm\paging.h include\utsm\log.h \
include\utsm\idt.h include\utsm\mm.h dkm\..\arch\x86_64\limine.h
include\utsm\dkm.h:
include\utsm\types.h:
include\utsm\dma.h:
include\utsm\block.h:
include\utsm\net.h:
include\utsm\paging.h:
include\utsm\log.h:
include\utsm\idt.h:
include\utsm\mm.h:
dkm\..\arch\x86_64\limine.h:
CODE/UTSM/dkm/kernel_api.o
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CODE/UTSM/dkm/manifest.c
+18
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@@ -2,6 +2,10 @@
#include <utsm/log.h>
#include <utsm/types.h>
#include "../arch/x86_64/limine.h"
#include "../kernel/ini_parser.h"
/* 前向声明：带 FUCK [drivers] 过滤的加载入口（定义见下文） */
void dsm_load_by_manifest_ex(const ini_config *cfg);
#define DSM_MAX_DRIVERS_PER_STAGE 8
#define DSM_MAX_STAGES 4
@@ -283,6 +287,10 @@ static int dsm_parse_manifest(const char *text, u64 size) {
}
void dsm_load_by_manifest(void) {
dsm_load_by_manifest_ex(NULL);
}
void dsm_load_by_manifest_ex(const ini_config *cfg) {
struct limine_module_response *rsp = g_module_request.response;
if (!rsp) {
log_warn("[DSM] no Limine module response");
@@ -317,6 +325,16 @@ void dsm_load_by_manifest(void) {
for (u32 di = 0; di < stage->driver_count; di++) {
dsm_driver_entry *drv = &stage->drivers[di];
/* === FUCK [drivers] 驱动开关检查 === */
if (cfg) {
int enabled = ini_get_bool(cfg, "drivers", drv->name, 1);
if (!enabled) {
log_info("[DSM] driver disabled by FUCK: ");
log_info(drv->name);
continue; /* 跳过此驱动 */
}
}
drv->boot_module = dsm_find_boot_module(drv->path);
if (!drv->boot_module) {
log_info("[DSM] module not found");
CODE/UTSM/dkm/manifest.d
+13
View File
@@ -0,0 +1,13 @@
dkm/manifest.o: dkm\manifest.c include\utsm\dkm.h include\utsm\types.h \
include\utsm\dma.h include\utsm\block.h include\utsm\net.h \
include\utsm\paging.h include\utsm\log.h dkm\..\arch\x86_64\limine.h \
dkm\..\kernel\ini_parser.h
include\utsm\dkm.h:
include\utsm\types.h:
include\utsm\dma.h:
include\utsm\block.h:
include\utsm\net.h:
include\utsm\paging.h:
include\utsm\log.h:
dkm\..\arch\x86_64\limine.h:
dkm\..\kernel\ini_parser.h:
CODE/UTSM/dkm/manifest.o
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CODE/UTSM/drr/drr_stub.d
+6
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@@ -0,0 +1,6 @@
drr/drr_stub.o: drr\drr_stub.c include\utsm\drr.h include\utsm\types.h \
include\utsm\config.h include\utsm\log.h
include\utsm\drr.h:
include\utsm\types.h:
include\utsm\config.h:
include\utsm\log.h:
CODE/UTSM/include/utsm/config.h
+24 -5
View File
@@ -1,13 +1,32 @@
#ifndef UTSM_CONFIG_H
#define UTSM_CONFIG_H
#include <utsm/types.h>
/* ---- 编译期固定常量（不暴露给 FUCK 配置） ---- */
#define UTSM_CACHE_LINE_SIZE 64ULL
#define UTSM_PAGE_SIZE 4096ULL
#define UTSM_MAX_SEGMENTS 1024U
#define UTSM_MAX_CAPABILITIES 256U
#define UTSM_MAX_PCKC_KEYS 8U
#define UTSM_ARENA_SIZE (16ULL * 1024ULL * 1024ULL)
#define UTSM_DIRTY_SHARD_PAGES 1024ULL
#define UTSM_KERNEL_STACK_SIZE 16384ULL
/* ---- 编译期默认值宏（用于静态数组大小上限） ---- */
#define UTSM_MAX_SEGMENTS_DEFAULT 1024U
#define UTSM_MAX_CAPABILITIES_DEFAULT 256U
#define UTSM_MAX_PCKC_KEYS_DEFAULT 8U
#define UTSM_ARENA_SIZE_DEFAULT (64ULL * 1024ULL * 1024ULL)
#define UTSM_DIRTY_SHARD_PAGES_DEFAULT 1024ULL
/* ---- 运行期配置变量（由 kernel_main 从 FUCK 文件初始化） ---- */
extern u32 g_utsm_max_segments;
extern u32 g_utsm_max_capabilities;
extern u32 g_utsm_max_pckc_keys;
extern u64 g_utsm_arena_size;
extern u64 g_utsm_dirty_shard_pages;
/* ---- 保留旧宏名（兼容性），映射到默认值 ---- */
#define UTSM_MAX_SEGMENTS UTSM_MAX_SEGMENTS_DEFAULT
#define UTSM_MAX_CAPABILITIES UTSM_MAX_CAPABILITIES_DEFAULT
#define UTSM_MAX_PCKC_KEYS UTSM_MAX_PCKC_KEYS_DEFAULT
#define UTSM_ARENA_SIZE UTSM_ARENA_SIZE_DEFAULT
#define UTSM_DIRTY_SHARD_PAGES UTSM_DIRTY_SHARD_PAGES_DEFAULT
#endif
CODE/UTSM/include/utsm/dkm.h
+5
View File
@@ -5,6 +5,7 @@
#include <utsm/dma.h>
#include <utsm/block.h>
#include <utsm/net.h>
#include <utsm/paging.h>
#define DKM_DRIVER_MAGIC 0x444B4D31u
#define DKM_ABI_VERSION 1u
@@ -95,6 +96,10 @@ typedef struct dkm_kernel_api {
int (*irq_register)(u8 irq, void *handler); /* kernel irq_register */
u64 hhdm_offset; /* physical → virtual */
const dkm_block_api *block; /* block provider registry */
const dkm_mmio_api *mmio; /* 页表/高位 MMIO 映射服务（尾部追加，ABI 兼容） */
/* —— 新增字段只允许追加在末尾（DSK 以 api+0xA8 硬偏移读取 block） —— */
void *(*mm_map_mmio)(u64 phys, u64 size); /* MMIO 独立窗口映射（PCD|PWT），返回虚拟地址，失败返回 0 */
void (*mm_unmap_mmio)(void *virt, u64 size); /* 解除 MMIO 独立窗口映射 */
} dkm_kernel_api;
typedef enum dkm_driver_state {
CODE/UTSM/include/utsm/dsk.h
+17
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@@ -9,6 +9,23 @@
#define DSK_BOOT_FLAG_FROM_UTSM (1ULL << 0)
#define DSK_BOOT_FLAG_DKM_READY (1ULL << 1)
#define DSK_BOOT_FLAG_FAT32_PATH (1ULL << 2)
#define DSK_BOOT_FLAG_PROBE_INFO (1ULL << 3)
/* ---- Probe 信息结构（通过 reserved[6] 传递给 shell/desktop） ---- */
#define PROBE_INFO_MAGIC 0x50524F42u /* "PRFB" — Probe inFo Buffer */
typedef struct probe_info {
u32 magic; /* PROBE_INFO_MAGIC */
u32 version; /* ABI 版本，当前 1 */
u64 probe_buf_addr; /* probe_entry 缓冲基地址（物理/HHDM 地址） */
u32 probe_cap; /* 缓冲容量（条目数） */
u32 probe_head; /* 当前写入位置（递增取模） */
u32 probe_count; /* 已写入总条目数 */
u32 probe_dropped; /* 因缓冲满而覆盖的条目数 */
u32 instr_enabled; /* g_instr_enabled 当前值 */
u32 instr_probe_enable; /* g_instr_probe_enable 当前值 */
u64 reserved[4];
} probe_info;
typedef struct dsk_boot_context {
u64 magic;
CODE/UTSM/include/utsm/ept.h
+15
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@@ -30,4 +30,19 @@ int ept_identity_map(u64 gpa, u64 size, u64 flags);
* Handles 4KB pages and 2MB large pages. */
u64 ept_gpa_to_hpa(u64 gpa);
/* Map a 2MB large page in EPT (PD-level direct mapping).
* GPA and HPA must be 2MB-aligned. memtype = EPT_MEMORY_TYPE_*.
* Required for real hardware MTRR compliance. */
int ept_map_2m_page(u64 gpa, u64 hpa, u64 flags, u64 memtype);
/* Check INVVPID/INVEPT support from IA32_VMX_EPT_VPID_CAP MSR.
* Call once after VMX init. */
void ept_check_vpid_support(void);
/* Flush EPT TLB entries (INVEPT). Required after EPT mapping changes on real hardware. */
void ept_flush_ept(void);
/* Flush VPID TLB entries (INVVPID). Required after VPID changes on real hardware. */
void ept_flush_vpid(u16 vpid);
#endif
CODE/UTSM/include/utsm/idt.h
+11 -3
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@@ -5,8 +5,16 @@
void idt_init(void);
/* IRQ handler: return 1 to suppress default ACK, 0 for normal EOI */
typedef int (*irq_handler_t)(u8 irq);
int irq_register(u8 irq, irq_handler_t handler);
/* 将 IDT 所有 256 个条目替换为安全 halt stub (cli; hlt)。
* 用于 UTSM→DSK 跳转前，防止 DSK 运行期间过期 UTSM handler
* 被 spurious IRQ / 异常触发导致三重故障重启。 */
void idt_halt_all(void);
/* IRQ handler: return 1 to suppress default ACK (PIC), 0 for normal EOI.
* 参数为 IDT vector 号 (0x20-0xFF)。
* PIC IRQ (0x20-0x2F): 返回 1 抑制 PIC EOI; 返回 0 自动发送 PIC EOI。
* APIC/IOAPIC/MSI (0x30-0xFF): 返回值当前忽略, EOI 需手动处理 (TODO)。 */
typedef int (*irq_handler_t)(u8 vector);
int irq_register(u8 vector, irq_handler_t handler);
#endif
CODE/UTSM/include/utsm/instr.h
+181
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@@ -0,0 +1,181 @@
/* instr.h — Deshab 统一插桩宏系统
*
* 提供四级插桩原语:
* INSTR_LOG — 带级别和模块过滤的日志输出
* INSTR_STAT — 轻量级计数器 + 周期性摘要
* INSTR_PROBE — 环形探测缓冲写入（结构化事件记录）
* INSTR_TS — 时间戳标注（阶段耗时测量）
*
* 设计原则:
* - 禁用时零开销: g_instr_enabled=0 时所有宏展开为空操作
* - 热路径安全: STAT_INC 仅一条条件自增，PROBE 仅条件写入
* - 统一配置: 通过 FUCK [debug] 段控制开关与粒度
* - 标签编码: 4 字符 ASCII 编码为 u32，避免字符串比较
*
* 使用方式:
* 1. 在 kernel_main() 中调用 instr_init(&g_boot_cfg) 初始化
* 2. 各模块 #include <utsm/instr.h> 后使用 INSTR_* 宏
* 3. 在 FUCK 中设置 [debug] enabled=1 开启插桩
*/
#ifndef UTSM_INSTR_H
#define UTSM_INSTR_H
#include <utsm/types.h>
/* ---- 日志级别 ---- */
#define INSTR_LOG_TRACE 0
#define INSTR_LOG_DEBUG 1
#define INSTR_LOG_INFO 2
#define INSTR_LOG_WARN 3
#define INSTR_LOG_ERROR 4
#define INSTR_LOG_SILENT 5
/* ---- 全局配置变量 (instr.c 定义) ---- */
extern u32 g_instr_enabled; /* 全局插桩开关，FUCK debug.enabled */
extern u32 g_instr_log_level; /* 日志级别阈值，FUCK debug.log_level */
extern u32 g_instr_probe_enable; /* 探测缓冲开关，FUCK debug.probe_enable */
extern u32 g_instr_stat_interval; /* 统计摘要间隔，FUCK debug.stat_summary_interval */
extern u32 g_instr_module_flags; /* 模块级过滤位掩码 */
/* ---- 模块标志位 ---- */
#define INSTR_F_UTSM_TRACE (1u << 0)
#define INSTR_F_VMM_TRACE (1u << 1)
#define INSTR_F_DKM_TRACE (1u << 2)
#define INSTR_F_DSK_TRACE (1u << 3)
#define INSTR_F_BLOCK_TRACE (1u << 4)
#define INSTR_F_NET_TRACE (1u << 5)
#define INSTR_F_INPUT_TRACE (1u << 6)
/* ---- INSTR_LOG: 带级别和模块过滤的日志 ----
* level: INSTR_LOG_TRACE/DEBUG/INFO/WARN/ERROR
* mod_flag: INSTR_F_xxx 或 0(不过滤)
* msg: 常量字符串
*
* 仅当 g_instr_enabled && level >= g_instr_log_level &&
* (mod_flag==0 || mod_flag & g_instr_module_flags) 时输出。
*/
#define INSTR_LOG(level, mod_flag, msg) do { \
if (g_instr_enabled && (level) >= g_instr_log_level && \
((mod_flag) == 0 || (g_instr_module_flags & (mod_flag)))) { \
if ((level) <= INSTR_LOG_ERROR) log_error(msg); \
else if ((level) <= INSTR_LOG_WARN) log_warn(msg); \
else log_info(msg); \
} \
} while(0)
/* ---- INSTR_STAT: 轻量级计数器 (声明+增量+摘要) ----
* INSTR_STAT_DECL(name) — 在函数/文件作用域声明计数器
* INSTR_STAT_INC(name) — 原子性自增 (仅当 enabled)
* INSTR_STAT_SUMMARY(name) — 达到间隔时输出摘要并重置
*/
#define INSTR_STAT_DECL(name) \
static u64 name##_count = 0; \
static u64 name##_last_ts __attribute__((unused)) = 0
#define INSTR_STAT_INC(name) do { \
if (g_instr_enabled) { name##_count++; } \
} while(0)
#define INSTR_STAT_SUMMARY(name) do { \
if (g_instr_enabled && name##_count >= g_instr_stat_interval) { \
u64 _now = instr_rdtsc(); \
u64 _elapsed_ms = (_now - name##_last_ts) / (instr_tsc_per_ms ? instr_tsc_per_ms : 1); \
log_info("[STAT] " #name " count="); \
log_hex64("", name##_count); \
log_info("[STAT] " #name " interval_ms="); \
log_hex64("", _elapsed_ms); \
name##_count = 0; \
name##_last_ts = _now; \
} \
} while(0)
/* ---- INSTR_PROBE: 写入环形探测缓冲 ----
* 标签编码: 4 字符 ASCII，如 "BOOT", "VME0", "EPTV", "IDTI", "AHCI"
* a0-a3: 4 个 u64 参数，语义由标签定义
*
* 仅当 g_instr_enabled && g_instr_probe_enable 时写入。
*/
#define INSTR_PROBE(tag, a0, a1, a2, a3) do { \
if (g_instr_enabled && g_instr_probe_enable) \
probe_write(INSTR_TAG_##tag, (u64)(a0), (u64)(a1), (u64)(a2), (u64)(a3)); \
} while(0)
/* ---- INSTR_TS: 时间戳标注（阶段耗时测量） ----
* INSTR_TS_DECL(name) — 声明时间戳变量
* INSTR_TS_BEGIN(name) — 记录起始 TSC
* INSTR_TS_END(name, label) — 计算耗时并输出（仅当 enabled）
*/
#define INSTR_TS_DECL(name) static u64 name##_ts = 0
#define INSTR_TS_BEGIN(name) do { name##_ts = instr_rdtsc(); } while(0)
#define INSTR_TS_END(name, label) do { \
if (g_instr_enabled) { \
u64 _d = instr_rdtsc() - name##_ts; \
u64 _ms = _d / (instr_tsc_per_ms ? instr_tsc_per_ms : 1); \
log_info("[TS] " label " elapsed_ms="); \
log_hex64("", _ms); \
} \
} while(0)
/* ---- 标签编码常量 ----
* 4 字符 ASCII 编码为大端序 u32:
* 'B'=0x42, 'O'=0x4F, 'O'=0x4F, 'T'=0x54 → 0x424F4F54
*/
#define INSTR_TAG_BOOT 0x424F4F54u /* "BOOT" — 通用启动事件 */
#define INSTR_TAG_IDT0 0x49445430u /* "IDT0" — IDT/中断初始化 */
#define INSTR_TAG_ARE0 0x41524530u /* "ARE0" — Arena 初始化 */
#define INSTR_TAG_DMA0 0x444D4130u /* "DMA0" — DMA 初始化 */
#define INSTR_TAG_NET0 0x4E455430u /* "NET0" — 网络注册 */
#define INSTR_TAG_DRR0 0x44525230u /* "DRR0" — DRR 初始化 */
#define INSTR_TAG_UTS0 0x55545330u /* "UTS0" — UTSM 核心初始化 */
#define INSTR_TAG_DKM0 0x444B4D30u /* "DKM0" — DKM 加载 */
#define INSTR_TAG_DSM0 0x44534D30u /* "DSM0" — 驱动 manifest 加载 */
#define INSTR_TAG_DSK0 0x44534B30u /* "DSK0" — DSK 加载跳转 */
#define INSTR_TAG_SELF 0x53454C46u /* "SELF" — 自检 */
#define INSTR_TAG_VMM0 0x564D4D30u /* "VMM0" — VMM 初始化 */
#define INSTR_TAG_LIN0 0x4C494E30u /* "LIN0" — Linux loader */
#define INSTR_TAG_VME0 0x564D4530u /* "VME0" — VM-Exit 事件 */
#define INSTR_TAG_EPTV 0x45505456u /* "EPTV" — EPT violation */
#define INSTR_TAG_EPTM 0x4550544Du /* "EPTM" — EPT misconfig */
#define INSTR_TAG_AHCI 0x41484349u /* "AHCI" — AHCI 事件 */
#define INSTR_TAG_E1K0 0x45314B30u /* "E1K0" — e1000 事件 */
#define INSTR_TAG_FAT0 0x46415430u /* "FAT0" — FAT32 事件 */
#define INSTR_TAG_NVM0 0x4E564D30u /* "NVM0" — NVMe 事件 */
#define INSTR_TAG_IRQ0 0x49525130u /* "IRQ0" — IRQ 注册/触发 */
#define INSTR_TAG_PIT0 0x50495430u /* "PIT0" — PIT 模拟 */
#define INSTR_TAG_SRL0 0x53524C30u /* "SRL0" — 串口事件 */
#define INSTR_TAG_MMIO 0x4D4D494Fu /* "MMIO" — MMIO 访问 */
#define INSTR_TAG_HCALL 0x4843414Cu /* "HCAL" — Hypercall */
#define INSTR_TAG_EXCP 0x45584350u /* "EXCP" — CPU 异常 */
/* ---- 探测条目结构（与 probe.c 共享） ---- */
typedef struct probe_entry {
u32 tag; /* 4字符ASCII标签 */
u32 tick; /* 低32位TSC（~2s溢出@2GHz，足够诊断） */
u64 args[4]; /* 4个u64参数 */
} probe_entry;
/* ---- 辅助函数声明 (instr.c / probe.c 定义) ---- */
u64 instr_rdtsc(void);
extern u64 instr_tsc_per_ms;
void instr_init(const void *ini_config);
void probe_init(const void *ini_config);
void probe_write(u32 tag, u64 a0, u64 a1, u64 a2, u64 a3);
int probe_read(u32 n, probe_entry *out);
u32 probe_count(void);
u32 probe_capacity(void);
probe_entry *probe_buf_address(void);
u32 probe_head_value(void);
u32 probe_dropped_count(void);
/* 需要前向声明 log 函数 (避免循环 include) */
#ifndef UTSM_LOG_H
void log_info(const char *msg);
void log_warn(const char *msg);
void log_error(const char *msg);
void log_hex64(const char *prefix, u64 value);
#endif
#endif /* UTSM_INSTR_H */
CODE/UTSM/include/utsm/ipc_shm.h
+14
View File
@@ -43,6 +43,20 @@ u64 ipc_shm_get_gpa(void);
/* Get the size of the shared memory region. */
u64 ipc_shm_get_size(void);
/* ===== Payload pool access (bulk data channel) =====
*
* The payload_pool area of the SHM region carries bulk file-transfer data
* (Phase 3 FILE_LIST/FILE_READ). Linux daemon writes into it (via
* UTSM_IOCTL_WRITE_POOL) before sending UTSM_MSG_FILE_RESPONSE; UTSM reads
* it directly through its own HHDM mapping. */
/* Host virtual pointer into payload_pool at byte offset.
* Returns NULL if not initialized or offset out of range. */
void *ipc_shm_payload_ptr(u32 offset);
/* Total capacity of the payload pool in bytes. */
u32 ipc_shm_payload_capacity(void);
/* ===== Message API (UTSM-side) ===== */
/* Send a message from UTSM to Linux (enqueues into utsm_to_linux ring).
CODE/UTSM/include/utsm/linux_compat.h
+58
View File
@@ -42,10 +42,68 @@ typedef struct linux_compat_service {
char *stdout_buf, u64 stdout_cap, u64 *stdout_len,
u64 *exit_code);
/* 列出 Linux 目录内容（Phase 3 文件传输）。
* path : Linux 绝对路径（如 "/usr/bin"）
* buf/cap : 接收列表文本的缓冲区（每行一项，目录名带 '/' 后缀）
* out_len : 实际写入字节数（可为 NULL）
* 返回 0 成功，负值失败（-1=服务不可用, -2=IPC 发送失败,
* -3=linux_resume 失败, -4=无响应, -5=Linux 侧错误,
* -6=缓冲区不足被截断，此时 out_len 仍给出截断长度）。 */
int (*file_list)(const char *path, char *buf, u64 cap, u64 *out_len);
/* 读取 Linux 文件内容（Phase 3 文件传输，支持大文件分块）。
* path : Linux 绝对路径（如 "/etc/hostname"）
* offset : 文件内起始偏移（首次读传 0）
* buf/cap : 接收文件数据的缓冲区
* out_len : 本次实际读取字节数（可为 NULL）
* out_total : 文件总大小（可为 NULL）
* 返回 0 成功（含 EOF：out_len=0 且 offset>=total），负值失败
* （错误码同 file_list）。 */
int (*file_read)(const char *path, u64 offset, char *buf, u64 cap,
u64 *out_len, u64 *out_total);
/* 查询 Linux guest 状态字符串（调试用），写入 buf，返回字符串长度。 */
int (*status)(char *buf, u64 cap);
/* 写入 Linux 文件（Phase 3 文件传输，支持大文件分块）。
* 调用方以递增 offset 循环调用即可上传任意大小文件。
* path : Linux 绝对路径（不存在则以 0644 创建；
* offset==0 时先截断，即 push 语义为整文件替换）
* offset : 文件内写入偏移（首次写传 0）
* buf/len : 待写数据（len 会被钳制到 payload pool 容量，
* 实际写入量以 out_written 为准；len=0 仅创建/截断）
* out_written : 本次实际写入字节数（可为 NULL）
* 返回 0 成功，负值失败（错误码同 file_list）。 */
int (*file_write)(const char *path, u64 offset, const char *buf, u64 len,
u64 *out_written);
/* 跨内核文件拉取：Linux 文件 → UTSM FAT32 系统盘根目录（≤256KB，整文件）。
* linux_path : Linux 绝对路径
* fat32_name : UTSM FAT32 根目录文件名（如 "HOSTNAME.TXT"，8.3 可转换）
* out_size : 实际传输字节数（可为 NULL）
* 返回 0 成功，负值失败（-7=文件超过 256KB 暂存上限, -9=无块设备,
* -10=非法 FAT32 名, -12=FAT32 写失败，其余同 file_list）。 */
int (*file_pull)(const char *linux_path, const char *fat32_name,
u64 *out_size);
/* 跨内核文件推送：UTSM FAT32 系统盘根目录 → Linux 文件（≤256KB，整文件替换）。
* fat32_name : UTSM FAT32 根目录文件名（8.3 可转换）
* linux_path : Linux 绝对路径
* out_size : 实际传输字节数（可为 NULL）
* 返回 0 成功，负值失败（-11=文件不存在，其余同 file_pull）。 */
int (*file_push)(const char *fat32_name, const char *linux_path,
u64 *out_size);
} linux_compat_service;
/* ===== UTSM 内部接口（不进服务表，供 hypercall.c 等内核代码使用） =====
*
* UTSM FAT32 系统盘根目录文件访问（经 block_get_api() + fat32_io）。
* name 为普通文件名（内部做 8.3 转换）。
* 返回 0 成功；负值：-9 无块设备, -10 非法文件名, -11 文件不存在,
* -12 磁盘 I/O 错误。 */
int lxc_f32_read_file(const char *name, u8 **out_data, u32 *out_size);
int lxc_f32_write_file(const char *name, const u8 *data, u32 size);
/* 获取全局 Linux 兼容层服务实例指针（UTSM 内部使用，
* 外部通过 boot context reserved[5] 获取）。 */
const linux_compat_service *linux_compat_get_service(void);
CODE/UTSM/include/utsm/linux_loader.h
+8 -2
View File
@@ -135,9 +135,10 @@ struct linux_setup_header {
#define VIRTIO_MMIO_BLK_GPA (VIRTIO_MMIO_GPA_BASE + 0 * VIRTIO_MMIO_GPA_STRIDE) /* 0xF4000000 */
#define VIRTIO_MMIO_NET_GPA (VIRTIO_MMIO_GPA_BASE + 1 * VIRTIO_MMIO_GPA_STRIDE) /* 0xF4001000 */
#define VIRTIO_MMIO_ROOTFS_GPA (VIRTIO_MMIO_GPA_BASE + 2 * VIRTIO_MMIO_GPA_STRIDE) /* 0xF4002000 */
/* 判断 GPA 是否落在 virtio-mmio 设备区（含两端） */
#define VIRTIO_MMIO_GPA_END (VIRTIO_MMIO_GPA_BASE + 2 * VIRTIO_MMIO_GPA_STRIDE)
#define VIRTIO_MMIO_GPA_END (VIRTIO_MMIO_GPA_BASE + 3 * VIRTIO_MMIO_GPA_STRIDE)
#define IS_VIRTIO_MMIO_GPA(gpa) ((gpa) >= VIRTIO_MMIO_GPA_BASE && (gpa) < VIRTIO_MMIO_GPA_END)
/* ===== Linux loader API ===== */
@@ -162,6 +163,10 @@ struct linux_guest_info {
* Sets *size_out to the module size. */
void *linux_find_bzimage_module(u64 *size_out);
/* Find the Arch rootfs image boot module (path contains "rootfs").
* Exposed to Linux guest via memory-backed virtio-blk as /dev/vdb. */
void *linux_find_rootfs_module(u64 *size_out);
/* Parse bzImage header and extract key parameters.
* Returns 0 on success, negative on error. */
int linux_parse_bzimage(const void *bzimage, u64 size,
@@ -194,6 +199,7 @@ int linux_launch(void);
"no_timer_check loglevel=7 nohlt idle=poll " \
"noapic nolapic nosmp " \
"virtio_mmio.device=4K@0xF4000000:5 " \
"virtio_mmio.device=4K@0xF4001000:6"
"virtio_mmio.device=4K@0xF4001000:6 " \
"virtio_mmio.device=4K@0xF4002000:7"
#endif
CODE/UTSM/include/utsm/mm.h
+17
View File
@@ -0,0 +1,17 @@
#ifndef UTSM_MM_H
#define UTSM_MM_H
#include <utsm/types.h>
/* MMIO 映射接口：
* mm_map_mmio 在当前页表（Limine 提供的 CR3）的 MMIO 专用窗口中
* 建立 phys → virt 的 4K 页映射，页属性带 PCD|PWT（等效 UC），
* 适用于任意物理地址（含 4G 以上的 PCI BAR）。
* 返回的虚拟地址包含 phys 的页内偏移；失败返回 0。 */
void *mm_map_mmio(u64 phys, u64 size);
/* 解除 mm_map_mmio 建立的映射（按页清除 PTE + invlpg）。
* 窗口虚拟地址与中间页表页不回收，保留复用。 */
void mm_unmap_mmio(void *virt, u64 size);
#endif
CODE/UTSM/include/utsm/net.h
+12
View File
@@ -58,6 +58,16 @@ typedef struct dkm_net_device_info {
u32 flags;
} dkm_net_device_info;
/* 网络设备统计（真机诊断用，驱动层累计）。 */
typedef struct dkm_net_stats {
u64 tx_ok; /* TX 成功帧数 */
u64 tx_err; /* TX 失败帧数 */
u64 rx_ok; /* RX 成功帧数 */
u64 rx_err; /* RX 错误帧数 */
u64 rx_overflow; /* RX buffer 溢出丢包 */
u64 link_changes; /* 链路状态变化次数 */
} dkm_net_stats;
typedef struct dkm_net_api {
int (*register_device)(const dkm_net_device_desc *desc);
u32 (*device_count)(void);
@@ -69,6 +79,8 @@ typedef struct dkm_net_api {
int (*scan_count)(u32 index);
int (*scan_result)(u32 index, u32 n, dkm_net_scan_result *out);
int (*is_wireless)(u32 index);
/* 网络统计查询（返回 0 成功，-1 索引越界）。 */
int (*device_stats)(u32 index, dkm_net_stats *out);
} dkm_net_api;
void net_init(void);
CODE/UTSM/include/utsm/paging.h
+34
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@@ -0,0 +1,34 @@
#ifndef UTSM_PAGING_H
#define UTSM_PAGING_H
#include <utsm/types.h>
/*
* UTSM 页表/MMIO 映射服务
*
* 背景：内核使用 Limine 建立的页表 + HHDM 直映射访问全部 RAM，
* 但 HHDM 只保证覆盖内存映射中的 RAM 区域，不保证覆盖 4G 以上的
* PCI MMIO 空洞（QEMU/OVMF 常把 NVMe 等 64-bit BAR 分配到 48GiB
* 附近）。本模块提供：
* 1. is_mapped —— 四级页表只读 walk，运行时核实某虚拟地址是否可访问，
* 用于在触碰高位 BAR 前先确认 HHDM 覆盖情况（零 #PF 风险）。
* 2. map_mmio —— 在 Limine 页表的 HHDM 空洞处原地补充 4KiB UC 映射
* （P|RW|PCD|PWT），页表页取自 DMA 物理页分配器（低 4G、4K 对齐、清零）。
*
* SAS-R0 单地址空间模型：不新建地址空间，直接扩展当前 CR3 指向的页表，
* 所有 CPU/驱动立即可见，无切换成本。
*/
typedef struct dkm_mmio_api {
/* 四级页表 walk。返回 0=未映射；1=4K PTE 命中；2=2M PDE 命中；3=1G PDPTE 命中 */
int (*is_mapped)(u64 vaddr);
/* 把物理区间 [phys, phys+size) 映射到 hhdm_offset + phys，4KiB UC 页。
* 已被 Limine 覆盖（含 1G/2M 大页）的页自动跳过。返回 0 成功，负数失败。 */
int (*map_mmio)(u64 phys, u64 size);
/* 当前 CR3 物理地址（诊断用） */
u64 (*cr3)(void);
} dkm_mmio_api;
const dkm_mmio_api *paging_get_api(void);
#endif
CODE/UTSM/include/utsm/virtio_mmio.h
+9
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@@ -153,4 +153,13 @@ int virtio_queue_get_ptrs(u32 device_id, u32 queue_idx,
* 由后端在写 used ring 元素后调用，内部做内存屏障。 */
void virtio_queue_bump_used(struct virtq_used *used, u16 new_idx);
/* 异步触发设备中断（设置 INTERRUPT_STATUS bit0 并向 guest 注入虚拟 IRQ）。
* 用于后端在 QUEUE_NOTIFY 上下文之外完成工作（如周期轮询收到 RX 包）。
* device_id: VIRTIO_ID_*；设备未注册或 irq==0 时为空操作。 */
void virtio_mmio_raise_irq(u32 device_id);
/* 周期轮询 virtio-net RX 路径（填充 guest 已投递的 RX buffer，
* 有填充时自动注入 IRQ）。由 vmexit 的 preemption timer 路径调用。 */
void virtio_net_poll(void);
#endif /* UTSM_VIRTIO_MMIO_H */
CODE/UTSM/kernel/block.d
+5
View File
@@ -0,0 +1,5 @@
kernel/block.o: kernel\block.c include\utsm\block.h include\utsm\types.h \
include\utsm\log.h
include\utsm\block.h:
include\utsm\types.h:
include\utsm\log.h:
CODE/UTSM/kernel/dsk_loader.c
+387 -26
View File
@@ -5,6 +5,7 @@
#include <utsm/types.h>
#include <utsm/pe.h>
#include <utsm/linux_compat.h>
#include <utsm/instr.h>
#include "../arch/x86_64/limine.h"
#define DSK_PATH "/system/deshab64/deshab.elf"
@@ -20,6 +21,27 @@
#define ET_EXEC 2
#define EM_X86_64 62
#define PT_LOAD 1
#define PT_DYNAMIC 2
/* ELF Dynamic section tags */
#define DT_NULL 0
#define DT_RELA 7
#define DT_RELASZ 8
#define DT_RELAENT 9
/* ELF Relocation types */
#define R_X86_64_RELATIVE 8
typedef struct elf64_dyn {
i64 tag;
u64 val;
} elf64_dyn;
typedef struct elf64_rela {
u64 offset;
u64 info;
i64 addend;
} elf64_rela;
void *memset(void *dst, int value, usize len);
void *memcpy(void *dst, const void *src, usize len);
@@ -152,27 +174,86 @@ static struct limine_file *dsk_find_module(void) {
}
/* ---- FAT32 block-provider file reader ---- */
static u8 g_dsk_fat32_disk[65536]; /* 128-sector BPB+FAT+root dir buffer */
static u8 g_dsk_fat32_disk[131072]; /* 256-sector BPB+FAT+root dir buffer (与 DSK 端一致) */
static u8 g_dsk_fat32_cluster[4096]; /* 8-sector cluster buffer */
/* 实机要求: 文件缓冲区足够大容纳 deshab.elf (~1.5MB) */
static u8 g_dsk_fat32_filedata[2097152]; /* 2MB file data buffer */
/* BUG-019 修复: FAT 按需扇区读取缓冲区（仅 512 字节），
* 当 FAT 条目偏移超出 g_dsk_fat32_disk (128KB) 时使用。 */
static u8 g_dsk_fat32_fat_sec[512];
/* BUG-019 修复: 按需读取 FAT 扇区获取下一个簇号。
* 如果目标 FAT 条目在预读缓冲区内，直接读取；
* 否则只读取包含该条目的单个 FAT 扇区（512 字节）。
* fat_start: FAT 在预读缓冲区中的字节偏移（reserved_sectors * 512）。
* clus: 当前簇号。
* bpb: BPB 指针（用于计算 FAT 扇区 LBA）。
* disk: 预读缓冲区基址。
* 返回: 下一个簇号，失败返回 0x0FFFFFFF（链终止）。 */
static u32 fat32_get_next_cluster(u32 fat_start_byte, u32 clus,
const fat32_bpb *bpb, const u8 *disk) {
u32 fat_ent_off = fat_start_byte + clus * 4;
/* 情况 1: FAT 条目在预读缓冲区内（小分区） */
if (fat_ent_off + 4 <= sizeof(g_dsk_fat32_disk)) {
return fat32_read_u32(disk + fat_ent_off) & 0x0FFFFFFF;
}
/* 情况 2: FAT 条目超出预读缓冲区（实机大分区）——按需读取单个 FAT 扇区 */
const dkm_kernel_api *api = dkm_get_kernel_api();
if (!api || !api->block) return 0x0FFFFFFF;
/* FAT 条目在 FAT 表中的字节偏移（相对于 FAT 起始） */
u32 fat_byte_off_in_fat = clus * 4;
/* 该条目所在的 FAT 扇区号（相对于 FAT 起始） */
u32 fat_sec_index = fat_byte_off_in_fat / 512;
/* 条目在扇区内的字节偏移 */
u32 ent_off_in_sec = fat_byte_off_in_fat % 512;
/* FAT 扇区的绝对 LBA */
u32 fat_sec_lba = bpb->reserved_sector_count + fat_sec_index;
int st = api->block->read(0, fat_sec_lba, 1, g_dsk_fat32_fat_sec);
if (st != 0) {
log_error("[UTSM] FAT32: on-demand FAT sector read failed");
log_hex64("[UTSM] FAT32: fat_sec_lba=", fat_sec_lba);
log_hex64("[UTSM] FAT32: clus=", clus);
return 0x0FFFFFFF;
}
return fat32_read_u32(g_dsk_fat32_fat_sec + ent_off_in_sec) & 0x0FFFFFFF;
}
static int dsk_load_from_block_fat32(const void **out_addr, u64 *out_size) {
const dkm_kernel_api *api = dkm_get_kernel_api();
if (!api || !api->block || !api->block->device_count) return -1;
if (!api || !api->block || !api->block->device_count) {
log_error("[UTSM] FAT32: no block api available");
return -1;
}
u32 count = api->block->device_count();
if (count == 0 || api->block->sector_size(0) != 512) return -1;
if (count == 0 || api->block->sector_size(0) != 512) {
log_error("[UTSM] FAT32: no block device or wrong sector size");
log_hex64("[UTSM] FAT32: device_count=", count);
return -1;
}
/* Read first 128 sectors: BPB + FAT + root dir */
/* Read first 256 sectors: BPB + FAT + root dir */
u8 *disk = g_dsk_fat32_disk;
int st = api->block->read(0, 0, 128, disk);
if (st != 0) return -1;
int st = api->block->read(0, 0, 256, disk);
if (st != 0) {
log_error("[UTSM] FAT32: BPB read failed");
log_hex64("[UTSM] FAT32: read status=", (u64)(i64)st);
return -1;
}
const fat32_bpb *bpb = (const fat32_bpb *)disk;
if (bpb->boot_sig != 0xAA55 || bpb->bytes_per_sector != 512) return -1;
if (bpb->boot_sig != 0xAA55 || bpb->bytes_per_sector != 512) {
log_error("[UTSM] FAT32: invalid BPB signature or sector size");
log_hex64("[UTSM] FAT32: boot_sig=", bpb->boot_sig);
log_hex64("[UTSM] FAT32: bps=", bpb->bytes_per_sector);
return -1;
}
u32 fat_start = bpb->reserved_sector_count * 512;
u32 data_start_sec = bpb->reserved_sector_count + (u32)bpb->fat_count * bpb->sectors_per_fat;
log_hex64("[UTSM] FAT32: fat_start_off=", fat_start);
log_hex64("[UTSM] FAT32: data_start_sec=", data_start_sec);
log_hex64("[UTSM] FAT32: spc=", bpb->sectors_per_cluster);
log_hex64("[UTSM] FAT32: root_clus=", bpb->root_cluster);
u32 clus = bpb->root_cluster;
u32 found_clus = 0;
@@ -184,7 +265,12 @@ static int dsk_load_from_block_fat32(const void **out_addr, u64 *out_size) {
u32 cls_sec = bpb->sectors_per_cluster;
u8 *cb = g_dsk_fat32_cluster;
st = api->block->read(0, clus_lba, cls_sec, cb);
if (st != 0) return -1;
if (st != 0) {
log_error("[UTSM] FAT32: dir cluster read failed");
log_hex64("[UTSM] FAT32: clus=", clus);
log_hex64("[UTSM] FAT32: lba=", clus_lba);
return -1;
}
const fat32_dir_entry *dir = (const fat32_dir_entry *)cb;
for (u32 e = 0; e * 32 < cls_sec * 512; e++) {
@@ -194,19 +280,27 @@ static int dsk_load_from_block_fat32(const void **out_addr, u64 *out_size) {
if (dir[e].attr & 0x08) continue;
if (fat32_name11_eq(dir[e].name, target)) {
found_size = dir[e].file_size;
found_clus = fat32_read_u16((const u8 *)&dir[e].cluster_low);
found_clus = fat32_read_u16((const u8 *)&dir[e].cluster_low) |
((u32)fat32_read_u16((const u8 *)&dir[e].cluster_high) << 16);
break;
}
}
if (found_clus) break;
u32 fat_ent = fat_start + clus * 4;
if (fat_ent + 4 > 65536) break;
clus = fat32_read_u32(disk + fat_ent) & 0x0FFFFFFF;
/* BUG-019: 使用按需 FAT 读取，不再受 128KB 缓冲区限制 */
clus = fat32_get_next_cluster(fat_start, clus, bpb, disk);
}
if (!found_clus || found_size == 0) return -1;
if (!found_clus || found_size == 0) {
log_error("[UTSM] FAT32: DESHAB.ELF not found in root dir");
return -1;
}
log_hex64("[UTSM] FAT32: found_clus=", found_clus);
log_hex64("[UTSM] FAT32: found_size=", found_size);
if (found_size > sizeof(g_dsk_fat32_filedata)) return -1;
if (found_size > sizeof(g_dsk_fat32_filedata)) {
log_error("[UTSM] FAT32: file exceeds 2MB buffer");
return -1;
}
u8 *dst = g_dsk_fat32_filedata;
u32 remaining = found_size;
u32 fc = found_clus;
@@ -219,19 +313,27 @@ static int dsk_load_from_block_fat32(const void **out_addr, u64 *out_size) {
u8 *chunk = g_dsk_fat32_cluster;
st = api->block->read(0, fc_lba, fc_sec, chunk);
if (st != 0) return -1;
if (st != 0) {
log_error("[UTSM] FAT32: data cluster read failed");
log_hex64("[UTSM] FAT32: fc=", fc);
log_hex64("[UTSM] FAT32: lba=", fc_lba);
return -1;
}
for (u32 b = 0; b < fc_bytes; b++) dst[b] = chunk[b];
dst += fc_bytes;
remaining -= fc_bytes;
u32 fat_ent = fat_start + fc * 4;
if (fat_ent + 4 > 65536) { fc = 0x0FFFFFFF; break; }
fc = fat32_read_u32(disk + fat_ent) & 0x0FFFFFFF;
/* BUG-019: 使用按需 FAT 读取 */
fc = fat32_get_next_cluster(fat_start, fc, bpb, disk);
}
/* Copy to arena for ELF loader */
u8 *file_buf = (u8 *)kmem_alloc_aligned(found_size, 16);
if (!file_buf) return -1;
if (!file_buf) {
log_error("[UTSM] FAT32: arena alloc failed");
log_hex64("[UTSM] FAT32: size=", found_size);
return -1;
}
for (u32 i = 0; i < found_size; i++) file_buf[i] = g_dsk_fat32_filedata[i];
*out_addr = file_buf;
@@ -240,6 +342,139 @@ static int dsk_load_from_block_fat32(const void **out_addr, u64 *out_size) {
return 0;
}
/* ---- FAT32 subdirectory traversal ---- */
/* 在指定起始 cluster 的目录项中查找 name11。
* is_dir=1 时只匹配子目录（attr & 0x10），is_dir=0 时只匹配文件。
* 返回 0 成功，out_clus/out_size 返回匹配项的起始 cluster 和大小。 */
static int fat32_find_in_dir(u32 start_clus, const char *name11, int is_dir,
u32 *out_clus, u32 *out_size) {
const dkm_kernel_api *api = dkm_get_kernel_api();
if (!api || !api->block || !api->block->device_count) return -1;
u8 *disk = g_dsk_fat32_disk;
const fat32_bpb *bpb = (const fat32_bpb *)disk;
if (bpb->boot_sig != 0xAA55 || bpb->bytes_per_sector != 512) return -2;
u32 fat_start = bpb->reserved_sector_count * 512;
u32 data_start_sec = bpb->reserved_sector_count + (u32)bpb->fat_count * bpb->sectors_per_fat;
u32 spc = bpb->sectors_per_cluster;
u32 clus = start_clus;
while (clus >= 2 && clus < 0x0FFFFFF8) {
u32 clus_lba = data_start_sec + (clus - 2) * spc;
u8 *cb = g_dsk_fat32_cluster;
int st = api->block->read(0, clus_lba, spc, cb);
if (st != 0) return -3;
const fat32_dir_entry *dir = (const fat32_dir_entry *)cb;
for (u32 e = 0; e * 32 < spc * 512; e++) {
if (dir[e].name[0] == 0) break;
if ((u8)dir[e].name[0] == 0xE5) continue;
if (dir[e].attr == 0x0F) continue;
if (dir[e].attr & 0x08) continue;
if (!fat32_name11_eq(dir[e].name, name11)) continue;
/* 名称匹配，检查类型 */
int entry_is_dir = (dir[e].attr & 0x10) ? 1 : 0;
if (entry_is_dir != is_dir) continue;
*out_clus = fat32_read_u16((const u8 *)&dir[e].cluster_low) |
((u32)fat32_read_u16((const u8 *)&dir[e].cluster_high) << 16);
*out_size = dir[e].file_size;
return 0;
}
/* 跟随 FAT 链 — BUG-019: 使用按需 FAT 读取 */
clus = fat32_get_next_cluster(fat_start, clus, bpb, disk);
}
return -4; /* 未找到 */
}
/* 按路径查找文件并读取内容。
* path: '/' 分隔的 8.3 格式路径（如 "SYSTEM /DESHAB64 /FUCK "）。
* out_data: 返回在 g_dsk_fat32_filedata 中的文件数据指针。
* out_size: 返回文件大小。
* 返回 0 成功。 */
int fat32_read_path(const char *path, u8 **out_data, u32 *out_size) {
const dkm_kernel_api *api = dkm_get_kernel_api();
if (!api || !api->block || !api->block->device_count) return -1;
u8 *disk = g_dsk_fat32_disk;
/* 确保 BPB 缓冲区是新鲜的 */
if (api->block->read(0, 0, 256, disk) != 0) return -2;
const fat32_bpb *bpb = (const fat32_bpb *)disk;
if (bpb->boot_sig != 0xAA55 || bpb->bytes_per_sector != 512) return -3;
u32 fat_start = bpb->reserved_sector_count * 512;
u32 data_start_sec = bpb->reserved_sector_count + (u32)bpb->fat_count * bpb->sectors_per_fat;
u32 spc = bpb->sectors_per_cluster;
/* 解析路径组件 */
u32 pos = 0;
u32 path_len = 0;
while (path[path_len]) path_len++;
u32 cur_clus = bpb->root_cluster; /* 从根目录开始 */
while (pos < path_len) {
/* 提取一个路径组件（到下一个 '/' 或结尾） */
char comp[12]; /* 11 字符 8.3 名 + \0 */
u32 ci = 0;
while (pos < path_len && path[pos] != '/' && ci < 11) {
comp[ci++] = path[pos++];
}
/* 不足 11 字符则补空格 */
while (ci < 11) comp[ci++] = ' ';
comp[11] = 0;
/* 跳过 '/' */
if (pos < path_len && path[pos] == '/') pos++;
/* 判断是否为最后一个组件 */
int is_last = (pos >= path_len);
if (is_last) {
/* 最后一级：查找文件 */
u32 found_clus = 0, found_size = 0;
int rc = fat32_find_in_dir(cur_clus, comp, 0, &found_clus, &found_size);
if (rc != 0) return -4;
if (found_size > sizeof(g_dsk_fat32_filedata)) return -5;
/* 读取文件数据 */
u8 *dst = g_dsk_fat32_filedata;
u32 remaining = found_size;
u32 fc = found_clus;
while (fc >= 2 && fc < 0x0FFFFFF8 && remaining > 0) {
u32 fc_lba = data_start_sec + (fc - 2) * spc;
u32 fc_bytes = spc * 512;
if (fc_bytes > remaining) fc_bytes = remaining;
u8 *chunk = g_dsk_fat32_cluster;
if (api->block->read(0, fc_lba, spc, chunk) != 0) return -6;
for (u32 b = 0; b < fc_bytes; b++) dst[b] = chunk[b];
dst += fc_bytes;
remaining -= fc_bytes;
/* BUG-019: 使用按需 FAT 读取 */
fc = fat32_get_next_cluster(fat_start, fc, bpb, disk);
}
*out_data = g_dsk_fat32_filedata;
*out_size = found_size;
return 0;
} else {
/* 中间级：查找子目录 */
u32 sub_clus = 0, sub_size = 0;
int rc = fat32_find_in_dir(cur_clus, comp, 1, &sub_clus, &sub_size);
if (rc != 0) return -7;
cur_clus = sub_clus;
}
}
return -8; /* 路径为空或无效 */
}
/* ---- ELF checks ---- */
static int dsk_check_elf(const void *address, u64 size) {
if (!address || size < sizeof(elf64_ehdr)) return -1;
@@ -263,15 +498,26 @@ static int dsk_load_elf_image(const void *address, u64 size, dsk_entry_fn *entry
u64 max_align = 0x1000;
u32 load_count = 0;
/* PT_DYNAMIC 的位置（PIE 重定位用） */
u64 dyn_off = 0;
u64 dyn_filesz = 0;
int has_dyn = 0;
for (u16 i = 0; i < eh->phnum; i++) {
const elf64_phdr *ph = (const elf64_phdr *)(base + eh->phoff + (u64)i * eh->phentsize);
if (ph->type != PT_LOAD) continue;
if (ph->filesz > ph->memsz) return -1;
if (!range_ok(ph->offset, ph->filesz, size)) return -2;
if (ph->vaddr < min_vaddr) min_vaddr = ph->vaddr;
if (ph->vaddr + ph->memsz > max_vaddr) max_vaddr = ph->vaddr + ph->memsz;
if (ph->align > max_align) max_align = ph->align;
load_count++;
if (ph->type == PT_LOAD) {
if (ph->filesz > ph->memsz) return -1;
if (!range_ok(ph->offset, ph->filesz, size)) return -2;
if (ph->vaddr < min_vaddr) min_vaddr = ph->vaddr;
if (ph->vaddr + ph->memsz > max_vaddr) max_vaddr = ph->vaddr + ph->memsz;
if (ph->align > max_align) max_align = ph->align;
load_count++;
} else if (ph->type == PT_DYNAMIC) {
if (!range_ok(ph->offset, ph->filesz, size)) return -2;
dyn_off = ph->offset;
dyn_filesz = ph->filesz;
has_dyn = 1;
}
}
if (load_count == 0 || min_vaddr == ~0ULL || max_vaddr <= min_vaddr) return -3;
@@ -290,6 +536,44 @@ static int dsk_load_elf_image(const void *address, u64 size, dsk_entry_fn *entry
memcpy(image + dst_off, base + ph->offset, ph->filesz);
}
/* PIE 重定位: 处理 PT_DYNAMIC → DT_RELA → R_X86_64_RELATIVE
* load_bias = image 实际加载地址 - ELF 预期最小 vaddr
* 对每个 R_X86_64_RELATIVE: slot = load_bias + addend */
if (has_dyn && eh->type == ET_DYN) {
u64 load_bias = (u64)image - min_vaddr;
const elf64_dyn *dyn = (const elf64_dyn *)(base + dyn_off);
u64 dyn_count = dyn_filesz / sizeof(elf64_dyn);
u64 rela_off = 0, rela_sz = 0, rela_ent = sizeof(elf64_rela);
for (u64 d = 0; d < dyn_count; d++) {
if (dyn[d].tag == DT_NULL) break;
if (dyn[d].tag == DT_RELA) rela_off = dyn[d].val;
if (dyn[d].tag == DT_RELASZ) rela_sz = dyn[d].val;
if (dyn[d].tag == DT_RELAENT) rela_ent = dyn[d].val;
}
if (rela_off != 0 && rela_sz != 0 && rela_ent != 0) {
/* rela_off 是相对于文件开头的 vaddr，需转换为 image 内偏移 */
if (rela_off >= min_vaddr && rela_off < min_vaddr + image_size) {
u64 rela_count = rela_sz / rela_ent;
for (u64 r = 0; r < rela_count; r++) {
const elf64_rela *rel = (const elf64_rela *)(
image + (rela_off - min_vaddr) + r * rela_ent);
u32 rtype = (u32)rel->info;
if (rtype == R_X86_64_RELATIVE) {
if (rel->offset < min_vaddr || rel->offset >= min_vaddr + image_size) continue;
u64 *slot = (u64 *)(image + (rel->offset - min_vaddr));
*slot = load_bias + (u64)rel->addend;
}
}
}
log_info("[UTSM] PIE reloc applied");
log_hex64("[UTSM] load_bias=", load_bias);
log_hex64("[UTSM] rela_count=", rela_sz / rela_ent);
}
}
*entry_out = (dsk_entry_fn)(image + (eh->entry - min_vaddr));
log_hex64("[UTSM] DSK image base=", (u64)image);
log_hex64("[UTSM] DSK image size=", image_size);
@@ -333,6 +617,24 @@ static void dsk_fill_boot_context(dsk_boot_context *ctx) {
ctx->reserved[5] = (u64)lxc;
}
/* Probe 探测缓冲信息（供 shell $probe 命令读取） */
if (g_instr_enabled) {
probe_info *pi = (probe_info *)kmem_alloc_aligned(sizeof(probe_info), 8);
if (pi) {
pi->magic = PROBE_INFO_MAGIC;
pi->version = 1;
pi->probe_buf_addr = (u64)probe_buf_address();
pi->probe_cap = probe_capacity();
pi->probe_head = probe_head_value();
pi->probe_count = probe_count();
pi->probe_dropped = probe_dropped_count();
pi->instr_enabled = g_instr_enabled;
pi->instr_probe_enable = g_instr_probe_enable;
ctx->reserved[6] = (u64)pi;
ctx->flags |= DSK_BOOT_FLAG_PROBE_INFO;
}
}
u64 rsp;
__asm__ volatile ("movq %%rsp, %0" : "=r"(rsp));
ctx->kernel_stack_top = rsp;
@@ -384,6 +686,65 @@ int dsk_load_and_jump(void) {
}
dsk_fill_boot_context(ctx);
/* 实机安全: 跳转前 cli → mask PIC → 重置 IDT → NMI off。
* DSK 加载的 ELF 映像可能覆盖 UTSM 的驱动代码段,
* 如果 UTSM 注册的 IRQ handler 所在内存被覆盖,
* 中断触发时跳转到无效地址 → 三重故障重启。
*
* P0 修复: 1) 先 cli 禁用中断，消除 PIC mask 两步操作之间的中断竞争窗口
* 2) mask PIC 确保不会有硬件中断到达
* 3) 设置 LAPIC TPR=0xFF 屏蔽所有通过 IOAPIC 路由的中断
* 4) 将 IDT 所有条目替换为安全 halt stub，防止 DSK 运行时
* 过期的 UTSM handler 被异常/spurious IRQ 触发
* 5) 禁用 NMI */
{
extern void outb(u16 port, u8 value);
extern u8 inb(u16 port);
/* 1) 先禁用中断——关键修复！原来缺少此步，
* outb(0xA1,0xFF) 和 outb(0x21,0xFF) 之间有中断窗口 */
__asm__ volatile("cli");
/* 2) mask PIC — 此时 IF=0，安全操作 */
outb(0xA1, 0xFF); /* PIC2: mask IRQ8-15 */
outb(0x21, 0xFF); /* PIC1: mask IRQ0-7 */
/* 3) BUG-020 修复: 设置 LAPIC TPR=0xFF 屏蔽所有 IOAPIC 路由中断。
* 实机多核平台中断通常经 IOAPIC 而非 PIC，PIC mask 不影响
* IOAPIC redirection entry。通过 IA32_APIC_BASE MSR 读取 LAPIC
* 基地址，写入 TPR（偏移 0x80）=0xFF 可在 LAPIC 层面屏蔽所有
* 可屏蔽中断（低于 0xFF 优先级），确保 DSK 运行期间不会有
* IOAPIC 路由的 IRQ 到达。HHDM 映射后 LAPIC MMIO 可访问。 */
{
u32 msr_lo, msr_hi;
__asm__ volatile("rdmsr" : "=a"(msr_lo), "=d"(msr_hi) : "c"(0x1B));
u64 lapic_phys = ((u64)msr_hi << 32) | (msr_lo & 0xFFFFF000ULL);
if (lapic_phys && (msr_lo & (1 << 11))) {
/* LAPIC 全局启用时（bit 11）才操作 TPR */
extern volatile struct limine_hhdm_request g_hhdm_request;
u64 hhdm_off = g_hhdm_request.response
? g_hhdm_request.response->offset : 0;
if (hhdm_off) {
u64 lapic_vaddr = lapic_phys + hhdm_off;
*(volatile u32 *)(lapic_vaddr + 0x80) = 0xFF;
}
}
}
/* 4) 将 IDT 所有 256 个条目替换为安全 halt stub。
* 实机会产生 spurious IRQ7/15（即使 PIC 已 mask），
* 且 SMI/NMI 可能触发异常。如果 UTSM 的 idt_handler
* 所调用的 log 函数或串口驱动被覆盖，会导致双重异常→三重故障。 */
extern void idt_halt_all(void);
idt_halt_all();
/* 5) NMI off */
outb(0x70, inb(0x70) | 0x80);
}
log_hex64("[UTSM] DSK context magic=", ctx->magic);
log_hex64("[UTSM] DSK context api=", ctx->dkm_kernel_api);
log_hex64("[UTSM] DSK context fb=", ctx->framebuffer_address);
log_info("[UTSM] jumping to DSK");
entry(ctx);
CODE/UTSM/kernel/dsk_loader.d
+19
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@@ -0,0 +1,19 @@
kernel/dsk_loader.o: kernel\dsk_loader.c include\utsm\dsk.h \
include\utsm\types.h include\utsm\arena.h include\utsm\dkm.h \
include\utsm\dma.h include\utsm\block.h include\utsm\net.h \
include\utsm\paging.h include\utsm\log.h include\utsm\pe.h \
include\utsm\linux_compat.h include\utsm\instr.h \
kernel\..\arch\x86_64\limine.h
include\utsm\dsk.h:
include\utsm\types.h:
include\utsm\arena.h:
include\utsm\dkm.h:
include\utsm\dma.h:
include\utsm\block.h:
include\utsm\net.h:
include\utsm\paging.h:
include\utsm\log.h:
include\utsm\pe.h:
include\utsm\linux_compat.h:
include\utsm\instr.h:
kernel\..\arch\x86_64\limine.h:
CODE/UTSM/kernel/dsk_loader.o
BIN
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CODE/UTSM/kernel/ini_parser.c
+166
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@@ -0,0 +1,166 @@
/* INI 分区格式解析器 — freestanding, 无堆分配, 无 libc 依赖 */
#include "ini_parser.h"
/* ---- 内部辅助 ---- */
static int ini_streq(const char *a, const char *b) {
if (!a || !b) return 0;
while (*a && *b) {
if (*a != *b) return 0;
a++; b++;
}
return *a == *b;
}
static int ini_isspace(char c) {
return c == ' ' || c == '\t' || c == '\r';
}
static int ini_isdigit(char c) {
return c >= '0' && c <= '9';
}
static int ini_strncpy(char *dst, const char *src, u32 max) {
u32 i = 0;
while (i + 1 < max && src[i]) {
dst[i] = src[i];
i++;
}
dst[i] = 0;
return (int)i;
}
static int ini_atoi(const char *s) {
int neg = 0, v = 0;
if (!s) return 0;
while (ini_isspace(*s)) s++;
if (*s == '-') { neg = 1; s++; }
while (ini_isdigit(*s)) {
v = v * 10 + (*s - '0');
s++;
}
return neg ? -v : v;
}
static int ini_parse_bool(const char *s) {
if (!s) return -1;
if (s[0] == '1') return 1;
if (s[0] == '0') return 0;
if (ini_streq(s, "true")) return 1;
if (ini_streq(s, "false")) return 0;
if (ini_streq(s, "yes")) return 1;
if (ini_streq(s, "no")) return 0;
return -1;
}
/* ---- 公共接口 ---- */
int ini_parse(const char *text, u32 size, ini_config *cfg) {
if (!text || !cfg) return -1;
cfg->count = 0;
char cur_section[32] = {0}; /* 当前分区名，默认空 */
u32 pos = 0;
while (pos < size) {
/* 跳过行首空白 */
while (pos < size && (text[pos] == ' ' || text[pos] == '\t'))
pos++;
if (pos >= size) break;
char c = text[pos];
/* 空行或换行 */
if (c == '\n') { pos++; continue; }
/* 注释行: # 或 ; 开头 */
if (c == '#' || c == ';') {
while (pos < size && text[pos] != '\n') pos++;
continue;
}
/* 分区头: [section] */
if (c == '[') {
pos++; /* 跳过 '[' */
u32 si = 0;
while (pos < size && text[pos] != ']' && text[pos] != '\n' && si + 1 < 32) {
cur_section[si++] = text[pos++];
}
cur_section[si] = 0;
/* 跳过到行尾 */
while (pos < size && text[pos] != '\n') pos++;
continue;
}
/* key=value 行 */
if (cfg->count >= 64) break; /* 达到上限 */
ini_entry *e = &cfg->entries[cfg->count];
/* 读取 key */
u32 ki = 0;
while (pos < size && text[pos] != '=' && text[pos] != '\n' &&
!ini_isspace(text[pos]) && ki + 1 < 32) {
e->key[ki++] = text[pos++];
}
e->key[ki] = 0;
/* 跳过 key 和 '=' 之间的空白 */
while (pos < size && ini_isspace(text[pos]) && text[pos] != '\n')
pos++;
/* 期望 '=' */
if (pos >= size || text[pos] != '=') {
/* 无效行，跳到行尾 */
while (pos < size && text[pos] != '\n') pos++;
continue;
}
pos++; /* 跳过 '=' */
/* 跳过 '=' 后的空白 */
while (pos < size && ini_isspace(text[pos]) && text[pos] != '\n')
pos++;
/* 读取 value（到行尾，去除尾部空白） */
u32 vi = 0;
while (pos < size && text[pos] != '\n' && vi + 1 < 64) {
e->value[vi++] = text[pos++];
}
/* 去除尾部空白 */
while (vi > 0 && ini_isspace(e->value[vi - 1])) vi--;
e->value[vi] = 0;
/* 复制 section 名 */
ini_strncpy(e->section, cur_section, 32);
cfg->count++;
}
return 0;
}
const char *ini_get(const ini_config *cfg, const char *section, const char *key) {
if (!cfg || !section || !key) return NULL;
for (u32 i = 0; i < cfg->count; i++) {
if (ini_streq(cfg->entries[i].section, section) &&
ini_streq(cfg->entries[i].key, key)) {
return cfg->entries[i].value;
}
}
return NULL;
}
int ini_get_int(const ini_config *cfg, const char *section, const char *key, int defval) {
const char *v = ini_get(cfg, section, key);
if (!v || v[0] == 0) return defval;
return ini_atoi(v);
}
int ini_get_bool(const ini_config *cfg, const char *section, const char *key, int defval) {
const char *v = ini_get(cfg, section, key);
if (!v || v[0] == 0) return defval;
int b = ini_parse_bool(v);
return (b >= 0) ? b : defval;
}
CODE/UTSM/kernel/ini_parser.d
+4
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@@ -0,0 +1,4 @@
kernel/ini_parser.o: kernel\ini_parser.c kernel\ini_parser.h \
include\utsm\types.h
kernel\ini_parser.h:
include\utsm\types.h:
CODE/UTSM/kernel/ini_parser.h
+38
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@@ -0,0 +1,38 @@
#ifndef UTSM_INI_PARSER_H
#define UTSM_INI_PARSER_H
#include <utsm/types.h>
/* INI 配置条目 */
typedef struct {
char section[32];
char key[32];
char value[64];
} ini_entry;
/* INI 配置集合（栈/静态分配，不依赖堆） */
typedef struct {
ini_entry entries[64]; /* 最多 64 条配置项 */
u32 count;
} ini_config;
/* 解析 INI 文本到 ini_config。
* text: INI 文本起始地址
* size: 文本字节长度
* cfg: 输出配置集合
* 返回 0 成功，负数失败 */
int ini_parse(const char *text, u32 size, ini_config *cfg);
/* 在 section 下查找 key，返回 value 字符串。
* 未找到返回 NULL。 */
const char *ini_get(const ini_config *cfg, const char *section, const char *key);
/* 便捷查询：返回整数值。
* 未找到或格式错误返回 defval。 */
int ini_get_int(const ini_config *cfg, const char *section, const char *key, int defval);
/* 便捷查询：返回布尔值。
* "0"/"false" = 0, "1"/"true" = 1，未找到返回 defval。 */
int ini_get_bool(const ini_config *cfg, const char *section, const char *key, int defval);
#endif /* UTSM_INI_PARSER_H */
CODE/UTSM/kernel/instr.c
+95
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@@ -0,0 +1,95 @@
/* instr.c — Deshab 插桩系统初始化与全局配置管理
*
* 从 FUCK [debug] 配置段加载插桩参数，初始化全局配置变量。
* 在 kernel_main() 中调用 instr_init(&g_boot_cfg) 启用。
*/
#include <utsm/instr.h>
#include <utsm/log.h>
#include <utsm/types.h>
#include "ini_parser.h"
/* ---- 全局配置变量（供 instr.h 宏条件判断） ---- */
u32 g_instr_enabled = 0;
u32 g_instr_log_level = INSTR_LOG_INFO;
u32 g_instr_probe_enable = 0;
u32 g_instr_stat_interval = 256;
u32 g_instr_module_flags = 0;
u64 instr_tsc_per_ms = 0;
/* ---- 低级 I/O（TSC 校准用，与 arch/x86_64/io.c 独立避免链接冲突） ---- */
static void instr_outb(u16 port, u8 value) {
__asm__ volatile("outb %0, %1" :: "a"(value), "Nd"(port));
}
static u8 instr_inb(u16 port) {
u8 value;
__asm__ volatile("inb %1, %0" : "=a"(value) : "Nd"(port));
return value;
}
/* TSC 读取 */
u64 instr_rdtsc(void) {
u32 lo, hi;
__asm__ volatile("rdtsc" : "=a"(lo), "=d"(hi));
return ((u64)hi << 32) | lo;
}
/* TSC 校准：PIT ch0 ~10ms 区间，与 serial.c / dkm_shared.h 相同逻辑 */
static void instr_tsc_calibrate(void) {
instr_outb(0x43, 0x30); /* ch0, lo+hi, mode 0, binary */
instr_outb(0x40, 0x7c); /* 11932 low = ~10ms */
instr_outb(0x40, 0x2e); /* 11932 high */
u64 tsc_start = instr_rdtsc();
u16 prev = 0;
u64 loops = 0;
for (;;) {
instr_outb(0x43, 0x00);
u16 cur = (u16)instr_inb(0x40) | ((u16)instr_inb(0x40) << 8);
if (cur > prev && loops > 10) break;
prev = cur;
loops++;
}
u64 tsc_end = instr_rdtsc();
instr_tsc_per_ms = (tsc_end - tsc_start) / 10;
}
void instr_init(const void *cfg_ptr) {
const ini_config *cfg = (const ini_config *)cfg_ptr;
/* 从 FUCK [debug] 段读取配置 */
g_instr_enabled = (u32)ini_get_bool(cfg, "debug", "enabled", 0);
g_instr_log_level = (u32)ini_get_int(cfg, "debug", "log_level", INSTR_LOG_INFO);
g_instr_probe_enable = (u32)ini_get_bool(cfg, "debug", "probe_enable", 0);
g_instr_stat_interval = (u32)ini_get_int(cfg, "debug", "stat_summary_interval", 256);
/* 模块级过滤标志 */
g_instr_module_flags = 0;
if (ini_get_bool(cfg, "debug", "utsm_trace", 0))
g_instr_module_flags |= INSTR_F_UTSM_TRACE;
if (ini_get_bool(cfg, "debug", "vmm_trace", 0))
g_instr_module_flags |= INSTR_F_VMM_TRACE;
if (ini_get_bool(cfg, "debug", "dkm_trace", 0))
g_instr_module_flags |= INSTR_F_DKM_TRACE;
if (ini_get_bool(cfg, "debug", "dsk_trace", 0))
g_instr_module_flags |= INSTR_F_DSK_TRACE;
if (ini_get_bool(cfg, "debug", "block_trace", 0))
g_instr_module_flags |= INSTR_F_BLOCK_TRACE;
if (ini_get_bool(cfg, "debug", "net_trace", 0))
g_instr_module_flags |= INSTR_F_NET_TRACE;
if (ini_get_bool(cfg, "debug", "input_trace", 0))
g_instr_module_flags |= INSTR_F_INPUT_TRACE;
/* 校准 TSC（独立于 serial.c 的校准，供插桩时间戳使用） */
instr_tsc_calibrate();
/* 初始化探测缓冲 */
probe_init(cfg);
/* 输出初始化状态 */
if (g_instr_enabled) {
log_info("[INSTR] enabled");
log_hex64("[INSTR] log_level=", g_instr_log_level);
log_hex64("[INSTR] probe_enable=", g_instr_probe_enable);
log_hex64("[INSTR] module_flags=", g_instr_module_flags);
log_hex64("[INSTR] tsc_per_ms=", instr_tsc_per_ms);
}
}
CODE/UTSM/kernel/instr.d
+6
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@@ -0,0 +1,6 @@
kernel/instr.o: kernel\instr.c include\utsm\instr.h include\utsm\types.h \
include\utsm\log.h kernel\ini_parser.h
include\utsm\instr.h:
include\utsm\types.h:
include\utsm\log.h:
kernel\ini_parser.h:
CODE/UTSM/kernel/log.d
+3
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@@ -0,0 +1,3 @@
kernel/log.o: kernel\log.c include\utsm\log.h include\utsm\types.h
include\utsm\log.h:
include\utsm\types.h:
CODE/UTSM/kernel/main.c
+267 -51
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@@ -9,94 +9,310 @@
#include <utsm/net.h>
#include <utsm/ipc_shm.h>
#include <utsm/linux_compat.h>
#include <utsm/instr.h>
#include "ini_parser.h"
#include "../arch/x86_64/limine.h"
void arch_halt_forever(void);
extern volatile struct limine_module_request g_module_request;
/* dkm/manifest.c: 带 FUCK [drivers] 过滤的 manifest 加载入口 */
void dsm_load_by_manifest_ex(const ini_config *cfg);
/* ---- 运行期配置全局变量（从 FUCK 文件初始化） ---- */
u32 g_utsm_max_segments = UTSM_MAX_SEGMENTS_DEFAULT;
u32 g_utsm_max_capabilities = UTSM_MAX_CAPABILITIES_DEFAULT;
u32 g_utsm_max_pckc_keys = UTSM_MAX_PCKC_KEYS_DEFAULT;
u64 g_utsm_arena_size = UTSM_ARENA_SIZE_DEFAULT;
u64 g_utsm_dirty_shard_pages = UTSM_DIRTY_SHARD_PAGES_DEFAULT;
/* 将 FUCK [utsm] 区的配置应用到运行期全局变量 */
static void utsm_apply_config(const ini_config *cfg) {
if (!cfg) return;
g_utsm_max_segments = (u32)ini_get_int(cfg, "utsm", "max_segments", UTSM_MAX_SEGMENTS_DEFAULT);
g_utsm_max_capabilities = (u32)ini_get_int(cfg, "utsm", "max_capabilities", UTSM_MAX_CAPABILITIES_DEFAULT);
g_utsm_max_pckc_keys = (u32)ini_get_int(cfg, "utsm", "max_pckc_keys", UTSM_MAX_PCKC_KEYS_DEFAULT);
g_utsm_arena_size = (u64)ini_get_int(cfg, "utsm", "arena_size_mb", 16) * 1024 * 1024;
g_utsm_dirty_shard_pages = (u64)ini_get_int(cfg, "utsm", "dirty_shard_pages", UTSM_DIRTY_SHARD_PAGES_DEFAULT);
log_info("[UTSM] FUCK config applied");
log_hex64("[UTSM] max_segments=", g_utsm_max_segments);
log_hex64("[UTSM] max_pckc_keys=", g_utsm_max_pckc_keys);
log_hex64("[UTSM] dirty_shard_pages=", g_utsm_dirty_shard_pages);
}
/* ---- 全局启动配置（从 FUCK 文件读取） ---- */
static ini_config g_boot_cfg;
static int g_boot_cfg_loaded = 0;
/* 从 Limine boot module 读取 FUCK 配置。
* cmdline="fuck:config" 的模块即为 FUCK 配置文件。
* 返回 0 成功，负数失败。 */
static int utsm_load_fuck_config(ini_config *cfg) {
struct limine_module_response *rsp = g_module_request.response;
if (!rsp) return -1;
for (u64 i = 0; i < rsp->module_count; i++) {
struct limine_file *f = rsp->modules[i];
if (f && f->cmdline) {
/* 比较 cmdline 是否为 "fuck:config" */
const char *c = f->cmdline;
const char *tag = "fuck:config";
int match = 1;
for (int j = 0; tag[j]; j++) {
if (c[j] != tag[j]) { match = 0; break; }
}
if (match && c[11] == 0) {
int rc = ini_parse((const char *)f->address, (u32)f->size, cfg);
if (rc == 0) {
log_info("[UTSM] FUCK config loaded from boot module");
return 0;
}
}
}
}
log_warn("[UTSM] FUCK boot module not found");
return -2;
}
void kernel_main(void) {
/* ---- 插桩: 启动总时间戳 ---- */
INSTR_TS_DECL(boot_total);
INSTR_TS_BEGIN(boot_total);
serial_init();
log_info("[UTSM] boot");
/* ==== 真机硬件特征早期检测 (在任何初始化之前) ====
* 检测项目:
* 1. CPU vendor (GenuineIntel / AuthenticAMD / etc.)
* 2. 最大物理地址宽度 (CPUID.80000008H:EAX[7:0])
* 3. LA57 (5-level paging) 是否激活 → 拒绝启动
* 4. CPU 核心数 (CPUID.0BH 或 CPUID.01H)
* 5. PCIe MCFG 可用性 (后续由 ACPI 驱动检测)
*
* **QEMU 无法测试但真机必需的代码路径**:
* - LA57 拒绝: QEMU 默认不启用 5 级分页
* - 物理地址宽度 > 48: 只有大内存真机才有
* - AMD CPU vendor: QEMU 默认 Intel, 实机可能是 AMD
* - 多核: QEMU -smp 可以模拟, 但真机拓扑更复杂
*/
{
/* CPU vendor */
u32 a, b, c, d;
__asm__ volatile("cpuid" : "=a"(a), "=b"(b), "=c"(c), "=d"(d) : "a"(0), "c"(0));
char vendor[13];
vendor[0] = (char)(b & 0xff);
vendor[1] = (char)((b >> 8) & 0xff);
vendor[2] = (char)((b >> 16) & 0xff);
vendor[3] = (char)((b >> 24) & 0xff);
vendor[4] = (char)(d & 0xff);
vendor[5] = (char)((d >> 8) & 0xff);
vendor[6] = (char)((d >> 16) & 0xff);
vendor[7] = (char)((d >> 24) & 0xff);
vendor[8] = (char)(c & 0xff);
vendor[9] = (char)((c >> 8) & 0xff);
vendor[10] = (char)((c >> 16) & 0xff);
vendor[11] = (char)((c >> 24) & 0xff);
vendor[12] = 0;
log_info("[UTSM] CPU vendor: ");
log_info(vendor);
/* Max physical address width */
__asm__ volatile("cpuid" : "=a"(a), "=b"(b), "=c"(c), "=d"(d) : "a"(0x80000000), "c"(0));
if (a >= 0x80000008) {
__asm__ volatile("cpuid" : "=a"(a), "=b"(b), "=c"(c), "=d"(d) : "a"(0x80000008), "c"(0));
u32 phys_bits = a & 0xff;
u32 virt_bits = (a >> 8) & 0xff;
log_hex64("[UTSM] MaxPhysAddr bits=", phys_bits);
log_hex64("[UTSM] MaxVirtAddr bits=", virt_bits);
}
/* LA57 early detection — 在 CR4 读之前先通过 CPUID 检查是否支持 */
__asm__ volatile("cpuid" : "=a"(a), "=b"(b), "=c"(c), "=d"(d) : "a"(7), "c"(0));
if (c & (1u << 16)) {
log_warn("[UTSM] CPU supports LA57 (5-level paging)");
/* 检查 CR4 是否实际启用了 LA57 */
u64 cr4;
__asm__ volatile("mov %%cr4, %0" : "=r"(cr4));
if (cr4 & (1ULL << 12)) {
log_error("[UTSM] LA57 is ACTIVE — this kernel requires 4-level paging");
log_error("[UTSM] Refusing to boot. Disable LA57 in firmware settings.");
arch_halt_forever();
}
}
/* CPU core count — CPUID leaf 0BH (Intel Extended Topology) */
__asm__ volatile("cpuid" : "=a"(a), "=b"(b), "=c"(c), "=d"(d) : "a"(0), "c"(0));
if (a >= 0x0B) {
/* 尝试 level 0 获取 SMT 核心数 */
u32 level_type = 0, cores = 0;
__asm__ volatile("cpuid" : "=a"(a), "=b"(b), "=c"(c), "=d"(d) : "a"(0x0B), "c"(0));
level_type = (c >> 8) & 0xff;
cores = b & 0xffff;
if (level_type == 1 && cores > 0) {
log_hex64("[UTSM] SMT threads=", cores);
}
__asm__ volatile("cpuid" : "=a"(a), "=b"(b), "=c"(c), "=d"(d) : "a"(0x0B), "c"(1));
level_type = (c >> 8) & 0xff;
cores = b & 0xffff;
if (level_type == 2 && cores > 0) {
log_hex64("[UTSM] logical processors=", cores);
}
} else {
/* fallback: CPUID.01H EBX[23:16] */
__asm__ volatile("cpuid" : "=a"(a), "=b"(b), "=c"(c), "=d"(d) : "a"(1), "c"(0));
u32 lc = (b >> 16) & 0xff;
log_hex64("[UTSM] logical processors (legacy)=", lc);
}
/* ---- 插桩: CPU 检测完成，记录 vendor ---- */
INSTR_PROBE(BOOT, (u64)vendor[0] | ((u64)vendor[1] << 8), 0, 0, 0);
}
/* ---- 插桩: IDT 初始化耗时 ---- */
INSTR_TS_DECL(ts_idt);
INSTR_TS_BEGIN(ts_idt);
idt_init();
INSTR_TS_END(ts_idt, "idt_init");
/* === 读取 FUCK 配置（通过 Limine boot module 预加载） === */
g_boot_cfg_loaded = (utsm_load_fuck_config(&g_boot_cfg) == 0);
ini_config *cfg = g_boot_cfg_loaded ? &g_boot_cfg : NULL;
/* ---- 插桩: FUCK 配置加载完成 ---- */
INSTR_PROBE(BOOT, (u64)g_boot_cfg_loaded, 0, 0, 0);
/* === 初始化插桩系统（在 arena_init 之前，但需要 FUCK 配置） === */
/* 注意: probe_init 需要 arena，所以 instr_init 必须在 arena_init 之后。
* 此处先设置 g_instr_enabled 等全局变量，probe_init 延后到 arena 后。
* 实际上 instr_init 内部会调用 probe_init，而 probe_init 需要 kmem_alloc。
* 所以我们将 instr_init 移到 arena_init 之后。*/
/* === 应用 UTSM 算法参数到运行期全局变量 === */
utsm_apply_config(cfg);
log_info("[UTSM] arena init begin");
INSTR_TS_DECL(ts_arena);
INSTR_TS_BEGIN(ts_arena);
arena_init();
INSTR_TS_END(ts_arena, "arena_init");
log_info("[UTSM] arena init ok");
/* ---- 插桩: arena 就绪后初始化插桩系统（含探测缓冲分配） ---- */
instr_init(cfg);
log_info("[UTSM] dma init begin");
INSTR_TS_DECL(ts_dma);
INSTR_TS_BEGIN(ts_dma);
dma_init();
INSTR_TS_END(ts_dma, "dma_init");
log_info("[UTSM] dma init ok");
log_info("[UTSM] net registry init begin");
INSTR_TS_DECL(ts_net);
INSTR_TS_BEGIN(ts_net);
net_init();
INSTR_TS_END(ts_net, "net_init");
log_info("[UTSM] net registry init ok");
log_info("[UTSM] drr init begin");
INSTR_TS_DECL(ts_drr);
INSTR_TS_BEGIN(ts_drr);
drr_init();
INSTR_TS_END(ts_drr, "drr_init");
log_info("[UTSM] drr init ok");
log_info("[UTSM] core init begin");
INSTR_TS_DECL(ts_utsm);
INSTR_TS_BEGIN(ts_utsm);
utsm_init();
INSTR_TS_END(ts_utsm, "utsm_init");
log_info("[UTSM] init ok");
INSTR_TS_DECL(ts_dkm);
INSTR_TS_BEGIN(ts_dkm);
dkm_init();
dkm_fill_platform_info();
dsm_load_by_manifest();
INSTR_TS_END(ts_dkm, "dkm_init");
int result = utsm_selftest_run();
if (result == 0) {
log_info("[UTSM] SELFTEST PASS");
/* === 驱动加载 — 按 [drivers] 区过滤 === */
INSTR_TS_DECL(ts_dsm);
INSTR_TS_BEGIN(ts_dsm);
dsm_load_by_manifest_ex(cfg);
INSTR_TS_END(ts_dsm, "dsm_load_manifest");
/* Phase 1.1: VMM (VMX/EPT) 初始化 + 自检
* 若 VMX 不可用（如 QEMU 未启用），仅警告，不阻断 DSK 启动 */
if (vmm_init() == 0) {
log_info("[UTSM] VMM init ok");
int vmm_st = vmm_self_test();
if (vmm_st == 0) {
log_info("[UTSM] VMM self-test PASS");
/* Phase 1.2: Linux 加载器 + 启动
* 若 bzImage 模块存在，加载并启动 Linux guest。
* 若无 bzImage，跳过 Linux 启动，继续 DSK 流程。 */
if (linux_loader_init() == 0) {
log_info("[UTSM] Linux loader init ok");
/* Phase 1.3: Initialize IPC shared memory before
* launching Linux. Allocates 1MB, initializes ring
* buffers, and EPT-maps at GPA 0x04000000 so the
* Linux guest can access it via UTSM_HCALL_SHM_INFO. */
if (ipc_shm_init() == 0) {
log_info("[UTSM] IPC shm init ok");
} else {
log_error("[UTSM] IPC shm init failed (non-fatal)");
}
int lin_st = linux_launch();
if (lin_st == 0) {
log_info("[UTSM] Linux guest parked (daemon ready)");
/* Phase 3.2: 初始化 Linux 兼容层服务
* （需在 linux_launch 成功 + guest park 后调用） */
linux_compat_init();
} else {
log_error("[UTSM] Linux launch failed");
log_hex64("[UTSM] Linux st=", (u64)(i64)lin_st);
}
} else {
log_warn("[UTSM] Linux loader unavailable (no bzImage)");
}
} else {
log_error("[UTSM] VMM self-test FAIL");
log_hex64("[UTSM] VMM st=", (u64)(i64)vmm_st);
}
/* === selftest — 可通过 FUCK [boot] selftest=0 跳过 === */
int run_selftest = ini_get_bool(cfg, "boot", "selftest", 1);
if (run_selftest) {
INSTR_TS_DECL(ts_self);
INSTR_TS_BEGIN(ts_self);
int result = utsm_selftest_run();
INSTR_TS_END(ts_self, "selftest");
if (result == 0) {
log_info("[UTSM] SELFTEST PASS");
} else {
log_warn("[UTSM] VMM unavailable (VMX not supported or disabled)");
}
if (dsk_load_and_jump() != 0) {
log_error("[UTSM] DSK jump failed");
log_error("[UTSM] SELFTEST FAIL");
arch_halt_forever();
}
} else {
log_error("[UTSM] SELFTEST FAIL");
log_info("[UTSM] selftest skipped by FUCK config");
}
/* === VMM — 可通过 FUCK [boot] vmm=0 跳过 === */
int run_vmm = ini_get_bool(cfg, "boot", "vmm", 1);
if (run_vmm && vmm_init() == 0) {
INSTR_TS_DECL(ts_vmm);
INSTR_TS_BEGIN(ts_vmm);
log_info("[UTSM] VMM init ok");
int vmm_st = vmm_self_test();
if (vmm_st == 0) {
INSTR_TS_END(ts_vmm, "vmm_init+selftest");
log_info("[UTSM] VMM self-test PASS");
/* === Linux guest — 可通过 FUCK [boot] linux_guest=0 跳过 === */
int run_linux = ini_get_bool(cfg, "boot", "linux_guest", 1);
if (run_linux && linux_loader_init() == 0) {
INSTR_TS_DECL(ts_linux);
INSTR_TS_BEGIN(ts_linux);
log_info("[UTSM] Linux loader init ok");
if (ipc_shm_init() == 0) {
log_info("[UTSM] IPC shm init ok");
} else {
log_error("[UTSM] IPC shm init failed (non-fatal)");
}
int lin_st = linux_launch();
INSTR_TS_END(ts_linux, "linux_launch");
if (lin_st == 0) {
log_info("[UTSM] Linux guest parked (daemon ready)");
linux_compat_init();
} else {
log_error("[UTSM] Linux launch failed");
log_hex64("[UTSM] Linux st=", (u64)(i64)lin_st);
}
} else {
log_warn("[UTSM] Linux loader unavailable (no bzImage or disabled)");
}
} else {
INSTR_TS_END(ts_vmm, "vmm_init+selftest");
log_error("[UTSM] VMM self-test FAIL");
log_hex64("[UTSM] VMM st=", (u64)(i64)vmm_st);
}
} else {
log_warn("[UTSM] VMM unavailable (VMX not supported or disabled by FUCK)");
}
/* ---- 插桩: DSK 加载跳转前记录 ---- */
INSTR_PROBE(DSK0, 0, 0, 0, 0);
if (dsk_load_and_jump() != 0) {
log_error("[UTSM] DSK jump failed");
}
/* ---- 插桩: 启动总耗时（仅在 DSK 跳转失败时可见） ---- */
INSTR_TS_END(boot_total, "boot_total");
arch_halt_forever();
}
CODE/UTSM/kernel/main.d
+40
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@@ -0,0 +1,40 @@
kernel/main.o: kernel\main.c include\utsm\log.h include\utsm\types.h \
include\utsm\arena.h include\utsm\utsm.h include\utsm\status.h \
include\utsm\config.h include\utsm\uuid.h include\utsm\process.h \
include\utsm\capability.h include\utsm\segment.h include\utsm\dirty.h \
include\utsm\utrw.h include\utsm\vmm.h include\utsm\linux_loader.h \
include\utsm\ipc_shm.h ..\utsm-ipc\ipc_proto.h \
include\utsm\hypercall.h include\utsm\drr.h include\utsm\dkm.h \
include\utsm\dma.h include\utsm\block.h include\utsm\net.h \
include\utsm\paging.h include\utsm\idt.h include\utsm\dsk.h \
include\utsm\linux_compat.h include\utsm\instr.h kernel\ini_parser.h \
kernel\..\arch\x86_64\limine.h
include\utsm\log.h:
include\utsm\types.h:
include\utsm\arena.h:
include\utsm\utsm.h:
include\utsm\status.h:
include\utsm\config.h:
include\utsm\uuid.h:
include\utsm\process.h:
include\utsm\capability.h:
include\utsm\segment.h:
include\utsm\dirty.h:
include\utsm\utrw.h:
include\utsm\vmm.h:
include\utsm\linux_loader.h:
include\utsm\ipc_shm.h:
..\utsm-ipc\ipc_proto.h:
include\utsm\hypercall.h:
include\utsm\drr.h:
include\utsm\dkm.h:
include\utsm\dma.h:
include\utsm\block.h:
include\utsm\net.h:
include\utsm\paging.h:
include\utsm\idt.h:
include\utsm\dsk.h:
include\utsm\linux_compat.h:
include\utsm\instr.h:
kernel\ini_parser.h:
kernel\..\arch\x86_64\limine.h:
CODE/UTSM/kernel/main.o
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CODE/UTSM/kernel/net.c
+16 -2
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@@ -52,7 +52,6 @@ static int net_tx_impl(u32 index, const void *packet, u32 length) {
if (index >= g_net_device_count) return -2;
const dkm_net_device_desc *dev = &g_net_devices[index];
if (!dev->tx) return -3;
log_hex64("[NET] tx dispatch fn=", (u64)dev->tx);
return dev->tx(dev->ctx, packet, length);
}
@@ -92,6 +91,20 @@ static int net_is_wireless_impl(u32 index) {
return (dev->flags & DKM_NET_F_WIRELESS) ? 1 : 0;
}
/* 统计查询：返回驱动层累计的收发统计。
* 当前实现为占位：返回全零统计。
* 后续由驱动在 tx/rx 回调内更新共享统计区，此处直接读取。
* 驱动层的本地统计（如 e1000 的 g_stat_tx_ok 等）与 netdev 层统计
* 通过 driver_ctx 统一后即可返回精确值。 */
static int net_device_stats_impl(u32 index, dkm_net_stats *out) {
if (!out) return -1;
if (index >= g_net_device_count) return -2;
/* 占位：全零。后续由驱动填充实际统计。 */
for (u32 i = 0; i < sizeof(dkm_net_stats); i++)
((u8 *)out)[i] = 0;
return 0;
}
static const dkm_net_api g_net_api = {
.register_device = net_register_device_impl,
.device_count = net_device_count_impl,
@@ -101,7 +114,8 @@ static const dkm_net_api g_net_api = {
.scan_start = net_scan_start_impl,
.scan_count = net_scan_count_impl,
.scan_result = net_scan_result_impl,
.is_wireless = net_is_wireless_impl
.is_wireless = net_is_wireless_impl,
.device_stats = net_device_stats_impl
};
const dkm_net_api *net_get_api(void) {
CODE/UTSM/kernel/net.d
+5
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@@ -0,0 +1,5 @@
kernel/net.o: kernel\net.c include\utsm\net.h include\utsm\types.h \
include\utsm\log.h
include\utsm\net.h:
include\utsm\types.h:
include\utsm\log.h:
CODE/UTSM/kernel/net.o
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CODE/UTSM/kernel/panic.d
+3
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@@ -0,0 +1,3 @@
kernel/panic.o: kernel\panic.c include\utsm\log.h include\utsm\types.h
include\utsm\log.h:
include\utsm\types.h:
CODE/UTSM/kernel/probe.c
+111
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@@ -0,0 +1,111 @@
/* probe.c — Deshab 环形探测缓冲管理
*
* 结构化事件记录系统：写入环形缓冲，支持事后回溯分析。
* 用于记录关键事件（CPU异常、EPT violation、DMA完成等），
* 通过 shell $probe 命令读取。
*
* 设计要点:
* - 环形缓冲容量由 FUCK debug.probe_capacity 控制（默认 4096 条）
* - 每条记录 40 字节 (tag:4 + tick:4 + args:4*8)
* - 写入时无内存分配，仅 head 指针推进
* - 满时覆盖最旧记录（环形覆盖）
* - 禁用时 probe_write 为空操作
*/
#include <utsm/instr.h>
#include <utsm/log.h>
#include <utsm/types.h>
#include <utsm/arena.h>
#include "ini_parser.h"
/* ---- 探测缓冲状态 ---- */
static probe_entry *g_probe_buf = 0; /* 缓冲基地址（arena 分配） */
static u32 g_probe_cap = 0; /* 缓冲容量（条目数） */
static u32 g_probe_head = 0; /* 下一条写入位置（递增取模） */
static u32 g_probe_count = 0; /* 已写入总条目数 */
static u32 g_probe_dropped = 0; /* 因缓冲满而覆盖的条目数 */
void probe_init(const void *cfg_ptr) {
const ini_config *cfg = (const ini_config *)cfg_ptr;
u32 cap = (u32)ini_get_int(cfg, "debug", "probe_capacity", 4096);
if (cap == 0) {
g_instr_probe_enable = 0;
return;
}
/* 从 arena 分配探测缓冲（对齐到 8 字节） */
u64 size = (u64)cap * sizeof(probe_entry);
g_probe_buf = (probe_entry *)kmem_alloc_aligned(size, 8);
if (!g_probe_buf) {
g_instr_probe_enable = 0;
log_warn("[PROBE] arena alloc failed, probe disabled");
return;
}
g_probe_cap = cap;
g_probe_head = 0;
g_probe_count = 0;
g_probe_dropped = 0;
log_info("[PROBE] init ok, capacity=");
log_hex64("", g_probe_cap);
}
void probe_write(u32 tag, u64 a0, u64 a1, u64 a2, u64 a3) {
if (!g_probe_buf || !g_probe_cap) return;
u32 idx = g_probe_head % g_probe_cap;
/* 环形覆盖：如果 head >= cap，说明有旧记录被覆盖 */
if (g_probe_head >= g_probe_cap && g_probe_dropped == 0) {
/* 仅首次覆盖时计数，避免每条都做减法 */
}
if (g_probe_count >= g_probe_cap) {
g_probe_dropped++;
}
g_probe_buf[idx].tag = tag;
g_probe_buf[idx].tick = (u32)instr_rdtsc();
g_probe_buf[idx].args[0] = a0;
g_probe_buf[idx].args[1] = a1;
g_probe_buf[idx].args[2] = a2;
g_probe_buf[idx].args[3] = a3;
g_probe_head++;
g_probe_count++;
}
int probe_read(u32 n, probe_entry *out) {
if (!g_probe_buf || n == 0) return 0;
u32 avail = (g_probe_count < g_probe_cap) ? g_probe_count : g_probe_cap;
if (n > avail) n = avail;
for (u32 i = 0; i < n; i++) {
u32 src = (g_probe_head - n + i) % g_probe_cap;
out[i] = g_probe_buf[src];
}
return (int)n;
}
u32 probe_count(void) {
return g_probe_count;
}
u32 probe_capacity(void) {
return g_probe_cap;
}
/* ---- 供 dsk_loader 读取内部状态（填充 probe_info） ---- */
probe_entry *probe_buf_address(void) {
return g_probe_buf;
}
u32 probe_head_value(void) {
return g_probe_head;
}
u32 probe_dropped_count(void) {
return g_probe_dropped;
}
CODE/UTSM/kernel/probe.d
+7
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@@ -0,0 +1,7 @@
kernel/probe.o: kernel\probe.c include\utsm\instr.h include\utsm\types.h \
include\utsm\log.h include\utsm\arena.h kernel\ini_parser.h
include\utsm\instr.h:
include\utsm\types.h:
include\utsm\log.h:
include\utsm\arena.h:
kernel\ini_parser.h:
CODE/UTSM/mm/arena.d
+6
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@@ -0,0 +1,6 @@
mm/arena.o: mm\arena.c include\utsm\arena.h include\utsm\types.h \
include\utsm\config.h include\utsm\log.h
include\utsm\arena.h:
include\utsm\types.h:
include\utsm\config.h:
include\utsm\log.h:
CODE/UTSM/mm/arena.o
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CODE/UTSM/mm/dma.c
+4
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@@ -96,6 +96,10 @@ void dma_init(void) {
int dma_alloc_pages(u64 page_count, u64 alignment, u64 max_phys, dkm_dma_buffer *out) {
if (!out || page_count == 0 || !g_dma_ready) return -1;
if (page_count > DMA_BITMAP_PAGES) return -3;
/* 真机安全: max_phys 参数上限为低 4G (DMA bitmap 只覆盖低 4G)。
* 调用方若传 0 表示"无限制"，按低 4G 上限处理。
* 对 NVMe/AHCI 等需要 32-bit DMA 的设备, max_phys 传 0x100000000。
* 若未来需要 >4G DMA, 需要扩展 bitmap 或使用 IOMMU/SWIOTLB。 */
if (max_phys == 0 || max_phys > DMA_LOW_MAX_PHYS) max_phys = DMA_LOW_MAX_PHYS;
if (alignment < PAGE_SIZE) alignment = PAGE_SIZE;
CODE/UTSM/mm/dma.d
+6
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@@ -0,0 +1,6 @@
mm/dma.o: mm\dma.c include\utsm\dma.h include\utsm\types.h \
include\utsm\log.h mm\..\arch\x86_64\limine.h
include\utsm\dma.h:
include\utsm\types.h:
include\utsm\log.h:
mm\..\arch\x86_64\limine.h:
CODE/UTSM/mm/mmio.c
+241
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@@ -0,0 +1,241 @@
#include <utsm/mm.h>
#include <utsm/dma.h>
#include <utsm/log.h>
#include <utsm/types.h>
#include "../arch/x86_64/limine.h"
#define MM_PAGE_SIZE 4096ULL
/* 页表项属性位 */
#define PTE_PRESENT (1ULL << 0)
#define PTE_RW (1ULL << 1)
#define PTE_PWT (1ULL << 3)
#define PTE_PCD (1ULL << 4)
#define PTE_PS (1ULL << 7)
#define PTE_ADDR_MASK 0x000FFFFFFFFFF000ULL
#define PTE_NX (1ULL << 63)
#define CR4_LA57 (1ULL << 12)
#define CR4_PKE (1ULL << 22)
/* MMIO 专用虚拟窗口：运行时在高半部 PML4[256..510] 中扫描空闲槽位，
* 避开 Limine HHDM 区与内核映像（PML4[511]，0xFFFFFFFF80000000）。
* 单个 PML4 槽位对应 512GiB 虚拟空间，bump 分配不回收。 */
#define MM_WINDOW_SIZE (1ULL << 39)
extern volatile struct limine_hhdm_request g_hhdm_request;
static u64 g_hhdm;
static u64 g_pml4_phys;
static u64 g_window_base;
static u64 g_window_end;
static u64 g_window_next;
static int g_mm_state; /* 0=未初始化, 1=就绪, -1=不可用 */
static u32 g_max_phys_addr_bits; /* CPUID.80000008H:EAX[7:0], 真机物理地址宽度 */
static inline u64 mm_read_cr3(void) {
u64 v;
__asm__ volatile("mov %%cr3, %0" : "=r"(v));
return v;
}
static inline u64 mm_read_cr4(void) {
u64 v;
__asm__ volatile("mov %%cr4, %0" : "=r"(v));
return v;
}
static inline void mm_cpuid(u32 leaf, u32 *a, u32 *b, u32 *c, u32 *d) {
__asm__ volatile("cpuid" : "=a"(*a), "=b"(*b), "=c"(*c), "=d"(*d) : "a"(leaf), "c"(0));
}
static inline void mm_invlpg(u64 virt) {
__asm__ volatile("invlpg (%0)" :: "r"(virt) : "memory");
}
/* 在高半部 PML4[256..510] 中找一个空闲槽位作为 MMIO 窗口。
* 返回该槽位覆盖的 canonical 虚拟基址；无空闲槽返回 0。 */
static u64 mm_find_window(void) {
u64 *pml4 = (u64 *)(g_hhdm + g_pml4_phys);
for (u64 idx = 256; idx < 511; idx++) {
if (!(pml4[idx] & PTE_PRESENT)) {
/* bit39..47 为槽位号，bit48 以上符号扩展为全 1 */
return 0xFFFF000000000000ULL | (idx << 39);
}
}
return 0;
}
/* 首次调用时懒初始化：取 HHDM offset 与当前 CR3。
* UTSM 复用 Limine 页表，PML4 经 HHDM 访问。
*
* 真机安全检查:
* 1. LA57 (5-level paging) 拒绝 — 页表 walk 假定 4 级
* 2. CPUID 最大物理地址宽度检测 — 确保映射的物理地址合法
* 3. PML4 槽位扫描 — 确认空闲窗口可用
*/
static void mm_lazy_init(void) {
g_mm_state = -1;
g_max_phys_addr_bits = 0;
if (!g_hhdm_request.response) {
log_warn("[MM] missing HHDM response");
return;
}
g_hhdm = g_hhdm_request.response->offset;
if (!g_hhdm) {
log_warn("[MM] null HHDM offset");
return;
}
/* ---- 真机安全: LA57 早期检测与拒绝 ---- *
* 若固件/BIOS 启用了 5 级分页 (CR4.LA57=1), 本实现的 4 级页表 walk
* 将产生错误的地址转换, 必须拒绝继续运行。
* **QEMU 默认不会启用 LA57, 此路径只在真机触发。** */
if (mm_read_cr4() & CR4_LA57) {
log_error("[MM] LA57 5-level paging ACTIVE — REFUSING to proceed");
log_error("[MM] This kernel requires 4-level paging (48-bit virtual)");
log_error("[MM] Disable LA57 in BIOS/firmware settings");
return;
}
/* ---- 真机安全: 物理地址宽度检测 ---- *
* CPUID leaf 0x80000008 EAX[7:0] 给出 MaxPhysAddr 位宽。
* 典型值: QEMU=40/46, 实机=46/48/52。
* 若物理地址 > 48-bit, 4 级分页的 PTE 地址位可能不够用。
* 当前 PTE_ADDR_MASK 只使用 bit12-51 (40 位物理页号 = 52 位物理地址),
* 支持到 52-bit 物理地址, 足以覆盖所有现有 x86_64 实现。 */
{
u32 a, b, c, d;
mm_cpuid(0x80000000, &a, &b, &c, &d);
if (a >= 0x80000008) {
mm_cpuid(0x80000008, &a, &b, &c, &d);
g_max_phys_addr_bits = a & 0xff;
log_hex64("[MM] CPU MaxPhysAddr bits=", g_max_phys_addr_bits);
if (g_max_phys_addr_bits > 52) {
log_error("[MM] physical address width > 52 bits — PTE cannot represent");
return;
}
} else {
/* 无 80000008H leaf, 假定 36 或 39 位 (旧 CPU) */
g_max_phys_addr_bits = 36;
log_warn("[MM] CPUID 80000008H not available; assuming 36-bit phys");
}
}
g_pml4_phys = mm_read_cr3() & PTE_ADDR_MASK;
g_window_base = mm_find_window();
if (!g_window_base) {
log_error("[MM] no free PML4 slot for mmio window");
return;
}
g_window_end = g_window_base + MM_WINDOW_SIZE;
g_window_next = g_window_base;
g_mm_state = 1;
log_info("[MM] mmio mapper ready");
log_hex64("[MM] PML4 phys=", g_pml4_phys);
log_hex64("[MM] mmio window=", g_window_base);
log_hex64("[MM] MaxPhysAddr bits=", g_max_phys_addr_bits);
}
/* 逐级 walk 到 PT，缺层时从 DMA 页分配器取清零页补层。
* 返回最终 PTE 槽位的 HHDM 虚拟地址；冲突（撞上既有大页）或 OOM 返回 0。 */
static u64 *mm_walk_create(u64 virt) {
u64 *table = (u64 *)(g_hhdm + g_pml4_phys);
/* 中间三级：lvl=3 PML4(shift39) → lvl=2 PDPT(shift30) → lvl=1 PD(shift21) */
for (int lvl = 3; lvl >= 1; lvl--) {
u64 shift = 12 + (u64)lvl * 9;
u64 idx = (virt >> shift) & 0x1FFULL;
u64 entry = table[idx];
if (entry & PTE_PRESENT) {
if (entry & PTE_PS) return 0; /* 既有 1GiB/2MiB 大页占用，冲突 */
table = (u64 *)(g_hhdm + (entry & PTE_ADDR_MASK));
} else {
dkm_dma_buffer buf;
if (dma_alloc_pages(1, MM_PAGE_SIZE, 0, &buf) != 0) {
log_warn("[MM] page table alloc failed");
return 0;
}
table[idx] = buf.phys | PTE_PRESENT | PTE_RW;
table = (u64 *)buf.virt; /* dma 分配已清零 */
}
}
return &table[(virt >> 12) & 0x1FFULL];
}
/* 只查询不创建的 walk；任一级缺失或为大页时返回 0。 */
static u64 *mm_walk_query(u64 virt) {
u64 *table = (u64 *)(g_hhdm + g_pml4_phys);
for (int lvl = 3; lvl >= 1; lvl--) {
u64 shift = 12 + (u64)lvl * 9;
u64 entry = table[(virt >> shift) & 0x1FFULL];
if (!(entry & PTE_PRESENT) || (entry & PTE_PS)) return 0;
table = (u64 *)(g_hhdm + (entry & PTE_ADDR_MASK));
}
return &table[(virt >> 12) & 0x1FFULL];
}
void *mm_map_mmio(u64 phys, u64 size) {
if (g_mm_state == 0) mm_lazy_init();
if (g_mm_state != 1 || !size) return 0;
/* 真机安全: 验证物理地址在 CPU 支持的范围内 */
if (g_max_phys_addr_bits > 0) {
u64 max_phys = (1ULL << g_max_phys_addr_bits) - 1;
if (phys > max_phys) {
log_error("[MM] phys address exceeds CPU MaxPhysAddr");
log_hex64("[MM] phys=", phys);
log_hex64("[MM] max_phys=", max_phys);
return 0;
}
}
u64 off = phys & (MM_PAGE_SIZE - 1ULL);
u64 base_phys = phys - off;
u64 total = (off + size + MM_PAGE_SIZE - 1ULL) & ~(MM_PAGE_SIZE - 1ULL);
u64 pages = total / MM_PAGE_SIZE;
u64 vbase = g_window_next;
if (vbase < g_window_base || vbase + total > g_window_end) {
log_error("[MM] mmio window exhausted");
return 0;
}
u64 mapped = 0;
for (u64 i = 0; i < pages; i++) {
u64 virt = vbase + i * MM_PAGE_SIZE;
u64 *pte = mm_walk_create(virt);
if (!pte || (*pte & PTE_PRESENT)) {
/* 冲突/失败：回滚本次已建立的映射 */
log_error("[MM] map conflict");
for (u64 j = 0; j < mapped; j++) {
u64 v = vbase + j * MM_PAGE_SIZE;
u64 *p = mm_walk_query(v);
if (p) { *p = 0; mm_invlpg(v); }
}
return 0;
}
*pte = (base_phys + i * MM_PAGE_SIZE) | PTE_PRESENT | PTE_RW | PTE_PCD | PTE_PWT;
mm_invlpg(virt);
mapped++;
}
g_window_next = vbase + total;
log_hex64("[MM] map phys=", base_phys);
log_hex64("[MM] map virt=", vbase);
log_hex64("[MM] map pages=", pages);
return (void *)(vbase + off);
}
void mm_unmap_mmio(void *virt, u64 size) {
if (g_mm_state != 1 || !virt || !size) return;
u64 v = (u64)virt & ~(MM_PAGE_SIZE - 1ULL);
u64 end = ((u64)virt + size + MM_PAGE_SIZE - 1ULL) & ~(MM_PAGE_SIZE - 1ULL);
for (; v < end; v += MM_PAGE_SIZE) {
u64 *pte = mm_walk_query(v);
if (pte && (*pte & PTE_PRESENT)) {
*pte = 0;
mm_invlpg(v);
}
}
/* 窗口 bump 指针与中间页表页不回收：映射开销极小，保留复用 */
}
CODE/UTSM/mm/mmio.d
+7
View File
@@ -0,0 +1,7 @@
mm/mmio.o: mm\mmio.c include\utsm\mm.h include\utsm\types.h \
include\utsm\dma.h include\utsm\log.h mm\..\arch\x86_64\limine.h
include\utsm\mm.h:
include\utsm\types.h:
include\utsm\dma.h:
include\utsm\log.h:
mm\..\arch\x86_64\limine.h:
CODE/UTSM/mm/paging.c
+140
View File
@@ -0,0 +1,140 @@
/*
* UTSM 页表/MMIO 映射服务实现
*
* 算法说明：
* - is_mapped: 标准 x86_64 四级页表 walk，O(1)（固定 4 级），
* 页表页均为 RAM，经 HHDM 直映射访问，全程不触发 #PF。
* - map_mmio: 对 [phys, phys+size) 逐 4K 页在 HHDM 空间 (hhdm+phys)
* 补建 P|RW|PCD|PWT 映射。若中间级已存在则复用；若整页已被
* Limine 大页覆盖则跳过（is_mapped 先行判定）。页表页由
* dma_alloc_pages 提供（低 4G、4K 对齐、返回即清零）。
* - not-present 项不会被 TLB 缓存，新映射无需 invlpg；
* 仍对每页执行 invlpg 作为防御性措施（成本可忽略）。
*/
#include <utsm/paging.h>
#include <utsm/dma.h>
#include <utsm/log.h>
#include "../arch/x86_64/limine.h"
extern volatile struct limine_hhdm_request g_hhdm_request;
#define PTE_PRESENT (1ULL << 0)
#define PTE_RW (1ULL << 1)
#define PTE_PWT (1ULL << 3) /* MMIO: write-through */
#define PTE_PCD (1ULL << 4) /* MMIO: cache disable */
#define PTE_PS (1ULL << 7) /* 1G/2M 大页标志 */
#define PTE_ADDR_MASK 0x000FFFFFFFFFF000ULL
#define PAGE_4K 4096ULL
static u64 paging_hhdm(void) {
return g_hhdm_request.response ? g_hhdm_request.response->offset : 0;
}
static u64 paging_read_cr3(void) {
u64 v;
__asm__ volatile("mov %%cr3, %0" : "=r"(v));
return v & PTE_ADDR_MASK;
}
/* 返回 0=未映射；1=4K PTE；2=2M PDE；3=1G PDPTE */
static int paging_is_mapped_impl(u64 vaddr) {
u64 hhdm = paging_hhdm();
if (!hhdm) return 0;
u64 *pml4 = (u64 *)(paging_read_cr3() + hhdm);
u64 pml4e = pml4[(vaddr >> 39) & 0x1FF];
if (!(pml4e & PTE_PRESENT)) return 0;
u64 *pdpt = (u64 *)((pml4e & PTE_ADDR_MASK) + hhdm);
u64 pdpte = pdpt[(vaddr >> 30) & 0x1FF];
if (!(pdpte & PTE_PRESENT)) return 0;
if (pdpte & PTE_PS) return 3;
u64 *pd = (u64 *)((pdpte & PTE_ADDR_MASK) + hhdm);
u64 pde = pd[(vaddr >> 21) & 0x1FF];
if (!(pde & PTE_PRESENT)) return 0;
if (pde & PTE_PS) return 2;
u64 *pt = (u64 *)((pde & PTE_ADDR_MASK) + hhdm);
u64 pte = pt[(vaddr >> 12) & 0x1FF];
if (!(pte & PTE_PRESENT)) return 0;
return 1;
}
/* 分配一个清零的 4K 页作为页表页，返回物理地址；失败返回 0 */
static u64 paging_alloc_table(void) {
dkm_dma_buffer buf;
if (dma_alloc_pages(1, PAGE_4K, 0, &buf) != 0) return 0;
return buf.phys;
}
static int paging_map_mmio_impl(u64 phys, u64 size) {
u64 hhdm = paging_hhdm();
if (!hhdm || !size) return -1;
u64 begin = phys & ~(PAGE_4K - 1ULL);
u64 end = (phys + size + PAGE_4K - 1ULL) & ~(PAGE_4K - 1ULL);
u64 mapped = 0;
u64 skipped = 0;
for (u64 p = begin; p < end; p += PAGE_4K) {
u64 v = hhdm + p;
if (paging_is_mapped_impl(v)) {
skipped++; /* Limine 已覆盖（含 1G/2M 大页） */
continue;
}
u64 *pml4 = (u64 *)(paging_read_cr3() + hhdm);
u64 idx4 = (v >> 39) & 0x1FF;
if (!(pml4[idx4] & PTE_PRESENT)) {
u64 t = paging_alloc_table();
if (!t) { log_error("[PAGING] alloc PDPT failed"); return -2; }
pml4[idx4] = t | PTE_PRESENT | PTE_RW;
}
u64 *pdpt = (u64 *)((pml4[idx4] & PTE_ADDR_MASK) + hhdm);
u64 idx3 = (v >> 30) & 0x1FF;
if (pdpt[idx3] & PTE_PRESENT) {
if (pdpt[idx3] & PTE_PS) { skipped++; continue; } /* 1G 大页已覆盖 */
} else {
u64 t = paging_alloc_table();
if (!t) { log_error("[PAGING] alloc PD failed"); return -3; }
pdpt[idx3] = t | PTE_PRESENT | PTE_RW;
}
u64 *pd = (u64 *)((pdpt[idx3] & PTE_ADDR_MASK) + hhdm);
u64 idx2 = (v >> 21) & 0x1FF;
if (pd[idx2] & PTE_PRESENT) {
if (pd[idx2] & PTE_PS) { skipped++; continue; } /* 2M 大页已覆盖 */
} else {
u64 t = paging_alloc_table();
if (!t) { log_error("[PAGING] alloc PT failed"); return -4; }
pd[idx2] = t | PTE_PRESENT | PTE_RW;
}
u64 *pt = (u64 *)((pd[idx2] & PTE_ADDR_MASK) + hhdm);
u64 idx1 = (v >> 12) & 0x1FF;
pt[idx1] = p | PTE_PRESENT | PTE_RW | PTE_PCD | PTE_PWT;
__asm__ volatile("invlpg (%0)" :: "r"(v) : "memory");
mapped++;
}
log_info("[PAGING] map_mmio done");
log_hex64("[PAGING] phys=", phys);
log_hex64("[PAGING] size=", size);
log_hex64("[PAGING] 4K pages mapped=", mapped);
log_hex64("[PAGING] pages already covered=", skipped);
return 0;
}
static const dkm_mmio_api g_mmio_api = {
.is_mapped = paging_is_mapped_impl,
.map_mmio = paging_map_mmio_impl,
.cr3 = paging_read_cr3
};
const dkm_mmio_api *paging_get_api(void) {
return &g_mmio_api;
}
CODE/UTSM/mm/paging.d
+7
View File
@@ -0,0 +1,7 @@
mm/paging.o: mm\paging.c include\utsm\paging.h include\utsm\types.h \
include\utsm\dma.h include\utsm\log.h mm\..\arch\x86_64\limine.h
include\utsm\paging.h:
include\utsm\types.h:
include\utsm\dma.h:
include\utsm\log.h:
mm\..\arch\x86_64\limine.h:
CODE/UTSM/pckc/pckc.d
+13
View File
@@ -0,0 +1,13 @@
pckc/pckc.o: pckc\pckc.c include\utsm\pckc.h include\utsm\types.h \
include\utsm\config.h include\utsm\uuid.h include\utsm\crypto.h \
include\utsm\segment.h include\utsm\status.h include\utsm\capability.h \
include\utsm\dirty.h
include\utsm\pckc.h:
include\utsm\types.h:
include\utsm\config.h:
include\utsm\uuid.h:
include\utsm\crypto.h:
include\utsm\segment.h:
include\utsm\status.h:
include\utsm\capability.h:
include\utsm\dirty.h:
CODE/UTSM/pe/pe_loader.d
+11
View File
@@ -0,0 +1,11 @@
pe/pe_loader.o: pe\pe_loader.c pe\pe_loader.h include\utsm\types.h \
include\utsm\pe.h pe\pe_shim.h pe\x86emu32.h pe\..\include\utsm\pe.h \
include\utsm\arena.h include\utsm\log.h
pe\pe_loader.h:
include\utsm\types.h:
include\utsm\pe.h:
pe\pe_shim.h:
pe\x86emu32.h:
pe\..\include\utsm\pe.h:
include\utsm\arena.h:
include\utsm\log.h:
CODE/UTSM/pe/pe_service.c
+79 -21
View File
@@ -1,15 +1,15 @@
/* pe_service.c — PE 兼容层服务装配。
/* pe_service.c — PE 兼容层服务装配.
*
* 将 pe_loader + pe_shim + x86emu32 整合为统一的 pe_service，
* 通过 pe_get_service() 暴露给 DSK/cmd.elf（经 dsk_boot_context.reserved[4]）。
* 将 pe_loader + pe_shim + x86emu32 整合为统一的 pe_service,
* 通过 pe_get_service() 暴露给 DSK/cmd.elf(经 dsk_boot_context.reserved[4]).
*
* 执行策略：
* PE32+ (64位)：pe_load_image 加载（actual_base 重定位），
* IAT 填 ms_abi shim 函数地址，Ring0 原生执行入口。
* ExitProcess 经 __builtin_longjmp 跳回 pe_service_run。
* PE32 (32位)：直接以 preferred_base 加载到一块含栈/堆的大缓冲区，
* 无需重定位。IAT 填合成地址（0x00010000 | shim_idx），
* x86emu32 解释执行，CALL 合成地址时拦截分发到 shim32。
* 执行策略:
* PE32+ (64位):pe_load_image 加载(actual_base 重定位),
* IAT 填 ms_abi shim 函数地址,Ring0 原生执行入口.
* ExitProcess 经 __builtin_longjmp 跳回 pe_service_run.
* PE32 (32位):直接以 preferred_base 加载到一块含栈/堆的大缓冲区,
* 无需重定位.IAT 填合成地址(0x00010000 | shim_idx),
* x86emu32 解释执行,CALL 合成地址时拦截分发到 shim32.
*/
#include "pe_loader.h"
@@ -25,11 +25,11 @@
#define PE32_HEAP_SIZE (256 * 1024) /* 256KB 堆 */
#define PE32_MAX_IAT 256
/* 合成 shim 地址范围（与 pe_loader.c 一致） */
/* 合成 shim 地址范围(与 pe_loader.c 一致) */
#define PE32_SHIM_ADDR_BASE 0x00010000u
#define PE32_SHIM_UNIMPL 0x0001FFFFu
/* 前向声明（服务表引用） */
/* 前向声明(服务表引用) */
int pe_service_load(const void *pe_data, u64 size, pe_image_info *out);
int pe_service_run(const void *pe_data, u64 size, const char *cmdline, u64 *exit_code);
void pe_service_unload(pe_image_info *info);
@@ -46,7 +46,7 @@ const pe_service *pe_get_service(void) {
return &g_pe_service;
}
/* ===== 加载（不执行）===== */
/* ===== 加载(不执行)===== */
int pe_service_load(const void *pe_data, u64 size, pe_image_info *out) {
if (!pe_data || !out) return -1;
return pe_load_image(pe_data, size, out);
@@ -56,7 +56,7 @@ void pe_service_unload(pe_image_info *info) {
pe_unload_image(info);
}
/* ===== PE32 专用加载器（加载到指定缓冲区，base=preferred_base，无重定位）===== */
/* ===== PE32 专用加载器(加载到指定缓冲区,base=preferred_base,无重定位)===== */
typedef struct {
u8 *mem; /* 大缓冲区起始 */
u32 mem_size; /* 缓冲区总大小 */
@@ -93,7 +93,7 @@ static int pe32_load_into(const void *pe_data, u64 size, pe32_interp_image *img)
const image_section_header *sections = (const image_section_header *)
((const u8 *)opt + fh->size_of_optional_header);
/* 分配大缓冲区：[0 .. preferred_base + image_size + stack + heap] */
/* 分配大缓冲区:[0 .. preferred_base + image_size + stack + heap] */
u32 total = preferred_base + image_size + PE32_STACK_SIZE + PE32_HEAP_SIZE;
u8 *mem = (u8 *)kmem_alloc_aligned((u64)total, 0x1000);
if (!mem) return -9;
@@ -118,11 +118,11 @@ static int pe32_load_into(const void *pe_data, u64 size, pe32_interp_image *img)
for (u32 j = 0; j < copy_size; j++) img_start[va + j] = base[raw_off + j];
}
/* 解析 imports，填充 IAT（合成地址） */
/* 解析 imports,填充 IAT(合成地址) */
img->iat_count = 0;
const image_data_directory *import_dir = &oh->data_directory[IMAGE_DIRECTORY_ENTRY_IMPORT];
if (import_dir->virtual_address != 0 && import_dir->size != 0) {
/* RVA→offset 辅助 */
/* RVA->offset 辅助 */
for (int dll_idx = 0; ; dll_idx++) {
u32 imp_rva = import_dir->virtual_address + (u32)dll_idx * sizeof(image_import_descriptor);
/* imp_rva 在 image 内 */
@@ -198,12 +198,61 @@ static int pe32_load_into(const void *pe_data, u64 size, pe32_interp_image *img)
return 0;
}
/* ===== SSE/SSE2 启用 =====
* UTSM 自身用 -mno-sse -msoft-float 编译(启动早期安全),但 PE32+ 原生
* 代码(MSVC/LLVM x86_64 ABI)假定 SSE2 可用——浮点参数走 XMM0-3,
* egui 的 f32/f64 运算也全部编译为 SSE 指令.跳转 PE 入口前必须:
* CR0.EM=0, CR0.TS=0, CR0.MP=1, CR0.NE=1
* CR4.OSFXSR=1, CR4.OSXMMEXCPT=1
* MXCSR=0x1F80(屏蔽全部异常、round-to-nearest,Windows 默认)
* 内核 C 代码不带 SSE 指令,开启后对内核自身无副作用. */
static void pe_enable_sse(void) {
u64 cr0, cr4;
__asm__ volatile("mov %%cr0, %0" : "=r"(cr0));
cr0 &= ~((1ULL << 2) | (1ULL << 3)); /* EM=0, TS=0 */
cr0 |= (1ULL << 1) | (1ULL << 5); /* MP=1, NE=1 */
__asm__ volatile("mov %0, %%cr0" :: "r"(cr0));
__asm__ volatile("mov %%cr4, %0" : "=r"(cr4));
cr4 |= (1ULL << 9) | (1ULL << 10); /* OSFXSR=1, OSXMMEXCPT=1 */
__asm__ volatile("mov %0, %%cr4" :: "r"(cr4));
__asm__ volatile("fninit");
{
u32 mxcsr = 0x1F80;
__asm__ volatile("ldmxcsr %0" :: "m"(mxcsr));
}
log_info("[PE] SSE/SSE2 enabled for native PE32+ execution");
}
/* ===== PE 专用大栈 =====
* 调用链 UTSM->DSK->cmd->pe_service 全部运行在 16KB 内核栈上,
* Rust/egui 渲染(tessellate + 软光栅)栈需求远超 16KB,
* 因此跳转 PE 入口前切换到 arena 分配的 1MB 独立栈.
* 正常 ret 时由 trampoline 恢复旧 RSP;ExitProcess longjmp 路径
* 由 setjmp 时保存的内核 RSP 恢复,两条路径都安全. */
#define PE_STACK_BYTES (1024ULL * 1024ULL)
static u64 g_pe_saved_rsp;
typedef void (*pe_entry_fn)(void);
static void pe_call_on_stack(pe_entry_fn fn, u64 stack_top) {
__asm__ volatile(
"mov %%rsp, %0\n\t"
"mov %1, %%rsp\n\t"
"call *%2\n\t"
"mov %0, %%rsp\n\t"
: "=m"(g_pe_saved_rsp)
: "r"(stack_top), "r"(fn)
: "memory", "cc",
"rax", "rcx", "rdx", "rsi", "rdi",
"r8", "r9", "r10", "r11");
}
/* ===== 运行 =====
* 加载 + 执行 + 卸载。返回 0 成功，*exit_code 为进程退出码。 */
* 加载 + 执行 + 卸载.返回 0 成功,*exit_code 为进程退出码. */
int pe_service_run(const void *pe_data, u64 size, const char *cmdline, u64 *exit_code) {
if (!pe_data || size == 0) return -1;
/* 初始化 shim 状态（cmdline for GetCommandLineA） */
/* 初始化 shim 状态(cmdline for GetCommandLineA) */
pe_shim_init(cmdline ? cmdline : "");
/* 先解析 PE 判断 32/64 位 */
@@ -224,14 +273,23 @@ int pe_service_run(const void *pe_data, u64 size, const char *cmdline, u64 *exit
return -5;
}
log_info("[PE] running PE32+ natively");
pe_enable_sse();
/* 独立 1MB 栈(内核栈仅 16KB,egui 渲染会溢出) */
u8 *pe_stack = (u8 *)kmem_alloc_aligned(PE_STACK_BYTES, 4096);
if (!pe_stack) {
log_error("[PE] stack alloc failed");
return -9;
}
u64 stack_top = (u64)pe_stack + PE_STACK_BYTES; /* 4096 对齐 -> 16 对齐 */
u64 code = 0;
int jumped = pe_shim_setup_exit();
if (jumped == 0) {
typedef void (*pe_entry_fn)(void);
pe_entry_fn entry = (pe_entry_fn)info.entry_point;
log_hex64("[PE] entry=", (u64)entry);
entry();
log_hex64("[PE] stack_top=", stack_top);
pe_call_on_stack(entry, stack_top);
code = 0;
} else {
code = pe_shim_get_exit_code();
CODE/UTSM/pe/pe_service.d
+11
View File
@@ -0,0 +1,11 @@
pe/pe_service.o: pe\pe_service.c pe\pe_loader.h include\utsm\types.h \
include\utsm\pe.h pe\pe_shim.h pe\x86emu32.h pe\..\include\utsm\pe.h \
include\utsm\arena.h include\utsm\log.h
pe\pe_loader.h:
include\utsm\types.h:
include\utsm\pe.h:
pe\pe_shim.h:
pe\x86emu32.h:
pe\..\include\utsm\pe.h:
include\utsm\arena.h:
include\utsm\log.h:
CODE/UTSM/pe/pe_shim.c
+1004 -30
View File
@@ -1,22 +1,45 @@
/* pe_shim.c — Windows API shim 实现。
/* pe_shim.c — Windows API shim 实现.
*
* 所有 64位 shim 用 __attribute__((ms_abi)) 声明，匹配 PE32+ 调用约定。
* 32位 shim 从模拟栈读参数，供 x86emu32 解释器调用。
* 所有 64位 shim 用 __attribute__((ms_abi)) 声明,匹配 PE32+ 调用约定.
* 32位 shim 从模拟栈读参数,供 x86emu32 解释器调用.
*
* 支持 API：kernel32.dll（GetStdHandle/WriteFile/ReadFile/ExitProcess/
* HeapAlloc/HeapFree/VirtualAlloc/VirtualFree/GetCommandLineA/...）
* msvcrt.dll（printf/puts/putchar/malloc/free/exit/memcpy/memset/
* strlen/strcmp/strcpy/_initterm/_initterm_e）
* 支持 API:
* kernel32.dll 控制台、文件、堆、模块、编码转换、QPC、Sleep、同步、卸载桩
* msvcrt.dll printf、puts、malloc、free、mem 系列、str 系列、_initterm
* ntdll.dll NtWriteFile、RtlNtStatusToDosError
* bcryptprimitives.dll ProcessPrng (rdtsc xorshift)
* api-ms-win-core-synch-l1-2-0.dll WaitOnAddress、WakeByAddress (futex 桩)
* user32.dll 窗口类、窗口、消息泵 (PS/2 键盘轮询)、DefWindowProc
* gdi32.dll 内存 DC、DIBSection、BitBlt 到 Limine 帧缓冲
*
* 窗口模型:单顶层窗口 (固定伪句柄),GetDC 返回窗口 DC,
* BitBlt(窗口 DC, ...) 把 DIB 后台缓冲按窗口原点拷入帧缓冲.
* 消息泵:PeekMessageW 轮询 PS/2 键盘 (0x64/0x60),生成
* WM_KEYDOWN、WM_KEYUP、WM_CHAR;Esc 额外合成 WM_CLOSE (无鼠标环境的
* 唯一退出途径).鼠标字节 (状态位 0x20) 直接丢弃.
*/
#include "pe_shim.h"
#include <utsm/arena.h>
#include <utsm/log.h>
#include <utsm/types.h>
#include "../arch/x86_64/limine.h"
/* arch/x86_64/io.c */
extern void outb(u16 port, u8 value);
extern u8 inb(u16 port);
/* dkm/boot_modules.c — Limine framebuffer 请求(GDI BitBlt 目标) */
extern volatile struct limine_framebuffer_request g_fb_request;
/* 前向声明:shim 用户态堆(实现见下文"用户态堆"一节) */
static void *shim_heap_alloc(u64 size);
static void shim_heap_free(void *ptr);
static void *shim_heap_realloc(void *ptr, u64 size);
/* setjmp/longjmp for ExitProcess — 使用 __builtin_setjmp/__builtin_longjmp
* （clang/gcc 内置，freestanding 可用，无需 libc）。
* __builtin_setjmp 接受 void** 缓冲区，至少需要 8 个指针槽。 */
* (clang/gcc 内置,freestanding 可用,无需 libc).
* __builtin_setjmp 接受 void** 缓冲区,至少需要 8 个指针槽. */
static void *g_exit_jmp[24];
static int g_exit_jmp_set;
static u64 g_exit_code;
@@ -28,7 +51,7 @@ void pe_shim_init(const char *cmdline) {
g_exit_code = 0;
}
/* pe_run 调用：保存上下文，返回 0 = 首次（继续执行），1 = ExitProcess 触发 */
/* pe_run 调用:保存上下文,返回 0 = 首次(继续执行),1 = ExitProcess 触发 */
int pe_shim_setup_exit(void) {
g_exit_jmp_set = 1;
return __builtin_setjmp(g_exit_jmp);
@@ -39,7 +62,7 @@ void pe_shim_exit_process(u64 exit_code) {
if (g_exit_jmp_set) {
__builtin_longjmp(g_exit_jmp, 1);
}
/* 无 jmpbuf：直接返回 */
/* 无 jmpbuf:直接返回 */
}
int pe_shim_is_exit_call(u64 target) {
@@ -57,7 +80,7 @@ u64 pe_shim_unimpl_stub(void) {
return pe_shim_unimpl64_addr();
}
/* ===== 串口/帧缓冲输出（shim 内部复用） ===== */
/* ===== 串口/帧缓冲输出(shim 内部复用) ===== */
static void shim_output(const char *s, u64 len) {
for (u64 i = 0; i < len; i++) {
serial_putc(s[i]);
@@ -70,6 +93,9 @@ static void shim_output_str(const char *s) {
/* ===== kernel32.dll shims (64位, ms_abi) ===== */
/* 线程本地 last-error(简化全局) */
static u64 g_last_error = 0;
/* 句柄定义 */
#define STD_INPUT_HANDLE ((u64)0xFFFFFFF6)
#define STD_OUTPUT_HANDLE ((u64)0xFFFFFFF5)
@@ -91,7 +117,8 @@ static u64 __attribute__((ms_abi)) shim_WriteFile(u64 handle, u64 buffer, u64 le
if (handle == SHIM_STDOUT_HANDLE || handle == SHIM_STDERR_HANDLE) {
const char *buf = (const char *)buffer;
shim_output(buf, length);
if (bytes_written_ptr) *(u64 *)bytes_written_ptr = length;
/* lpNumberOfBytesWritten 是 DWORD*(4 字节),不能按 u64 写 */
if (bytes_written_ptr) *(u32 *)bytes_written_ptr = (u32)length;
return 1; /* TRUE */
}
return 0;
@@ -115,23 +142,36 @@ static u64 __attribute__((ms_abi)) shim_GetCommandLineA(void) {
}
static u64 __attribute__((ms_abi)) shim_GetCommandLineW(void) {
return (u64)g_cmdline; /* 简化：返回 ASCII */
return (u64)g_cmdline; /* 简化:返回 ASCII */
}
static u64 __attribute__((ms_abi)) shim_GetLastError(void) { return 0; }
static u64 __attribute__((ms_abi)) shim_SetLastError(u64 code) { (void)code; return 0; }
static u64 __attribute__((ms_abi)) shim_GetLastError(void) { return g_last_error; }
static u64 __attribute__((ms_abi)) shim_SetLastError(u64 code) { g_last_error = code; return 0; }
static u64 __attribute__((ms_abi)) shim_HeapCreate(u64 fl, u64 init, u64 max) {
(void)fl; (void)init; (void)max;
return 0x10000010; /* 假堆句柄 */
}
static u64 __attribute__((ms_abi)) shim_HeapAlloc(u64 heap, u64 flags, u64 size) {
(void)heap; (void)flags;
return (u64)kmem_alloc(size);
(void)heap;
void *p = shim_heap_alloc(size);
if (p && (flags & 8)) { /* HEAP_ZERO_MEMORY */
u8 *z = (u8 *)p;
for (u64 i = 0; i < size; i++) z[i] = 0;
}
return (u64)p;
}
static u64 __attribute__((ms_abi)) shim_HeapFree(u64 heap, u64 flags, u64 ptr) {
(void)heap; (void)flags; (void)ptr;
return 1; /* arena 无 free，返回 TRUE */
(void)heap; (void)flags;
shim_heap_free((void *)ptr);
return 1;
}
static u64 __attribute__((ms_abi)) shim_HeapReAlloc(u64 heap, u64 flags, u64 ptr, u64 size) {
(void)heap; (void)flags;
return (u64)shim_heap_realloc((void *)ptr, size);
}
static u64 __attribute__((ms_abi)) shim_GetProcessHeap(void) {
return 0x10000010;
}
static u64 __attribute__((ms_abi)) shim_VirtualAlloc(u64 addr, u64 size, u64 alloc_type, u64 protect) {
(void)addr; (void)alloc_type; (void)protect;
@@ -172,10 +212,10 @@ static void shim_msvcrt_output(const char *s) {
shim_output_str(s);
}
/* printf — 简化版，只支持 %s %d %c %x %u %% */
/* printf — 简化版,只支持 %s %d %c %x %u %% */
static u64 __attribute__((ms_abi)) shim_printf(u64 fmt, u64 a1, u64 a2, u64 a3) {
/* 可变参数：MS x64 ABI 下 a1-a3 在 RDX/R8/R9，更多参数在栈上。
* 简化处理：只处理前 3 个参数。 */
/* 可变参数:MS x64 ABI 下 a1-a3 在 RDX/R8/R9,更多参数在栈上.
* 简化处理:只处理前 3 个参数. */
const char *f = (const char *)fmt;
u64 args[3] = {a1, a2, a3};
int argi = 0;
@@ -244,17 +284,17 @@ static u64 __attribute__((ms_abi)) shim_putchar(u64 ch) {
}
static u64 __attribute__((ms_abi)) shim_malloc(u64 size) {
return (u64)kmem_alloc(size);
return (u64)shim_heap_alloc(size);
}
static u64 __attribute__((ms_abi)) shim_calloc(u64 count, u64 size) {
u64 total = count * size;
u8 *p = kmem_alloc(total);
u8 *p = shim_heap_alloc(total);
if (p) for (u64 i = 0; i < total; i++) p[i] = 0;
return (u64)p;
}
static u64 __attribute__((ms_abi)) shim_free(u64 ptr) { (void)ptr; return 0; }
static u64 __attribute__((ms_abi)) shim_free(u64 ptr) { shim_heap_free((void *)ptr); return 0; }
static u64 __attribute__((ms_abi)) shim_realloc(u64 ptr, u64 size) {
(void)ptr; return (u64)kmem_alloc(size);
return (u64)shim_heap_realloc((void *)ptr, size);
}
static u64 __attribute__((ms_abi)) shim_exit(u64 code) {
pe_shim_exit_process(code);
@@ -316,8 +356,8 @@ static u64 __attribute__((ms_abi)) shim_fputc(u64 ch, u64 stream) {
serial_putc((char)(ch & 0xFF));
return ch & 0xFF;
}
/* _initterm / _initterm_e — CRT 初始化，遍历函数指针表调用。
* 简化：直接跳过（返回 0）。 */
/* _initterm / _initterm_e — CRT 初始化,遍历函数指针表调用.
* 简化:直接跳过(返回 0). */
static u64 __attribute__((ms_abi)) shim_initterm(u64 start, u64 end) {
(void)start; (void)end;
return 0;
@@ -327,10 +367,866 @@ static u64 __attribute__((ms_abi)) shim_initterm_e(u64 start, u64 end) {
return 0;
}
/* 未实现 stub（64位）— 日志告警并返回 0 */
/* ============================================================
* 用户态堆(free-list,支持真正 free/realloc)
*
* Rust std 的 GlobalAlloc 走 GetProcessHeap/HeapAlloc/HeapReAlloc/
* HeapFree.arena 只增不减,GUI 主循环每帧的 Vec 分配会耗尽内存,
* 因此 shim 从 arena carve 一块 8MB 区域自行管理:
* 32B 块头 {size,used,next_free,pad},首次适应 + 分割 + 前向合并.
* ========================================================== */
#define SHIM_HEAP_BYTES (8ULL * 1024ULL * 1024ULL)
#define HEAP_HDR 32
typedef struct heap_blk {
u64 size; /* 数据区字节数(不含头) */
u64 used; /* 1=已分配 */
u64 next_free; /* 空闲链表(heap_blk*,0=尾) */
u64 pad;
} heap_blk;
static u8 *g_heap_region;
static heap_blk *g_heap_free_head;
static void shim_heap_init_once(void) {
if (g_heap_region) return;
g_heap_region = (u8 *)kmem_alloc_aligned(SHIM_HEAP_BYTES, 16);
if (!g_heap_region) {
log_error("[shim] heap region alloc failed");
return;
}
heap_blk *b = (heap_blk *)g_heap_region;
b->size = SHIM_HEAP_BYTES - HEAP_HDR;
b->used = 0;
b->next_free = 0;
b->pad = 0;
g_heap_free_head = b;
}
static void *shim_heap_alloc(u64 size) {
shim_heap_init_once();
if (!g_heap_region) return 0;
if (size == 0) size = 16;
size = (size + 15) & ~15ULL;
heap_blk *prev = 0, *b = g_heap_free_head;
while (b) {
if (b->size >= size) {
if (prev) prev->next_free = b->next_free;
else g_heap_free_head = (heap_blk *)b->next_free;
/* 剩余足够再分一块则分割 */
if (b->size >= size + HEAP_HDR + 16) {
heap_blk *nb = (heap_blk *)((u8 *)b + HEAP_HDR + size);
nb->size = b->size - size - HEAP_HDR;
nb->used = 0;
nb->pad = 0;
nb->next_free = (u64)g_heap_free_head;
g_heap_free_head = nb;
b->size = size;
}
b->used = 1;
b->next_free = 0;
return (u8 *)b + HEAP_HDR;
}
prev = b;
b = (heap_blk *)b->next_free;
}
log_error("[shim] heap OOM");
log_hex64("[shim] heap req=", size);
return 0;
}
static void shim_heap_free(void *ptr) {
if (!ptr) return;
heap_blk *b = (heap_blk *)((u8 *)ptr - HEAP_HDR);
b->used = 0;
/* 前向合并:物理下一块若空闲则吸收 */
heap_blk *nb = (heap_blk *)((u8 *)b + HEAP_HDR + b->size);
if ((u8 *)nb >= g_heap_region && (u8 *)nb < g_heap_region + SHIM_HEAP_BYTES
&& !nb->used && nb->size) {
/* 从空闲链摘除 nb */
heap_blk *prev = 0, *x = g_heap_free_head;
while (x && x != nb) { prev = x; x = (heap_blk *)x->next_free; }
if (x == nb) {
if (prev) prev->next_free = nb->next_free;
else g_heap_free_head = (heap_blk *)nb->next_free;
b->size += HEAP_HDR + nb->size;
}
}
b->next_free = (u64)g_heap_free_head;
g_heap_free_head = b;
}
static void *shim_heap_realloc(void *ptr, u64 size) {
if (!ptr) return shim_heap_alloc(size);
heap_blk *b = (heap_blk *)((u8 *)ptr - HEAP_HDR);
u64 old = b->size;
if (size <= old) return ptr;
u8 *np = (u8 *)shim_heap_alloc(size);
if (!np) return 0;
const u8 *s = (const u8 *)ptr;
for (u64 i = 0; i < old; i++) np[i] = s[i];
shim_heap_free(ptr);
return np;
}
/* ============================================================
* TSC 计时(QueryPerformanceCounter/Frequency、GetTickCount、Sleep)
* PIT channel 0 一次性校准(与 cmd.elf 同款手法).
* ========================================================== */
static __inline__ u64 shim_rdtsc(void) {
u32 lo, hi;
__asm__ volatile("rdtsc" : "=a"(lo), "=d"(hi));
return ((u64)hi << 32) | lo;
}
static u64 g_tsc_per_ms = 0;
static void shim_tsc_init(void) {
if (g_tsc_per_ms) return;
outb(0x43, 0x30);
outb(0x40, 0x7c);
outb(0x40, 0x2e);
u64 t0 = shim_rdtsc();
u16 prev = 0; u64 loops = 0;
for (;;) {
outb(0x43, 0x00);
u16 cur = (u16)inb(0x40) | ((u16)inb(0x40) << 8);
if (cur > prev && loops > 10) break;
prev = cur; loops++;
}
u64 t1 = shim_rdtsc();
g_tsc_per_ms = (t1 - t0) / 10;
if (!g_tsc_per_ms) g_tsc_per_ms = 1000000; /* 兜底 1GHz */
}
static u64 __attribute__((ms_abi)) shim_QueryPerformanceFrequency(u64 freq_ptr) {
shim_tsc_init();
if (freq_ptr) *(u64 *)freq_ptr = g_tsc_per_ms * 1000;
return 1;
}
static u64 __attribute__((ms_abi)) shim_QueryPerformanceCounter(u64 count_ptr) {
shim_tsc_init();
if (count_ptr) *(u64 *)count_ptr = shim_rdtsc();
return 1;
}
static u64 __attribute__((ms_abi)) shim_GetTickCount(void) {
shim_tsc_init();
return shim_rdtsc() / g_tsc_per_ms;
}
static u64 __attribute__((ms_abi)) shim_Sleep(u64 ms) {
shim_tsc_init();
u64 end = shim_rdtsc() + ms * g_tsc_per_ms;
while (shim_rdtsc() < end) __asm__ volatile("pause");
return 0;
}
/* SYSTEM_INFO(x64,48 字节) */
static u64 __attribute__((ms_abi)) shim_GetSystemInfo(u64 si_p) {
if (!si_p) return 0;
u8 *p = (u8 *)si_p;
for (int i = 0; i < 48; i++) p[i] = 0;
*(u32 *)(p + 0) = 9; /* PROCESSOR_ARCHITECTURE_AMD64 */
*(u32 *)(p + 4) = 4096; /* dwPageSize */
*(u32 *)(p + 20) = 1; /* dwNumberOfProcessors */
return 0;
}
/* ============================================================
* kernel32 增量:控制台/目录/环境/进程/同步/Rtl/编码转换
* ========================================================== */
static u64 __attribute__((ms_abi)) shim_GetConsoleMode(u64 handle, u64 mode_ptr) {
(void)handle; (void)mode_ptr;
g_last_error = 6; /* ERROR_INVALID_HANDLE -> std 回退 WriteFile */
return 0;
}
static u64 __attribute__((ms_abi)) shim_GetConsoleOutputCP(void) { return 65001; }
static u64 __attribute__((ms_abi)) shim_WriteConsoleW(u64 handle, u64 buf, u64 nchars,
u64 written_ptr, u64 reserved) {
(void)reserved;
if (handle != SHIM_STDOUT_HANDLE && handle != SHIM_STDERR_HANDLE) return 0;
const u16 *s = (const u16 *)buf;
for (u64 i = 0; i < nchars; i++) {
u32 c = s[i];
if (c < 0x80) {
serial_putc((char)c);
} else if (c < 0x800) {
serial_putc((char)(0xC0 | (c >> 6)));
serial_putc((char)(0x80 | (c & 0x3F)));
} else {
serial_putc((char)(0xE0 | (c >> 12)));
serial_putc((char)(0x80 | ((c >> 6) & 0x3F)));
serial_putc((char)(0x80 | (c & 0x3F)));
}
}
if (written_ptr) *(u32 *)written_ptr = (u32)nchars;
return 1;
}
static u64 __attribute__((ms_abi)) shim_GetCurrentDirectoryW(u64 buflen, u64 buf) {
static const u16 cwd[] = { 'C', ':', '\\', 0 };
if (!buf || buflen < 4) return 4; /* 需要 4 个字符(含 NUL) */
u16 *out = (u16 *)buf;
for (int i = 0; i < 4; i++) out[i] = cwd[i];
return 3; /* 不含 NUL 的字符数 */
}
static u64 __attribute__((ms_abi)) shim_GetEnvironmentVariableW(u64 name, u64 buf, u64 size) {
(void)name; (void)buf; (void)size;
g_last_error = 203; /* ERROR_ENVVAR_NOT_FOUND */
return 0;
}
static u64 __attribute__((ms_abi)) shim_GetCurrentProcess(void) { return (u64)-1; }
static u64 __attribute__((ms_abi)) shim_GetCurrentProcessId(void) { return 1; }
static u64 __attribute__((ms_abi)) shim_GetCurrentThreadId(void) { return 1; }
static u64 __attribute__((ms_abi)) shim_CreateMutexA(u64 sa, u64 initial, u64 name) {
(void)sa; (void)initial; (void)name;
return 0x10000030;
}
static u64 __attribute__((ms_abi)) shim_ReleaseMutex(u64 h) { (void)h; return 1; }
static u64 __attribute__((ms_abi)) shim_WaitForSingleObject(u64 h, u64 ms) {
(void)h; (void)ms; return 0; /* WAIT_OBJECT_0 */
}
static u64 __attribute__((ms_abi)) shim_WaitForSingleObjectEx(u64 h, u64 ms, u64 alert) {
(void)h; (void)ms; (void)alert; return 0;
}
static u64 __attribute__((ms_abi)) shim_FormatMessageW(u64 flags, u64 src, u64 msgid,
u64 lang, u64 buf, u64 size, u64 args) {
(void)flags; (void)src; (void)msgid; (void)lang; (void)buf; (void)size; (void)args;
return 0;
}
static u64 __attribute__((ms_abi)) shim_LoadLibraryA(u64 name_p) {
if (!name_p) return 0;
const char *n = (const char *)name_p;
/* 已知 DLL 返回伪句柄(大小写不敏感子串匹配) */
static const char *known[] = { "kernel32", "ntdll", "user32", "gdi32", "msvcrt" };
for (int k = 0; k < 5; k++) {
const char *pat = known[k];
for (const char *p = n; *p; p++) {
int i = 0;
while (pat[i] && p[i]) {
char a = p[i], b = pat[i];
if (a >= 'A' && a <= 'Z') a += 32;
if (a != b) break;
i++;
}
if (pat[i] == 0) return 0x10000020;
}
}
g_last_error = 126; /* ERROR_MOD_NOT_FOUND */
return 0;
}
static u64 __attribute__((ms_abi)) shim_lstrlenW(u64 str_p) {
const u16 *s = (const u16 *)str_p;
u64 n = 0;
if (s) while (s[n]) n++;
return n;
}
/* GetProcAddress — 在 shim 表内按函数名全局查找(hModule 为伪句柄,不限定 DLL).
* lpProcName 高 16 位为 0 时是 ordinal(不支持,返回 0)。
* Rust std 用它动态探测 Rtl 系列/dbghelp API,命中返回真实 shim 地址,miss 返回 0。 */
static u64 __attribute__((ms_abi)) shim_GetProcAddress(u64 module, u64 name_p) {
(void)module;
if (!name_p) return 0;
if ((name_p >> 16) == 0) { /* ordinal 导入 */
g_last_error = 127; /* ERROR_PROC_NOT_FOUND */
return 0;
}
const char *name = (const char *)name_p;
int n = pe_shim_count();
for (int i = 0; i < n; i++) {
const pe_shim_entry *e = pe_shim_get(i);
if (!e || !e->func || !e->fn64) continue;
const char *a = e->func, *b = name;
while (*a && *b && *a == *b) { a++; b++; }
if (*a == *b) return (u64)e->fn64;
}
log_info("[shim] GetProcAddress miss");
serial_write(" -> ");
serial_write(name);
serial_write("\n");
g_last_error = 127;
return 0;
}
/* Rtl* — Rust panic/unwind 机制引用(panic=abort 下不会真正走到) */
static u64 __attribute__((ms_abi)) shim_RtlCaptureContext(u64 ctx_p) {
u8 *p = (u8 *)ctx_p;
if (p) for (int i = 0; i < 1232; i++) p[i] = 0; /* x64 CONTEXT ≈ 1232B */
return 0;
}
static u64 __attribute__((ms_abi)) shim_RtlLookupFunctionEntry(u64 rip, u64 base_p, u64 table_p) {
(void)rip;
if (base_p) *(u64 *)base_p = 0;
if (table_p) *(u64 *)table_p = 0;
return 0;
}
static u64 __attribute__((ms_abi)) shim_RtlVirtualUnwind(u64 a, u64 b, u64 c, u64 d,
u64 e, u64 f, u64 g, u64 h, u64 i2) {
(void)a; (void)b; (void)c; (void)d; (void)e; (void)f; (void)g; (void)h; (void)i2;
return 0;
}
/* ---- MultiByteToWideChar / WideCharToMultiByte(CP_UTF8 + Latin-1)---- */
static u64 __attribute__((ms_abi)) shim_MultiByteToWideChar(u64 cp, u64 flags, u64 mbs_p,
u64 cbmb, u64 wbuf_p, u64 cchw) {
(void)flags;
const u8 *s = (const u8 *)mbs_p;
u16 *out = (u16 *)wbuf_p;
i64 remain = (i64)cbmb; /* -1 = NUL 结尾 */
u64 need = 0;
if (!s) return 0;
for (;;) {
if (remain == 0) break;
u8 b0 = s[0];
if (b0 == 0) {
if (remain < 0) { /* -1 模式把 NUL 计入 */
if (out && cchw > need) out[need] = 0;
need++;
}
break;
}
u32 cp32; u64 adv;
if (cp == 65001 && b0 >= 0xC2 && b0 < 0xE0 && (remain < 0 || remain >= 2)
&& (s[1] & 0xC0) == 0x80) {
cp32 = ((u32)(b0 & 0x1F) << 6) | (s[1] & 0x3F); adv = 2;
} else if (cp == 65001 && b0 >= 0xE0 && b0 < 0xF0 && (remain < 0 || remain >= 3)
&& (s[1] & 0xC0) == 0x80 && (s[2] & 0xC0) == 0x80) {
cp32 = ((u32)(b0 & 0x0F) << 12) | ((u32)(s[1] & 0x3F) << 6) | (s[2] & 0x3F); adv = 3;
} else if (cp == 65001 && b0 >= 0xF0 && b0 < 0xF5 && (remain < 0 || remain >= 4)
&& (s[1] & 0xC0) == 0x80 && (s[2] & 0xC0) == 0x80 && (s[3] & 0xC0) == 0x80) {
cp32 = ((u32)(b0 & 0x07) << 18) | ((u32)(s[1] & 0x3F) << 12)
| ((u32)(s[2] & 0x3F) << 6) | (s[3] & 0x3F); adv = 4;
} else {
cp32 = b0; adv = 1; /* Latin-1 / 非法序列按字节 */
}
if (cp32 > 0xFFFF) {
if (out && cchw > need + 1) {
cp32 -= 0x10000;
out[need] = (u16)(0xD800 + (cp32 >> 10));
out[need + 1] = (u16)(0xDC00 + (cp32 & 0x3FF));
}
need += 2;
} else {
if (out && cchw > need) out[need] = (u16)cp32;
need++;
}
s += adv;
if (remain > 0) remain -= (i64)adv;
}
return need;
}
static u64 __attribute__((ms_abi)) shim_WideCharToMultiByte(u64 cp, u64 flags, u64 ws_p,
u64 cchw, u64 mbs_p, u64 cbmb,
u64 defc, u64 used_p) {
(void)flags; (void)defc;
const u16 *s = (const u16 *)ws_p;
u8 *out = (u8 *)mbs_p;
i64 remain = (i64)cchw; /* -1 = NUL 结尾 */
u64 need = 0;
if (used_p) *(u32 *)used_p = 0;
if (!s) return 0;
for (;;) {
if (remain == 0) break;
u16 w = s[0];
if (w == 0) {
if (remain < 0) {
if (out && cbmb > need) out[need] = 0;
need++;
}
break;
}
u32 cp32 = w; u64 adv = 1;
if (w >= 0xD800 && w < 0xDC00 && (remain < 0 || remain >= 2)
&& s[1] >= 0xDC00 && s[1] < 0xE000) {
cp32 = 0x10000 + (((u32)(w - 0xD800) << 10) | (s[1] - 0xDC00));
adv = 2;
}
u8 enc[4]; u64 elen;
if (cp == 65001) {
if (cp32 < 0x80) { enc[0] = (u8)cp32; elen = 1; }
else if (cp32 < 0x800) {
enc[0] = (u8)(0xC0 | (cp32 >> 6)); enc[1] = (u8)(0x80 | (cp32 & 0x3F)); elen = 2;
} else if (cp32 < 0x10000) {
enc[0] = (u8)(0xE0 | (cp32 >> 12)); enc[1] = (u8)(0x80 | ((cp32 >> 6) & 0x3F));
enc[2] = (u8)(0x80 | (cp32 & 0x3F)); elen = 3;
} else {
enc[0] = (u8)(0xF0 | (cp32 >> 18)); enc[1] = (u8)(0x80 | ((cp32 >> 12) & 0x3F));
enc[2] = (u8)(0x80 | ((cp32 >> 6) & 0x3F)); enc[3] = (u8)(0x80 | (cp32 & 0x3F));
elen = 4;
}
} else {
enc[0] = (u8)(cp32 < 256 ? cp32 : '?'); elen = 1;
}
if (out) for (u64 i = 0; i < elen; i++) { if (cbmb > need + i) out[need + i] = enc[i]; }
need += elen;
s += adv;
if (remain > 0) remain -= (i64)adv;
}
return need;
}
/* ============================================================
* ntdll.dll / bcryptprimitives.dll / api-ms-win-core-synch
* ========================================================== */
static u64 __attribute__((ms_abi)) shim_NtWriteFile(u64 fh, u64 ev, u64 apc_r, u64 apc_c,
u64 iosb, u64 buf, u64 len,
u64 off, u64 key) {
(void)ev; (void)apc_r; (void)apc_c; (void)off; (void)key;
if (fh == SHIM_STDOUT_HANDLE || fh == SHIM_STDERR_HANDLE) {
shim_output((const char *)buf, len);
}
if (iosb) { /* IO_STATUS_BLOCK: {NTSTATUS Status; ULONG_PTR Information} */
((u64 *)iosb)[0] = 0;
((u64 *)iosb)[1] = len;
}
return 0; /* STATUS_SUCCESS */
}
static u64 __attribute__((ms_abi)) shim_RtlNtStatusToDosError(u64 status) {
return status & 0xFFFFFFFF;
}
static u64 __attribute__((ms_abi)) shim_ProcessPrng(u64 buf, u64 len) {
u64 s = shim_rdtsc() ^ 0x9E3779B97F4A7C15ULL;
u8 *p = (u8 *)buf;
for (u64 i = 0; i < len; i++) {
s ^= s << 13; s ^= s >> 7; s ^= s << 17; /* xorshift64 */
p[i] = (u8)(s & 0xFF);
}
return 1;
}
/* WaitOnAddress 允许虚假唤醒(调用者自旋重检),立即返回 TRUE 合法 */
static u64 __attribute__((ms_abi)) shim_WaitOnAddress(u64 addr, u64 expected, u64 size, u64 timeout) {
(void)addr; (void)expected; (void)size; (void)timeout;
return 1;
}
static u64 __attribute__((ms_abi)) shim_WakeByAddress(u64 addr) { (void)addr; return 0; }
/* ============================================================
* user32.dll — 单窗口 + 消息泵(PS/2 键盘轮询)
* ========================================================== */
#define SHIM_HWND 0x20000001ULL
#define SHIM_HDC_WND 0x20000002ULL
#define SHIM_HCURSOR 0x20000003ULL
#define SHIM_WM_CLOSE 0x0010u
#define SHIM_WM_QUIT 0x0012u
#define SHIM_WM_KEYDOWN 0x0100u
#define SHIM_WM_KEYUP 0x0101u
#define SHIM_WM_CHAR 0x0102u
static u64 g_wnd_proc = 0;
static int g_wnd_created = 0;
static i32 g_wnd_x = 0, g_wnd_y = 0, g_wnd_w = 0, g_wnd_h = 0;
/* MSG 布局与 PE 侧 #[repr(C)] MSG 一致(48 字节) */
typedef struct {
u64 hwnd;
u32 message; u32 pad0;
u64 wparam;
u64 lparam;
u32 time; u32 pad1;
i32 ptx, pty;
} shim_msg_t;
#define SHIM_MSGQ_CAP 64
static shim_msg_t g_msgq[SHIM_MSGQ_CAP];
static int g_mq_head = 0, g_mq_count = 0;
static void shim_msg_push(u32 msg, u64 w, u64 l) {
if (g_mq_count >= SHIM_MSGQ_CAP) return; /* 满则丢弃 */
int idx = (g_mq_head + g_mq_count) % SHIM_MSGQ_CAP;
g_msgq[idx].hwnd = SHIM_HWND;
g_msgq[idx].message = msg;
g_msgq[idx].pad0 = 0;
g_msgq[idx].wparam = w;
g_msgq[idx].lparam = l;
g_msgq[idx].time = 0;
g_msgq[idx].pad1 = 0;
g_msgq[idx].ptx = 0;
g_msgq[idx].pty = 0;
g_mq_count++;
}
/* PS/2 键盘状态 */
static int s_kbd_shift = 0, s_kbd_ctrl = 0, s_kbd_alt = 0, s_kbd_e0 = 0;
static char shim_scan_ascii(u8 sc, int shift) {
static const char normal[58] = {
0, 27, '1','2','3','4','5','6','7','8','9','0','-','=', 8, '\t',
'q','w','e','r','t','y','u','i','o','p','[',']','\n',0,
'a','s','d','f','g','h','j','k','l',';','\'', '`',0,'\\',
'z','x','c','v','b','n','m',',','.','/',0,'*',0,' '
};
static const char shifted[58] = {
0, 27, '!','@','#','$','%','^','&','*','(',')','_','+', 8, '\t',
'Q','W','E','R','T','Y','U','I','O','P','{','}','\n',0,
'A','S','D','F','G','H','J','K','L',':','"','~',0,'|',
'Z','X','C','V','B','N','M','<','>','?',0,'*',0,' '
};
if (sc >= 58) return 0;
return shift ? shifted[sc] : normal[sc];
}
/* scan code set 1 -> Win32 VK */
static u32 shim_scan_vk(u8 sc, int e0) {
if (e0) {
switch (sc) {
case 0x4B: return 0x25; /* VK_LEFT */
case 0x48: return 0x26; /* VK_UP */
case 0x4D: return 0x27; /* VK_RIGHT */
case 0x50: return 0x28; /* VK_DOWN */
case 0x53: return 0x2E; /* VK_DELETE */
case 0x1D: return 0x11; /* VK_CONTROL(右) */
case 0x38: return 0x12; /* VK_MENU(右) */
default: return 0;
}
}
if (sc >= 0x10 && sc <= 0x19) return 'Q' + (sc - 0x10);
if (sc >= 0x1E && sc <= 0x26) return 'A' + (sc - 0x1E);
if (sc >= 0x2C && sc <= 0x32) return 'Z' + (sc - 0x2C);
if (sc >= 0x02 && sc <= 0x0A) return '1' + (sc - 0x02);
if (sc == 0x0B) return '0';
switch (sc) {
case 0x1C: return 0x0D; /* VK_RETURN */
case 0x0E: return 0x08; /* VK_BACK */
case 0x39: return 0x20; /* VK_SPACE */
case 0x01: return 0x1B; /* VK_ESCAPE */
case 0x0F: return 0x09; /* VK_TAB */
case 0x2A: case 0x36: return 0x10; /* VK_SHIFT */
case 0x1D: return 0x11; /* VK_CONTROL */
case 0x38: return 0x12; /* VK_MENU */
default: return 0;
}
}
/* 排空 PS/2 输出缓冲,转成 Win32 消息入队 */
static void shim_kbd_poll(void) {
for (;;) {
u8 st = inb(0x64);
if (!(st & 1)) break;
u8 sc = inb(0x60);
if (st & 0x20) continue; /* 鼠标字节丢弃 */
if (sc == 0xE0) { s_kbd_e0 = 1; continue; }
int e0 = s_kbd_e0;
if (!e0) {
if (sc == 0x2A || sc == 0x36) { s_kbd_shift = 1; shim_msg_push(SHIM_WM_KEYDOWN, 0x10, sc); continue; }
if (sc == 0xAA || sc == 0xB6) { s_kbd_shift = 0; shim_msg_push(SHIM_WM_KEYUP, 0x10, sc); continue; }
if (sc == 0x1D) { s_kbd_ctrl = 1; shim_msg_push(SHIM_WM_KEYDOWN, 0x11, sc); continue; }
if (sc == 0x9D) { s_kbd_ctrl = 0; shim_msg_push(SHIM_WM_KEYUP, 0x11, sc); continue; }
if (sc == 0x38) { s_kbd_alt = 1; shim_msg_push(SHIM_WM_KEYDOWN, 0x12, sc); continue; }
if (sc == 0xB8) { s_kbd_alt = 0; shim_msg_push(SHIM_WM_KEYUP, 0x12, sc); continue; }
}
s_kbd_e0 = 0;
if (sc & 0x80) {
u32 vk = shim_scan_vk(sc & 0x7F, e0);
if (vk) shim_msg_push(SHIM_WM_KEYUP, vk, sc);
continue;
}
u32 vk = shim_scan_vk(sc, e0);
if (vk) {
shim_msg_push(SHIM_WM_KEYDOWN, vk, sc);
/* Esc -> 额外合成 WM_CLOSE:无鼠标环境下关闭窗口的唯一途径 */
if (vk == 0x1B && !e0) shim_msg_push(SHIM_WM_CLOSE, 0, 0);
}
if (!e0) {
char c = shim_scan_ascii(sc, s_kbd_shift);
if (c >= ' ' && c < 0x7F) shim_msg_push(SHIM_WM_CHAR, (u64)(u8)c, sc);
}
}
}
static u64 __attribute__((ms_abi)) shim_RegisterClassExW(u64 wc_p) {
if (!wc_p) return 0;
g_wnd_proc = *(u64 *)(wc_p + 8); /* cbSize(4)+style(4) -> lpfnWndProc */
log_info("[shim] RegisterClassExW ok");
return 0xC000;
}
static const struct limine_framebuffer *shim_fb(void) {
if (!g_fb_request.response || g_fb_request.response->framebuffer_count == 0) return 0;
return g_fb_request.response->framebuffers[0];
}
static u64 __attribute__((ms_abi)) shim_CreateWindowExW(
u64 exstyle, u64 class_name, u64 wnd_name, u64 style,
u64 x, u64 y, u64 w, u64 h,
u64 parent, u64 menu, u64 hinst, u64 param) {
(void)exstyle; (void)class_name; (void)wnd_name; (void)style;
(void)parent; (void)menu; (void)hinst; (void)param;
i32 ix = (i32)(u32)x, iy = (i32)(u32)y;
i32 iw = (i32)(u32)w, ih = (i32)(u32)h;
if (iw <= 0) iw = 800;
if (ih <= 0) ih = 600;
const struct limine_framebuffer *fb = shim_fb();
i32 fw = fb ? (i32)fb->width : 0;
i32 fh = fb ? (i32)fb->height : 0;
if (fw && iw > fw) iw = fw;
if (fh && ih > fh) ih = fh;
/* CW_USEDEFAULT(0x80000000) -> 居中 */
if (ix == (i32)0x80000000 || ix < 0) ix = fw ? (fw - iw) / 2 : 0;
if (iy == (i32)0x80000000 || iy < 0) iy = fh ? (fh - ih) / 2 : 0;
g_wnd_x = ix; g_wnd_y = iy; g_wnd_w = iw; g_wnd_h = ih;
g_wnd_created = 1;
log_info("[shim] CreateWindowExW ok");
log_hex64("[shim] wnd x=", (u64)(i64)ix);
log_hex64("[shim] wnd y=", (u64)(i64)iy);
log_hex64("[shim] wnd w=", (u64)(i64)iw);
log_hex64("[shim] wnd h=", (u64)(i64)ih);
return SHIM_HWND;
}
static u64 __attribute__((ms_abi)) shim_ShowWindow(u64 hwnd, u64 cmd) {
(void)hwnd; (void)cmd; return 1;
}
static u64 __attribute__((ms_abi)) shim_UpdateWindow(u64 hwnd) {
(void)hwnd; return 1;
}
static u64 __attribute__((ms_abi)) shim_DestroyWindow(u64 hwnd) {
(void)hwnd; g_wnd_created = 0; return 1;
}
static u64 __attribute__((ms_abi)) shim_LoadCursorW(u64 hinst, u64 name) {
(void)hinst; (void)name; return SHIM_HCURSOR;
}
static u64 __attribute__((ms_abi)) shim_SetCursor(u64 cur) {
(void)cur; return SHIM_HCURSOR;
}
static u64 __attribute__((ms_abi)) shim_GetCursorPos(u64 pt_p) {
if (pt_p) { ((i32 *)pt_p)[0] = g_wnd_w / 2; ((i32 *)pt_p)[1] = g_wnd_h / 2; }
return 1;
}
static u64 __attribute__((ms_abi)) shim_ScreenToClient(u64 hwnd, u64 pt_p) {
(void)hwnd; (void)pt_p; return 1; /* 窗口即全屏坐标系,无需转换 */
}
static u64 __attribute__((ms_abi)) shim_GetAsyncKeyState(u64 vk) {
(void)vk; return 0; /* 修饰键状态已由消息流维护 */
}
static u64 __attribute__((ms_abi)) shim_SetTimer(u64 hwnd, u64 id, u64 elapse, u64 cb) {
(void)hwnd; (void)elapse; (void)cb; return id ? id : 1;
}
static u64 __attribute__((ms_abi)) shim_KillTimer(u64 hwnd, u64 id) {
(void)hwnd; (void)id; return 1;
}
static u64 __attribute__((ms_abi)) shim_MessageBeep(u64 t) { (void)t; return 1; }
static u64 __attribute__((ms_abi)) shim_GetClientRect(u64 hwnd, u64 rect_p) {
(void)hwnd;
if (!rect_p) return 0;
i32 *r = (i32 *)rect_p;
r[0] = 0; r[1] = 0; r[2] = g_wnd_w; r[3] = g_wnd_h;
return 1;
}
static u64 __attribute__((ms_abi)) shim_InvalidateRect(u64 hwnd, u64 rect_p, u64 erase) {
(void)hwnd; (void)rect_p; (void)erase; return 1; /* 主循环每帧全量重绘 */
}
/* PAINTSTRUCT: {hdc(8), fErase(4), rcPaint(16), fRestore(4), fIncUpdate(4), rgb(32)} */
static u64 __attribute__((ms_abi)) shim_BeginPaint(u64 hwnd, u64 ps_p) {
(void)hwnd;
if (!ps_p) return 0;
u8 *p = (u8 *)ps_p;
for (int i = 0; i < 72; i++) p[i] = 0;
*(u64 *)p = SHIM_HDC_WND;
return SHIM_HDC_WND;
}
static u64 __attribute__((ms_abi)) shim_EndPaint(u64 hwnd, u64 ps_p) {
(void)hwnd; (void)ps_p; return 1;
}
static u64 __attribute__((ms_abi)) shim_ReleaseDC(u64 hwnd, u64 hdc) {
(void)hwnd; (void)hdc; return 1;
}
static u64 __attribute__((ms_abi)) shim_GetSystemMetrics(u64 idx) {
const struct limine_framebuffer *fb = shim_fb();
if (!fb) return 0;
if (idx == 0) return fb->width; /* SM_CXSCREEN */
if (idx == 1) return fb->height; /* SM_CYSCREEN */
return 0;
}
static u64 __attribute__((ms_abi)) shim_DefWindowProcW(u64 hwnd, u64 msg, u64 w, u64 l) {
(void)hwnd; (void)msg; (void)w; (void)l; return 0;
}
static u64 __attribute__((ms_abi)) shim_TranslateMessage(u64 msg_p) {
(void)msg_p; return 0; /* WM_CHAR 已在键盘轮询时合成 */
}
static u64 __attribute__((ms_abi)) shim_PeekMessageW(u64 msg_p, u64 hwnd,
u64 fmin, u64 fmax, u64 remove) {
(void)hwnd; (void)fmin; (void)fmax;
shim_kbd_poll();
if (g_mq_count == 0) return 0;
shim_msg_t *m = &g_msgq[g_mq_head];
if (msg_p) *(shim_msg_t *)msg_p = *m;
if (remove & 1) { /* PM_REMOVE */
g_mq_head = (g_mq_head + 1) % SHIM_MSGQ_CAP;
g_mq_count--;
}
return 1;
}
static u64 __attribute__((ms_abi)) shim_GetMessageW(u64 msg_p, u64 hwnd,
u64 fmin, u64 fmax) {
(void)hwnd; (void)fmin; (void)fmax;
for (;;) { /* 阻塞语义:轮询键盘直到有消息 */
shim_kbd_poll();
if (g_mq_count > 0) break;
__asm__ volatile("pause");
}
shim_msg_t *m = &g_msgq[g_mq_head];
if (msg_p) *(shim_msg_t *)msg_p = *m;
g_mq_head = (g_mq_head + 1) % SHIM_MSGQ_CAP;
g_mq_count--;
return (m->message == SHIM_WM_QUIT) ? 0 : 1;
}
static u64 __attribute__((ms_abi)) shim_PostQuitMessage(u64 exit_code) {
shim_msg_push(SHIM_WM_QUIT, exit_code, 0);
return 0;
}
typedef u64 (__attribute__((ms_abi)) *shim_wndproc_t)(u64, u64, u64, u64);
static u64 __attribute__((ms_abi)) shim_DispatchMessageW(u64 msg_p) {
if (!msg_p || !g_wnd_proc) return 0;
const shim_msg_t *m = (const shim_msg_t *)msg_p;
return ((shim_wndproc_t)g_wnd_proc)(m->hwnd, m->message, m->wparam, m->lparam);
}
/* ============================================================
* gdi32.dll — 内存 DC / DIBSection / BitBlt -> 帧缓冲
* ========================================================== */
typedef struct { u64 bmp; } shim_dc_t; /* 当前选中位图(0=无) */
typedef struct { i32 w, h; u32 *bits; } shim_bmp_t; /* 32bpp 0xAARRGGBB 位图 */
static u64 __attribute__((ms_abi)) shim_GetDC(u64 hwnd) {
(void)hwnd; return SHIM_HDC_WND;
}
static u64 __attribute__((ms_abi)) shim_CreateCompatibleDC(u64 hdc) {
(void)hdc;
shim_dc_t *dc = (shim_dc_t *)kmem_alloc(sizeof(shim_dc_t));
if (dc) dc->bmp = 0;
return (u64)dc;
}
static u64 __attribute__((ms_abi)) shim_CreateDIBSection(u64 hdc, u64 bmi_p, u64 usage,
u64 ppv, u64 hsec, u64 off) {
(void)hdc; (void)usage; (void)hsec; (void)off;
if (!bmi_p || !ppv) return 0;
const u8 *bmi = (const u8 *)bmi_p;
i32 w = *(const i32 *)(bmi + 4); /* biWidth */
i32 h = *(const i32 *)(bmi + 8); /* biHeight(负=top-down) */
u16 bpp = *(const u16 *)(bmi + 14); /* biBitCount */
if (h < 0) h = -h;
if (w <= 0 || h <= 0 || bpp != 32) return 0;
u64 npix = (u64)w * (u64)h;
u32 *bits = (u32 *)kmem_alloc(npix * 4);
if (!bits) return 0;
for (u64 i = 0; i < npix; i++) bits[i] = 0;
shim_bmp_t *b = (shim_bmp_t *)kmem_alloc(sizeof(shim_bmp_t));
if (!b) return 0;
b->w = w; b->h = h; b->bits = bits;
*(u64 *)ppv = (u64)bits;
log_info("[shim] CreateDIBSection ok");
log_hex64("[shim] dib w=", (u64)(i64)w);
log_hex64("[shim] dib h=", (u64)(i64)h);
log_hex64("[shim] dib bits=", (u64)bits);
return (u64)b;
}
static u64 __attribute__((ms_abi)) shim_SelectObject(u64 hdc, u64 obj) {
shim_dc_t *dc = (shim_dc_t *)hdc;
if (!dc) return 0;
u64 prev = dc->bmp;
dc->bmp = obj;
return prev;
}
static u64 __attribute__((ms_abi)) shim_DeleteDC(u64 hdc) {
if (hdc == SHIM_HDC_WND) return 1; /* 窗口 DC 不释放 */
shim_dc_t *dc = (shim_dc_t *)hdc;
/* kmem arena 不支持 free,小对象泄漏可接受 */
(void)dc;
return 1;
}
static u64 __attribute__((ms_abi)) shim_DeleteObject(u64 obj) {
(void)obj; return 1; /* 同上:arena 无 free,位图随进程退出回收 */
}
static u64 __attribute__((ms_abi)) shim_GetStockObject(u64 i) {
(void)i; return 0x20000010; /* 伪 GDI 对象句柄 */
}
static u64 __attribute__((ms_abi)) shim_GdiFlush(void) { return 1; }
static u64 g_blit_count = 0;
static u64 __attribute__((ms_abi)) shim_BitBlt(u64 dstdc, u64 x, u64 y, u64 cx, u64 cy,
u64 srcdc, u64 x1, u64 y1, u64 rop) {
(void)rop;
if (dstdc != SHIM_HDC_WND) return 1; /* 仅支持窗口 DC 目标 */
const struct limine_framebuffer *fb = shim_fb();
if (!fb || !fb->address) return 0;
if (fb->bpp != 32 && fb->bpp != 24) return 0;
shim_dc_t *sdc = (shim_dc_t *)srcdc;
if (!sdc || !sdc->bmp) return 0;
shim_bmp_t *bmp = (shim_bmp_t *)sdc->bmp;
i32 dx = (i32)(u32)x + g_wnd_x;
i32 dy = (i32)(u32)y + g_wnd_y;
i32 sx0 = (i32)(u32)x1, sy0 = (i32)(u32)y1;
i32 w = (i32)(u32)cx, h = (i32)(u32)cy;
u8 *fbb = (u8 *)fb->address;
u32 rsh = fb->red_mask_shift, gsh = fb->green_mask_shift, bsh = fb->blue_mask_shift;
u32 rsz = fb->red_mask_size ? fb->red_mask_size : 8;
u32 gsz = fb->green_mask_size ? fb->green_mask_size : 8;
u32 bsz = fb->blue_mask_size ? fb->blue_mask_size : 8;
int fast = (fb->bpp == 32 && rsh == 16 && gsh == 8 && bsh == 0
&& rsz == 8 && gsz == 8 && bsz == 8);
for (i32 row = 0; row < h; row++) {
i32 fy = dy + row, sy = sy0 + row;
if (fy < 0 || fy >= (i32)fb->height) continue;
if (sy < 0 || sy >= bmp->h) continue;
u8 *dst_row = fbb + (u64)fy * fb->pitch;
const u32 *src = bmp->bits + (u64)sy * (u64)bmp->w;
for (i32 col = 0; col < w; col++) {
i32 fx = dx + col, sx = sx0 + col;
if (fx < 0 || fx >= (i32)fb->width) continue;
if (sx < 0 || sx >= bmp->w) continue;
u32 px = src[sx];
if (fast) {
((u32 *)dst_row)[fx] = px;
} else {
u32 r = (px >> 16) & 0xFF, g = (px >> 8) & 0xFF, bl = px & 0xFF;
u32 v = ((r >> (8 - rsz)) << rsh)
| ((g >> (8 - gsz)) << gsh)
| ((bl >> (8 - bsz)) << bsh);
if (fb->bpp == 32) {
((u32 *)dst_row)[fx] = v;
} else {
u8 *p = dst_row + (u64)fx * 3;
p[0] = (u8)(v & 0xFF);
p[1] = (u8)((v >> 8) & 0xFF);
p[2] = (u8)((v >> 16) & 0xFF);
}
}
}
}
g_blit_count++;
if (g_blit_count == 1) log_info("[shim] BitBlt first frame on screen");
if ((g_blit_count % 600) == 0) log_hex64("[shim] BitBlt frames=", g_blit_count);
return 1;
}
/* 未实现 stub(64位)— 日志告警(含调用点返回地址)并返回 0 */
static u64 __attribute__((ms_abi)) shim_unimpl64(u64 a0, u64 a1, u64 a2, u64 a3) {
(void)a0; (void)a1; (void)a2; (void)a3;
log_warn("[PE] unimplemented API called");
log_hex64("[PE] caller rip=", (u64)__builtin_return_address(0));
return 0;
}
@@ -364,6 +1260,84 @@ static const pe_shim_entry g_shim_table[] = {
{"kernel32.dll", "CloseHandle", (void*)shim_CloseHandle, 0},
{"kernel32.dll", "GetFileSize", (void*)shim_GetFileSize, 0},
{"kernel32.dll", "SetFilePointer", (void*)shim_SetFilePointer, 0},
/* kernel32.dll — Deaicup GUI 增量 */
{"kernel32.dll", "HeapReAlloc", (void*)shim_HeapReAlloc, 0},
{"kernel32.dll", "GetProcessHeap", (void*)shim_GetProcessHeap, 0},
{"kernel32.dll", "QueryPerformanceFrequency", (void*)shim_QueryPerformanceFrequency, 0},
{"kernel32.dll", "QueryPerformanceCounter", (void*)shim_QueryPerformanceCounter, 0},
{"kernel32.dll", "GetTickCount", (void*)shim_GetTickCount, 0},
{"kernel32.dll", "Sleep", (void*)shim_Sleep, 0},
{"kernel32.dll", "GetSystemInfo", (void*)shim_GetSystemInfo, 0},
{"kernel32.dll", "GetConsoleMode", (void*)shim_GetConsoleMode, 0},
{"kernel32.dll", "GetConsoleOutputCP", (void*)shim_GetConsoleOutputCP, 0},
{"kernel32.dll", "WriteConsoleW", (void*)shim_WriteConsoleW, 0},
{"kernel32.dll", "GetCurrentDirectoryW", (void*)shim_GetCurrentDirectoryW, 0},
{"kernel32.dll", "GetEnvironmentVariableW", (void*)shim_GetEnvironmentVariableW, 0},
{"kernel32.dll", "GetCurrentProcess", (void*)shim_GetCurrentProcess, 0},
{"kernel32.dll", "GetCurrentProcessId", (void*)shim_GetCurrentProcessId, 0},
{"kernel32.dll", "GetCurrentThreadId", (void*)shim_GetCurrentThreadId, 0},
{"kernel32.dll", "CreateMutexA", (void*)shim_CreateMutexA, 0},
{"kernel32.dll", "ReleaseMutex", (void*)shim_ReleaseMutex, 0},
{"kernel32.dll", "WaitForSingleObject", (void*)shim_WaitForSingleObject, 0},
{"kernel32.dll", "WaitForSingleObjectEx", (void*)shim_WaitForSingleObjectEx, 0},
{"kernel32.dll", "FormatMessageW", (void*)shim_FormatMessageW, 0},
{"kernel32.dll", "LoadLibraryA", (void*)shim_LoadLibraryA, 0},
{"kernel32.dll", "GetProcAddress", (void*)shim_GetProcAddress, 0},
{"kernel32.dll", "lstrlenW", (void*)shim_lstrlenW, 0},
{"kernel32.dll", "MultiByteToWideChar", (void*)shim_MultiByteToWideChar, 0},
{"kernel32.dll", "WideCharToMultiByte", (void*)shim_WideCharToMultiByte, 0},
/* kernel32.dll 也转发导出这三个 Rtl*(Rust std 从 kernel32 静态导入) */
{"kernel32.dll", "RtlCaptureContext", (void*)shim_RtlCaptureContext, 0},
{"kernel32.dll", "RtlLookupFunctionEntry",(void*)shim_RtlLookupFunctionEntry, 0},
{"kernel32.dll", "RtlVirtualUnwind", (void*)shim_RtlVirtualUnwind, 0},
/* ntdll.dll */
{"ntdll.dll", "RtlCaptureContext", (void*)shim_RtlCaptureContext, 0},
{"ntdll.dll", "RtlLookupFunctionEntry",(void*)shim_RtlLookupFunctionEntry, 0},
{"ntdll.dll", "RtlVirtualUnwind", (void*)shim_RtlVirtualUnwind, 0},
{"ntdll.dll", "NtWriteFile", (void*)shim_NtWriteFile, 0},
{"ntdll.dll", "RtlNtStatusToDosError", (void*)shim_RtlNtStatusToDosError, 0},
/* bcryptprimitives.dll */
{"bcryptprimitives.dll", "ProcessPrng", (void*)shim_ProcessPrng, 0},
/* api-ms-win-core-synch-l1-2-0.dll */
{"api-ms-win-core-synch-l1-2-0.dll", "WaitOnAddress", (void*)shim_WaitOnAddress, 0},
{"api-ms-win-core-synch-l1-2-0.dll", "WakeByAddressSingle",(void*)shim_WakeByAddress, 0},
{"api-ms-win-core-synch-l1-2-0.dll", "WakeByAddressAll", (void*)shim_WakeByAddress, 0},
/* user32.dll */
{"user32.dll", "RegisterClassExW", (void*)shim_RegisterClassExW, 0},
{"user32.dll", "CreateWindowExW", (void*)shim_CreateWindowExW, 0},
{"user32.dll", "DestroyWindow", (void*)shim_DestroyWindow, 0},
{"user32.dll", "ShowWindow", (void*)shim_ShowWindow, 0},
{"user32.dll", "UpdateWindow", (void*)shim_UpdateWindow, 0},
{"user32.dll", "GetMessageW", (void*)shim_GetMessageW, 0},
{"user32.dll", "PeekMessageW", (void*)shim_PeekMessageW, 0},
{"user32.dll", "TranslateMessage", (void*)shim_TranslateMessage, 0},
{"user32.dll", "DispatchMessageW", (void*)shim_DispatchMessageW, 0},
{"user32.dll", "PostQuitMessage", (void*)shim_PostQuitMessage, 0},
{"user32.dll", "DefWindowProcW", (void*)shim_DefWindowProcW, 0},
{"user32.dll", "GetClientRect", (void*)shim_GetClientRect, 0},
{"user32.dll", "InvalidateRect", (void*)shim_InvalidateRect, 0},
{"user32.dll", "BeginPaint", (void*)shim_BeginPaint, 0},
{"user32.dll", "EndPaint", (void*)shim_EndPaint, 0},
{"user32.dll", "GetDC", (void*)shim_GetDC, 0},
{"user32.dll", "ReleaseDC", (void*)shim_ReleaseDC, 0},
{"user32.dll", "LoadCursorW", (void*)shim_LoadCursorW, 0},
{"user32.dll", "SetCursor", (void*)shim_SetCursor, 0},
{"user32.dll", "GetCursorPos", (void*)shim_GetCursorPos, 0},
{"user32.dll", "ScreenToClient", (void*)shim_ScreenToClient, 0},
{"user32.dll", "GetAsyncKeyState", (void*)shim_GetAsyncKeyState, 0},
{"user32.dll", "SetTimer", (void*)shim_SetTimer, 0},
{"user32.dll", "KillTimer", (void*)shim_KillTimer, 0},
{"user32.dll", "MessageBeep", (void*)shim_MessageBeep, 0},
{"user32.dll", "GetSystemMetrics", (void*)shim_GetSystemMetrics, 0},
/* gdi32.dll */
{"gdi32.dll", "CreateCompatibleDC", (void*)shim_CreateCompatibleDC, 0},
{"gdi32.dll", "CreateDIBSection", (void*)shim_CreateDIBSection, 0},
{"gdi32.dll", "SelectObject", (void*)shim_SelectObject, 0},
{"gdi32.dll", "DeleteObject", (void*)shim_DeleteObject, 0},
{"gdi32.dll", "DeleteDC", (void*)shim_DeleteDC, 0},
{"gdi32.dll", "BitBlt", (void*)shim_BitBlt, 0},
{"gdi32.dll", "GetStockObject", (void*)shim_GetStockObject, 0},
{"gdi32.dll", "GdiFlush", (void*)shim_GdiFlush, 0},
/* msvcrt.dll */
{"msvcrt.dll", "printf", (void*)shim_printf, 0},
{"msvcrt.dll", "puts", (void*)shim_puts, 0},
CODE/UTSM/pe/pe_shim.d
+7
View File
@@ -0,0 +1,7 @@
pe/pe_shim.o: pe\pe_shim.c pe\pe_shim.h include\utsm\types.h \
include\utsm\arena.h include\utsm\log.h pe\..\arch\x86_64\limine.h
pe\pe_shim.h:
include\utsm\types.h:
include\utsm\arena.h:
include\utsm\log.h:
pe\..\arch\x86_64\limine.h:
CODE/UTSM/pe/x86emu32.d
+6
View File
@@ -0,0 +1,6 @@
pe/x86emu32.o: pe\x86emu32.c pe\x86emu32.h include\utsm\types.h \
pe\pe_shim.h include\utsm\log.h
pe\x86emu32.h:
include\utsm\types.h:
pe\pe_shim.h:
include\utsm\log.h:

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