feat: Phase 1 网络端到端打通 + FirstInit/Login/DevMode 完善
- 用户态共享网络协议栈 CODE/tools/net_stack.h（eth/ARP/IPv4/ICMP/UDP-DNS/TCP static inline，轮询模型） - shell 内建 ping/curl/run 命令；ping.elf/curl.elf 对齐 net_stack.h 真实协议栈 - shell dev_mode 串口镜像（g_serial_mirror）便于自动化验证 - DSK 启动流程：firstInit.txt 双行格式（firstInit + dev_mode），dev_mode=1 触发 shell 自动回归测试 - FirstInit 完成→持久化 USER.CONF + 翻转 firstInit 0->1（保留 dev_mode） - firstInit=1 时 DSK 加载 login.elf 进行用户选择 + 密码校验后再进 desktop - 新增 CODE/login/ 登录应用、CODE/DKM/dkm_shared.h、Logo.png - ahci/e1000/virtio_net/fat32/console_fb 驱动更新；utsm serial/block/dsk_loader 调整 - build.ps1 打包 ping.elf/curl.elf 进 SATA FAT32 根目录 - 移除 CODE/tools/bash（与 shell.elf 重复）
This commit is contained in:
xyou
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-138
@@ -4,100 +4,7 @@
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* and ports so later block I/O can be added safely.
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*/
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#include <stdint.h>
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#define DKM_DRIVER_MAGIC 0x444B4D31u
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#define DKM_ABI_VERSION 1u
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typedef unsigned char u8;
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typedef unsigned short u16;
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typedef unsigned int u32;
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typedef unsigned long long u64;
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typedef long long i64;
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#define NULL ((void *)0)
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struct dkm_log_api {
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void (*info)(const char *msg);
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void (*warn)(const char *msg);
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void (*error)(const char *msg);
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void (*panic)(const char *msg);
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};
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struct dkm_dma_buffer {
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void *virt;
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u64 phys;
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u64 size;
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};
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struct dkm_dma_api {
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int (*alloc_pages)(u64 page_count, u64 alignment, u64 max_phys, struct dkm_dma_buffer *out);
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};
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struct dkm_block_device_desc {
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const char *name;
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u64 sector_size;
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u64 sector_count;
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void *ctx;
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int (*read)(void *ctx, u64 lba, u32 count, void *buffer);
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};
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struct dkm_block_api {
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int (*register_device)(const struct dkm_block_device_desc *desc);
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u32 (*device_count)(void);
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int (*read)(u32 index, u64 lba, u32 count, void *buffer);
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u64 (*sector_size)(u32 index);
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const char *(*device_name)(u32 index);
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};
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struct dkm_kernel_api {
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u32 version;
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u32 size;
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u64 feature_bits;
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const struct dkm_log_api *log;
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const void *mem;
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const void *utsm;
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const void *irq;
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const void *pci;
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const struct dkm_dma_api *dma;
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const void *vfs;
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const void *net;
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const void *timer;
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const void *drr;
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const void *rsdp_address;
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const void *fb_address;
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u64 fb_width;
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u64 fb_height;
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u64 fb_pitch;
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u16 fb_bpp;
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const void *boot_modules_response;
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int (*irq_register)(u8 irq, void *handler);
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u64 hhdm_offset;
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const struct dkm_block_api *block;
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};
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struct dkm_driver_handle;
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struct dkm_driver_desc {
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u32 magic;
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u16 abi_version;
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u16 desc_size;
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const char *name;
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const char *version;
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const char *vendor;
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u32 driver_class;
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u32 stage;
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u32 flags;
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u32 priority;
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const char *const *depends;
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u32 depends_count;
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const char *const *provides;
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u32 provides_count;
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u64 min_kernel_abi;
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u64 feature_bits;
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u64 reserved0;
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u64 reserved1;
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};
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#include "../dkm_shared.h"
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static const char *const g_depends[] = { "pci", "irq" };
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static const char *const g_provides[] = { "block" };
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@@ -124,21 +31,6 @@ const struct dkm_driver_desc driver_desc = {
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.reserved1 = 0
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};
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#define PCI_ADDR 0xCF8
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#define PCI_DATA 0xCFC
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#define PCI_VENDOR_ID 0x00
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#define PCI_COMMAND 0x04
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#define PCI_PROG_IF 0x09
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#define PCI_SUBCLASS 0x0A
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#define PCI_CLASS 0x0B
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#define PCI_HEADER 0x0E
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#define PCI_BAR5 0x24
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#define PCI_IRQ_LINE 0x3C
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#define PCI_CMD_IO (1u << 0)
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#define PCI_CMD_MEM (1u << 1)
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#define PCI_CMD_BUSM (1u << 2)
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#define AHCI_CLASS_STORAGE 0x01
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#define AHCI_SUBCLASS_SATA 0x06
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#define AHCI_PROGIF_AHCI 0x01
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@@ -170,12 +62,15 @@ const struct dkm_driver_desc driver_desc = {
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#define AHCI_CMD_ST (1u << 0)
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#define AHCI_CMD_FRE (1u << 4)
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#define AHCI_CMD_W (1u << 6)
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#define AHCI_CMD_FR (1u << 14)
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#define AHCI_CMD_CR (1u << 15)
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#define AHCI_CMD_ICC_ACTIVE (1u << 28)
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#define ATA_CMD_IDENTIFY 0xEC
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#define ATA_CMD_IDENTIFY_PACKET 0xA1
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#define ATA_CMD_READ_DMA_EXT 0x25
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#define ATA_CMD_WRITE_DMA_EXT 0x35
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typedef struct __attribute__((packed)) ahci_cmd_header {
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u16 flags;
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@@ -207,34 +102,12 @@ static ahci_cmd_header *g_cmd_header;
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static struct dkm_dma_buffer g_cmd_table;
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static struct dkm_dma_buffer g_data;
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static __inline__ void outl(u16 port, u32 value) {
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__asm__ volatile ("outl %0, %1" :: "a"(value), "Nd"(port));
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}
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static __inline__ u32 inl(u16 port) {
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u32 value;
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__asm__ volatile ("inl %1, %0" : "=a"(value) : "Nd"(port));
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return value;
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}
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static u32 pci_read(u8 bus, u8 dev, u8 func, u8 reg) {
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u32 addr = (1u << 31)
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| ((u32)bus << 16)
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| ((u32)dev << 11)
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| ((u32)func << 8)
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| ((u32)reg & 0xFC);
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outl(PCI_ADDR, addr);
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return inl(PCI_DATA);
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return dkm_pci_read(bus, dev, func, reg);
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}
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static void pci_write(u8 bus, u8 dev, u8 func, u8 reg, u32 value) {
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u32 addr = (1u << 31)
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| ((u32)bus << 16)
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| ((u32)dev << 11)
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| ((u32)func << 8)
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| ((u32)reg & 0xFC);
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outl(PCI_ADDR, addr);
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outl(PCI_DATA, value);
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dkm_pci_write(bus, dev, func, reg, value);
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}
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static void log_hex(const char *prefix, u64 value) {
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@@ -333,15 +206,21 @@ static int ahci_stop_port(u32 port) {
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u32 cmd = g_abar[(base + PxCMD) / 4];
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cmd &= ~AHCI_CMD_ST;
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g_abar[(base + PxCMD) / 4] = cmd;
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for (u32 i = 0; i < 100000; i++) {
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/* 实机: 500ms TSC 超时等待 CR 清除 */
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u64 deadline = dkm_rdtsc() + dkm_tsc_per_ms * 500;
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while (dkm_rdtsc() < deadline) {
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cmd = g_abar[(base + PxCMD) / 4];
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if (!(cmd & AHCI_CMD_CR)) break;
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__asm__ volatile("pause");
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}
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cmd &= ~AHCI_CMD_FRE;
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g_abar[(base + PxCMD) / 4] = cmd;
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for (u32 i = 0; i < 100000; i++) {
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/* 实机: 500ms TSC 超时等待 FR 清除 */
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deadline = dkm_rdtsc() + dkm_tsc_per_ms * 500;
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while (dkm_rdtsc() < deadline) {
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cmd = g_abar[(base + PxCMD) / 4];
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if (!(cmd & AHCI_CMD_FR)) return 0;
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__asm__ volatile("pause");
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}
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return -1;
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}
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@@ -368,7 +247,23 @@ static void ahci_fill_read_fis(u8 *fis, u64 lba, u32 count) {
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ahci_zero(fis, 64);
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fis[0] = 0x27;
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fis[1] = 1u << 7;
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fis[2] = 0x25; /* READ DMA EXT */
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fis[2] = ATA_CMD_READ_DMA_EXT;
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fis[4] = (u8)(lba & 0xff);
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fis[5] = (u8)((lba >> 8) & 0xff);
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fis[6] = (u8)((lba >> 16) & 0xff);
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fis[7] = (1u << 6) | (u8)((lba >> 24) & 0x0f);
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fis[8] = (u8)((lba >> 24) & 0xff);
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fis[9] = (u8)((lba >> 32) & 0xff);
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fis[10] = (u8)((lba >> 40) & 0xff);
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fis[12] = (u8)(count & 0xff);
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fis[13] = (u8)((count >> 8) & 0xff);
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}
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static void ahci_fill_write_fis(u8 *fis, u64 lba, u32 count) {
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ahci_zero(fis, 64);
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fis[0] = 0x27;
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fis[1] = 1u << 7;
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fis[2] = ATA_CMD_WRITE_DMA_EXT;
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fis[4] = (u8)(lba & 0xff);
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fis[5] = (u8)((lba >> 8) & 0xff);
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fis[6] = (u8)((lba >> 16) & 0xff);
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@@ -420,7 +315,81 @@ static int ahci_read_blocks_internal(u32 port, ahci_cmd_header *hdr, struct dkm_
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return -3;
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}
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static int ahci_write_blocks_internal(u32 port, ahci_cmd_header *hdr, struct dkm_dma_buffer *table, struct dkm_dma_buffer *data, u64 lba, u32 count, const void *buffer) {
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if (!buffer || count == 0) return -1;
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if (count > 8) return -2;
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u32 base = HBA_PORT_BASE + port * HBA_PORT_SIZE;
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ahci_cmd_table *tbl = (ahci_cmd_table *)table->virt;
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u32 bytes = count * 512;
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ahci_zero(tbl, sizeof(ahci_cmd_table));
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/* copy data from user buffer into DMA buffer */
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{
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u8 *dst = (u8 *)data->virt;
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const u8 *src = (const u8 *)buffer;
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for (u32 j = 0; j < bytes; j++) dst[j] = src[j];
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}
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hdr[0].flags = 5 | (1u << 6); /* CFL=5, W=1 (write) */
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hdr[0].prdtl = 1;
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hdr[0].prdbc = 0;
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hdr[0].ctba = (u32)(table->phys & 0xffffffffu);
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hdr[0].ctbau = (u32)(table->phys >> 32);
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tbl->prdt[0].dba = (u32)(data->phys & 0xffffffffu);
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tbl->prdt[0].dbau = (u32)(data->phys >> 32);
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tbl->prdt[0].dbc_i = (bytes - 1) | (1u << 31);
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ahci_fill_write_fis(tbl->cfis, lba, count);
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/* set PxCMD.W to indicate write direction */
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u32 cmd = g_abar[(base + PxCMD) / 4];
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cmd |= AHCI_CMD_W;
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g_abar[(base + PxCMD) / 4] = cmd;
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g_abar[(base + PxIS) / 4] = 0xffffffffu;
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g_abar[HBA_IS / 4] = (1u << port);
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g_abar[(base + PxCI) / 4] = 1;
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for (u32 i = 0; i < 5000000; i++) {
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if ((g_abar[(base + PxCI) / 4] & 1u) == 0) {
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/* clear PxCMD.W after write completes */
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cmd = g_abar[(base + PxCMD) / 4];
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cmd &= ~AHCI_CMD_W;
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g_abar[(base + PxCMD) / 4] = cmd;
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return 0;
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}
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}
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/* timeout: clear PxCMD.W */
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cmd = g_abar[(base + PxCMD) / 4];
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cmd &= ~AHCI_CMD_W;
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g_abar[(base + PxCMD) / 4] = cmd;
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g_log->warn("[ahci] WRITE timeout");
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log_hex("[ahci] WRITE lba=", lba);
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log_hex("[ahci] WRITE count=", count);
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log_hex("[ahci] WRITE CI=", g_abar[(base + PxCI) / 4]);
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log_hex("[ahci] WRITE IS=", g_abar[(base + PxIS) / 4]);
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log_hex("[ahci] WRITE TFD=", g_abar[(base + PxTFD) / 4]);
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return -3;
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}
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static int ahci_block_read(void *ctx, u64 lba, u32 count, void *buffer) {
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(void)ctx;
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if (g_ready_port == 0xffffffffu || !g_cmd_header) return -1;
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log_hex("[ahci] block_read lba=", lba);
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log_hex("[ahci] block_read count=", count);
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while (count > 0) {
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u32 chunk = count > 8 ? 8 : count;
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int status = ahci_read_blocks_internal(g_ready_port, g_cmd_header, &g_cmd_table, &g_data, lba, chunk, buffer);
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if (status != 0) return status;
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lba += chunk;
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count -= chunk;
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buffer = (void *)((u8 *)buffer + (chunk * 512));
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}
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return 0;
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}
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static int ahci_block_write(void *ctx, u64 lba, u32 count, const void *buffer) {
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(void)ctx;
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if (g_ready_port == 0xffffffffu || !g_cmd_header) return -1;
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/* ensure port is in ST+FRE state */
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@@ -433,11 +402,11 @@ static int ahci_block_read(void *ctx, u64 lba, u32 count, void *buffer) {
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}
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while (count > 0) {
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u32 chunk = count > 8 ? 8 : count;
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int status = ahci_read_blocks_internal(g_ready_port, g_cmd_header, &g_cmd_table, &g_data, lba, chunk, buffer);
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int status = ahci_write_blocks_internal(g_ready_port, g_cmd_header, &g_cmd_table, &g_data, lba, chunk, buffer);
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if (status != 0) return status;
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lba += chunk;
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count -= chunk;
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buffer = (void *)((u8 *)buffer + (chunk * 512));
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buffer = (const void *)((const u8 *)buffer + (chunk * 512));
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}
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return 0;
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}
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@@ -536,6 +505,8 @@ __attribute__((visibility("default")))
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int driver_init(const struct dkm_kernel_api *api,
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struct dkm_driver_handle *handle) {
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(void)handle;
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/* 实机要求: 先校准 TSC, 再使用基于 CPU 频率的延迟 */
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dkm_tsc_calibrate();
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if (!api || !api->log) return -1;
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g_log = api->log;
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@@ -628,6 +599,7 @@ int driver_init(const struct dkm_kernel_api *api,
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desc.sector_count = 0;
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desc.ctx = 0;
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desc.read = ahci_block_read;
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desc.write = ahci_block_write;
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int index = api->block->register_device(&desc);
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log_hex("[ahci] block provider index=", (u64)(i64)index);
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} else if (identified) {
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Reference in New Issue
Block a user